ARMInstrNEON.td revision e0053d22f825bf4749beaa282a4263e945aebcbc
1//===- ARMInstrNEON.td - NEON support for ARM -----------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM NEON instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// NEON-specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>; 19 20def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>; 21def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>; 22def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>; 23def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>; 24def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>; 25def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>; 26 27// Types for vector shift by immediates. The "SHX" version is for long and 28// narrow operations where the source and destination vectors have different 29// types. The "SHINS" version is for shift and insert operations. 30def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 31 SDTCisVT<2, i32>]>; 32def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, 33 SDTCisVT<2, i32>]>; 34def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; 36 37def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>; 38def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>; 39def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>; 40def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>; 41def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>; 42def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>; 43def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>; 44 45def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>; 46def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>; 47def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>; 48 49def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>; 50def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>; 51def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>; 52def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>; 53def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>; 54def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>; 55 56def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>; 57def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>; 58def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>; 59 60def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>; 61def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>; 62 63def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, 64 SDTCisVT<2, i32>]>; 65def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; 66def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; 67 68def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; 69 70// VDUPLANE can produce a quad-register result from a double-register source, 71// so the result is not constrained to match the source. 72def NEONvduplane : SDNode<"ARMISD::VDUPLANE", 73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 74 SDTCisVT<2, i32>]>>; 75 76def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; 78def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>; 79 80def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>; 81def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>; 82def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>; 83def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>; 84 85def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>; 87def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>; 88def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>; 89def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>; 90 91//===----------------------------------------------------------------------===// 92// NEON operand definitions 93//===----------------------------------------------------------------------===// 94 95// addrmode_neonldstm := reg 96// 97/* TODO: Take advantage of vldm. 98def addrmode_neonldstm : Operand<i32>, 99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> { 100 let PrintMethod = "printAddrNeonLdStMOperand"; 101 let MIOperandInfo = (ops GPR, i32imm); 102} 103*/ 104 105//===----------------------------------------------------------------------===// 106// NEON load / store instructions 107//===----------------------------------------------------------------------===// 108 109/* TODO: Take advantage of vldm. 110let mayLoad = 1, hasExtraDefRegAllocReq = 1 in { 111def VLDMD : NI<(outs), 112 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), 113 IIC_fpLoadm, 114 "vldm${addr:submode} ${addr:base}, $dst1", 115 []> { 116 let Inst{27-25} = 0b110; 117 let Inst{20} = 1; 118 let Inst{11-9} = 0b101; 119} 120 121def VLDMS : NI<(outs), 122 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), 123 IIC_fpLoadm, 124 "vldm${addr:submode} ${addr:base}, $dst1", 125 []> { 126 let Inst{27-25} = 0b110; 127 let Inst{20} = 1; 128 let Inst{11-9} = 0b101; 129} 130} 131*/ 132 133// Use vldmia to load a Q register as a D register pair. 134def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), 135 IIC_fpLoadm, 136 "vldmia $addr, ${dst:dregpair}", 137 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> { 138 let Inst{27-25} = 0b110; 139 let Inst{24} = 0; // P bit 140 let Inst{23} = 1; // U bit 141 let Inst{20} = 1; 142 let Inst{11-9} = 0b101; 143} 144 145// Use vstmia to store a Q register as a D register pair. 146def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), 147 IIC_fpStorem, 148 "vstmia $addr, ${src:dregpair}", 149 [(store (v2f64 QPR:$src), addrmode4:$addr)]> { 150 let Inst{27-25} = 0b110; 151 let Inst{24} = 0; // P bit 152 let Inst{23} = 1; // U bit 153 let Inst{20} = 0; 154 let Inst{11-9} = 0b101; 155} 156 157// VLD1 : Vector Load (multiple single elements) 158class VLD1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> 159 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1, 160 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "", 161 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>; 162class VLD1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> 163 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1, 164 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "", 165 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>; 166 167def VLD1d8 : VLD1D<0b0000, "vld1.8", v8i8, int_arm_neon_vld1>; 168def VLD1d16 : VLD1D<0b0100, "vld1.16", v4i16, int_arm_neon_vld1>; 169def VLD1d32 : VLD1D<0b1000, "vld1.32", v2i32, int_arm_neon_vld1>; 170def VLD1df : VLD1D<0b1000, "vld1.32", v2f32, int_arm_neon_vld1>; 171def VLD1d64 : VLD1D<0b1100, "vld1.64", v1i64, int_arm_neon_vld1>; 172 173def VLD1q8 : VLD1Q<0b0000, "vld1.8", v16i8, int_arm_neon_vld1>; 174def VLD1q16 : VLD1Q<0b0100, "vld1.16", v8i16, int_arm_neon_vld1>; 175def VLD1q32 : VLD1Q<0b1000, "vld1.32", v4i32, int_arm_neon_vld1>; 176def VLD1qf : VLD1Q<0b1000, "vld1.32", v4f32, int_arm_neon_vld1>; 177def VLD1q64 : VLD1Q<0b1100, "vld1.64", v2i64, int_arm_neon_vld1>; 178 179let mayLoad = 1, hasExtraDefRegAllocReq = 1 in { 180 181// VLD2 : Vector Load (multiple 2-element structures) 182class VLD2D<bits<4> op7_4, string OpcodeStr> 183 : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2), 184 (ins addrmode6:$addr), IIC_VLD2, 185 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>; 186class VLD2Q<bits<4> op7_4, string OpcodeStr> 187 : NLdSt<0,0b10,0b0011,op7_4, 188 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), 189 (ins addrmode6:$addr), IIC_VLD2, 190 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), 191 "", []>; 192 193def VLD2d8 : VLD2D<0b0000, "vld2.8">; 194def VLD2d16 : VLD2D<0b0100, "vld2.16">; 195def VLD2d32 : VLD2D<0b1000, "vld2.32">; 196def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2), 197 (ins addrmode6:$addr), IIC_VLD1, 198 "vld1.64\t\\{$dst1,$dst2\\}, $addr", "", []>; 199 200def VLD2q8 : VLD2Q<0b0000, "vld2.8">; 201def VLD2q16 : VLD2Q<0b0100, "vld2.16">; 202def VLD2q32 : VLD2Q<0b1000, "vld2.32">; 203 204// VLD3 : Vector Load (multiple 3-element structures) 205class VLD3D<bits<4> op7_4, string OpcodeStr> 206 : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), 207 (ins addrmode6:$addr), IIC_VLD3, 208 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>; 209class VLD3WB<bits<4> op7_4, string OpcodeStr> 210 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb), 211 (ins addrmode6:$addr), IIC_VLD3, 212 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), 213 "$addr.addr = $wb", []>; 214 215def VLD3d8 : VLD3D<0b0000, "vld3.8">; 216def VLD3d16 : VLD3D<0b0100, "vld3.16">; 217def VLD3d32 : VLD3D<0b1000, "vld3.32">; 218def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100, 219 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), 220 (ins addrmode6:$addr), IIC_VLD1, 221 "vld1.64\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>; 222 223// vld3 to double-spaced even registers. 224def VLD3q8a : VLD3WB<0b0000, "vld3.8">; 225def VLD3q16a : VLD3WB<0b0100, "vld3.16">; 226def VLD3q32a : VLD3WB<0b1000, "vld3.32">; 227 228// vld3 to double-spaced odd registers. 229def VLD3q8b : VLD3WB<0b0000, "vld3.8">; 230def VLD3q16b : VLD3WB<0b0100, "vld3.16">; 231def VLD3q32b : VLD3WB<0b1000, "vld3.32">; 232 233// VLD4 : Vector Load (multiple 4-element structures) 234class VLD4D<bits<4> op7_4, string OpcodeStr> 235 : NLdSt<0,0b10,0b0000,op7_4, 236 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), 237 (ins addrmode6:$addr), IIC_VLD4, 238 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), 239 "", []>; 240class VLD4WB<bits<4> op7_4, string OpcodeStr> 241 : NLdSt<0,0b10,0b0001,op7_4, 242 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), 243 (ins addrmode6:$addr), IIC_VLD4, 244 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), 245 "$addr.addr = $wb", []>; 246 247def VLD4d8 : VLD4D<0b0000, "vld4.8">; 248def VLD4d16 : VLD4D<0b0100, "vld4.16">; 249def VLD4d32 : VLD4D<0b1000, "vld4.32">; 250def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100, 251 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), 252 (ins addrmode6:$addr), IIC_VLD1, 253 "vld1.64\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>; 254 255// vld4 to double-spaced even registers. 256def VLD4q8a : VLD4WB<0b0000, "vld4.8">; 257def VLD4q16a : VLD4WB<0b0100, "vld4.16">; 258def VLD4q32a : VLD4WB<0b1000, "vld4.32">; 259 260// vld4 to double-spaced odd registers. 261def VLD4q8b : VLD4WB<0b0000, "vld4.8">; 262def VLD4q16b : VLD4WB<0b0100, "vld4.16">; 263def VLD4q32b : VLD4WB<0b1000, "vld4.32">; 264 265// VLD1LN : Vector Load (single element to one lane) 266// FIXME: Not yet implemented. 267 268// VLD2LN : Vector Load (single 2-element structure to one lane) 269class VLD2LN<bits<4> op11_8, string OpcodeStr> 270 : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2), 271 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), 272 IIC_VLD2, 273 !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"), 274 "$src1 = $dst1, $src2 = $dst2", []>; 275 276def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">; 277def VLD2LNd16 : VLD2LN<0b0101, "vld2.16">; 278def VLD2LNd32 : VLD2LN<0b1001, "vld2.32">; 279 280// vld2 to double-spaced even registers. 281def VLD2LNq16a: VLD2LN<0b0101, "vld2.16">; 282def VLD2LNq32a: VLD2LN<0b1001, "vld2.32">; 283 284// vld2 to double-spaced odd registers. 285def VLD2LNq16b: VLD2LN<0b0101, "vld2.16">; 286def VLD2LNq32b: VLD2LN<0b1001, "vld2.32">; 287 288// VLD3LN : Vector Load (single 3-element structure to one lane) 289class VLD3LN<bits<4> op11_8, string OpcodeStr> 290 : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), 291 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, 292 nohash_imm:$lane), IIC_VLD3, 293 !strconcat(OpcodeStr, 294 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"), 295 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; 296 297def VLD3LNd8 : VLD3LN<0b0010, "vld3.8">; 298def VLD3LNd16 : VLD3LN<0b0110, "vld3.16">; 299def VLD3LNd32 : VLD3LN<0b1010, "vld3.32">; 300 301// vld3 to double-spaced even registers. 302def VLD3LNq16a: VLD3LN<0b0110, "vld3.16">; 303def VLD3LNq32a: VLD3LN<0b1010, "vld3.32">; 304 305// vld3 to double-spaced odd registers. 306def VLD3LNq16b: VLD3LN<0b0110, "vld3.16">; 307def VLD3LNq32b: VLD3LN<0b1010, "vld3.32">; 308 309// VLD4LN : Vector Load (single 4-element structure to one lane) 310class VLD4LN<bits<4> op11_8, string OpcodeStr> 311 : NLdSt<1,0b10,op11_8,0b0000, 312 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), 313 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, 314 nohash_imm:$lane), IIC_VLD4, 315 !strconcat(OpcodeStr, 316 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"), 317 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>; 318 319def VLD4LNd8 : VLD4LN<0b0011, "vld4.8">; 320def VLD4LNd16 : VLD4LN<0b0111, "vld4.16">; 321def VLD4LNd32 : VLD4LN<0b1011, "vld4.32">; 322 323// vld4 to double-spaced even registers. 324def VLD4LNq16a: VLD4LN<0b0111, "vld4.16">; 325def VLD4LNq32a: VLD4LN<0b1011, "vld4.32">; 326 327// vld4 to double-spaced odd registers. 328def VLD4LNq16b: VLD4LN<0b0111, "vld4.16">; 329def VLD4LNq32b: VLD4LN<0b1011, "vld4.32">; 330 331// VLD1DUP : Vector Load (single element to all lanes) 332// VLD2DUP : Vector Load (single 2-element structure to all lanes) 333// VLD3DUP : Vector Load (single 3-element structure to all lanes) 334// VLD4DUP : Vector Load (single 4-element structure to all lanes) 335// FIXME: Not yet implemented. 336} // mayLoad = 1, hasExtraDefRegAllocReq = 1 337 338// VST1 : Vector Store (multiple single elements) 339class VST1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> 340 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST, 341 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "", 342 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>; 343class VST1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> 344 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST, 345 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "", 346 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>; 347 348let hasExtraSrcRegAllocReq = 1 in { 349def VST1d8 : VST1D<0b0000, "vst1.8", v8i8, int_arm_neon_vst1>; 350def VST1d16 : VST1D<0b0100, "vst1.16", v4i16, int_arm_neon_vst1>; 351def VST1d32 : VST1D<0b1000, "vst1.32", v2i32, int_arm_neon_vst1>; 352def VST1df : VST1D<0b1000, "vst1.32", v2f32, int_arm_neon_vst1>; 353def VST1d64 : VST1D<0b1100, "vst1.64", v1i64, int_arm_neon_vst1>; 354 355def VST1q8 : VST1Q<0b0000, "vst1.8", v16i8, int_arm_neon_vst1>; 356def VST1q16 : VST1Q<0b0100, "vst1.16", v8i16, int_arm_neon_vst1>; 357def VST1q32 : VST1Q<0b1000, "vst1.32", v4i32, int_arm_neon_vst1>; 358def VST1qf : VST1Q<0b1000, "vst1.32", v4f32, int_arm_neon_vst1>; 359def VST1q64 : VST1Q<0b1100, "vst1.64", v2i64, int_arm_neon_vst1>; 360} // hasExtraSrcRegAllocReq 361 362let mayStore = 1, hasExtraSrcRegAllocReq = 1 in { 363 364// VST2 : Vector Store (multiple 2-element structures) 365class VST2D<bits<4> op7_4, string OpcodeStr> 366 : NLdSt<0,0b00,0b1000,op7_4, (outs), 367 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST, 368 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>; 369class VST2Q<bits<4> op7_4, string OpcodeStr> 370 : NLdSt<0,0b00,0b0011,op7_4, (outs), 371 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), 372 IIC_VST, 373 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), 374 "", []>; 375 376def VST2d8 : VST2D<0b0000, "vst2.8">; 377def VST2d16 : VST2D<0b0100, "vst2.16">; 378def VST2d32 : VST2D<0b1000, "vst2.32">; 379def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs), 380 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST, 381 "vst1.64\t\\{$src1,$src2\\}, $addr", "", []>; 382 383def VST2q8 : VST2Q<0b0000, "vst2.8">; 384def VST2q16 : VST2Q<0b0100, "vst2.16">; 385def VST2q32 : VST2Q<0b1000, "vst2.32">; 386 387// VST3 : Vector Store (multiple 3-element structures) 388class VST3D<bits<4> op7_4, string OpcodeStr> 389 : NLdSt<0,0b00,0b0100,op7_4, (outs), 390 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST, 391 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>; 392class VST3WB<bits<4> op7_4, string OpcodeStr> 393 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb), 394 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST, 395 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), 396 "$addr.addr = $wb", []>; 397 398def VST3d8 : VST3D<0b0000, "vst3.8">; 399def VST3d16 : VST3D<0b0100, "vst3.16">; 400def VST3d32 : VST3D<0b1000, "vst3.32">; 401def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs), 402 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), 403 IIC_VST, 404 "vst1.64\t\\{$src1,$src2,$src3\\}, $addr", "", []>; 405 406// vst3 to double-spaced even registers. 407def VST3q8a : VST3WB<0b0000, "vst3.8">; 408def VST3q16a : VST3WB<0b0100, "vst3.16">; 409def VST3q32a : VST3WB<0b1000, "vst3.32">; 410 411// vst3 to double-spaced odd registers. 412def VST3q8b : VST3WB<0b0000, "vst3.8">; 413def VST3q16b : VST3WB<0b0100, "vst3.16">; 414def VST3q32b : VST3WB<0b1000, "vst3.32">; 415 416// VST4 : Vector Store (multiple 4-element structures) 417class VST4D<bits<4> op7_4, string OpcodeStr> 418 : NLdSt<0,0b00,0b0000,op7_4, (outs), 419 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), 420 IIC_VST, 421 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), 422 "", []>; 423class VST4WB<bits<4> op7_4, string OpcodeStr> 424 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb), 425 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), 426 IIC_VST, 427 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), 428 "$addr.addr = $wb", []>; 429 430def VST4d8 : VST4D<0b0000, "vst4.8">; 431def VST4d16 : VST4D<0b0100, "vst4.16">; 432def VST4d32 : VST4D<0b1000, "vst4.32">; 433def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs), 434 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, 435 DPR:$src4), IIC_VST, 436 "vst1.64\t\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>; 437 438// vst4 to double-spaced even registers. 439def VST4q8a : VST4WB<0b0000, "vst4.8">; 440def VST4q16a : VST4WB<0b0100, "vst4.16">; 441def VST4q32a : VST4WB<0b1000, "vst4.32">; 442 443// vst4 to double-spaced odd registers. 444def VST4q8b : VST4WB<0b0000, "vst4.8">; 445def VST4q16b : VST4WB<0b0100, "vst4.16">; 446def VST4q32b : VST4WB<0b1000, "vst4.32">; 447 448// VST1LN : Vector Store (single element from one lane) 449// FIXME: Not yet implemented. 450 451// VST2LN : Vector Store (single 2-element structure from one lane) 452class VST2LN<bits<4> op11_8, string OpcodeStr> 453 : NLdSt<1,0b00,op11_8,0b0000, (outs), 454 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), 455 IIC_VST, 456 !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"), 457 "", []>; 458 459def VST2LNd8 : VST2LN<0b0000, "vst2.8">; 460def VST2LNd16 : VST2LN<0b0100, "vst2.16">; 461def VST2LNd32 : VST2LN<0b1000, "vst2.32">; 462 463// vst2 to double-spaced even registers. 464def VST2LNq16a: VST2LN<0b0100, "vst2.16">; 465def VST2LNq32a: VST2LN<0b1000, "vst2.32">; 466 467// vst2 to double-spaced odd registers. 468def VST2LNq16b: VST2LN<0b0100, "vst2.16">; 469def VST2LNq32b: VST2LN<0b1000, "vst2.32">; 470 471// VST3LN : Vector Store (single 3-element structure from one lane) 472class VST3LN<bits<4> op11_8, string OpcodeStr> 473 : NLdSt<1,0b00,op11_8,0b0000, (outs), 474 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, 475 nohash_imm:$lane), IIC_VST, 476 !strconcat(OpcodeStr, 477 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>; 478 479def VST3LNd8 : VST3LN<0b0010, "vst3.8">; 480def VST3LNd16 : VST3LN<0b0110, "vst3.16">; 481def VST3LNd32 : VST3LN<0b1010, "vst3.32">; 482 483// vst3 to double-spaced even registers. 484def VST3LNq16a: VST3LN<0b0110, "vst3.16">; 485def VST3LNq32a: VST3LN<0b1010, "vst3.32">; 486 487// vst3 to double-spaced odd registers. 488def VST3LNq16b: VST3LN<0b0110, "vst3.16">; 489def VST3LNq32b: VST3LN<0b1010, "vst3.32">; 490 491// VST4LN : Vector Store (single 4-element structure from one lane) 492class VST4LN<bits<4> op11_8, string OpcodeStr> 493 : NLdSt<1,0b00,op11_8,0b0000, (outs), 494 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, 495 nohash_imm:$lane), IIC_VST, 496 !strconcat(OpcodeStr, 497 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"), 498 "", []>; 499 500def VST4LNd8 : VST4LN<0b0011, "vst4.8">; 501def VST4LNd16 : VST4LN<0b0111, "vst4.16">; 502def VST4LNd32 : VST4LN<0b1011, "vst4.32">; 503 504// vst4 to double-spaced even registers. 505def VST4LNq16a: VST4LN<0b0111, "vst4.16">; 506def VST4LNq32a: VST4LN<0b1011, "vst4.32">; 507 508// vst4 to double-spaced odd registers. 509def VST4LNq16b: VST4LN<0b0111, "vst4.16">; 510def VST4LNq32b: VST4LN<0b1011, "vst4.32">; 511 512} // mayStore = 1, hasExtraSrcRegAllocReq = 1 513 514 515//===----------------------------------------------------------------------===// 516// NEON pattern fragments 517//===----------------------------------------------------------------------===// 518 519// Extract D sub-registers of Q registers. 520// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6) 521def DSubReg_i8_reg : SDNodeXForm<imm, [{ 522 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32); 523}]>; 524def DSubReg_i16_reg : SDNodeXForm<imm, [{ 525 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32); 526}]>; 527def DSubReg_i32_reg : SDNodeXForm<imm, [{ 528 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32); 529}]>; 530def DSubReg_f64_reg : SDNodeXForm<imm, [{ 531 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32); 532}]>; 533def DSubReg_f64_other_reg : SDNodeXForm<imm, [{ 534 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32); 535}]>; 536 537// Extract S sub-registers of Q/D registers. 538// (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.) 539def SSubReg_f32_reg : SDNodeXForm<imm, [{ 540 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32); 541}]>; 542 543// Translate lane numbers from Q registers to D subregs. 544def SubReg_i8_lane : SDNodeXForm<imm, [{ 545 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32); 546}]>; 547def SubReg_i16_lane : SDNodeXForm<imm, [{ 548 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32); 549}]>; 550def SubReg_i32_lane : SDNodeXForm<imm, [{ 551 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32); 552}]>; 553 554//===----------------------------------------------------------------------===// 555// Instruction Classes 556//===----------------------------------------------------------------------===// 557 558// Basic 2-register operations, both double- and quad-register. 559class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 560 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 561 ValueType ResTy, ValueType OpTy, SDNode OpNode> 562 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst), 563 (ins DPR:$src), IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "", 564 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>; 565class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 566 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 567 ValueType ResTy, ValueType OpTy, SDNode OpNode> 568 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst), 569 (ins QPR:$src), IIC_VUNAQ, !strconcat(OpcodeStr, "\t$dst, $src"), "", 570 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>; 571 572// Basic 2-register operations, scalar single-precision. 573class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 574 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 575 ValueType ResTy, ValueType OpTy, SDNode OpNode> 576 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, 577 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), 578 IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>; 579 580class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst> 581 : NEONFPPat<(ResTy (OpNode SPR:$a)), 582 (EXTRACT_SUBREG 583 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)), 584 arm_ssubreg_0)>; 585 586// Basic 2-register intrinsics, both double- and quad-register. 587class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 588 bits<2> op17_16, bits<5> op11_7, bit op4, 589 InstrItinClass itin, string OpcodeStr, 590 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 591 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst), 592 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "", 593 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>; 594class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 595 bits<2> op17_16, bits<5> op11_7, bit op4, 596 InstrItinClass itin, string OpcodeStr, 597 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 598 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst), 599 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "", 600 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>; 601 602// Basic 2-register intrinsics, scalar single-precision 603class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 604 bits<2> op17_16, bits<5> op11_7, bit op4, 605 InstrItinClass itin, string OpcodeStr, 606 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 607 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, 608 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin, 609 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>; 610 611class N2VDIntsPat<SDNode OpNode, NeonI Inst> 612 : NEONFPPat<(f32 (OpNode SPR:$a)), 613 (EXTRACT_SUBREG 614 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)), 615 arm_ssubreg_0)>; 616 617// Narrow 2-register intrinsics. 618class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 619 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, 620 InstrItinClass itin, string OpcodeStr, 621 ValueType TyD, ValueType TyQ, Intrinsic IntOp> 622 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst), 623 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "", 624 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>; 625 626// Long 2-register intrinsics (currently only used for VMOVL). 627class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 628 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, 629 InstrItinClass itin, string OpcodeStr, 630 ValueType TyQ, ValueType TyD, Intrinsic IntOp> 631 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst), 632 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "", 633 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>; 634 635// 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register. 636class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr> 637 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2), 638 (ins DPR:$src1, DPR:$src2), IIC_VPERMD, 639 !strconcat(OpcodeStr, "\t$dst1, $dst2"), 640 "$src1 = $dst1, $src2 = $dst2", []>; 641class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, 642 InstrItinClass itin, string OpcodeStr> 643 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2), 644 (ins QPR:$src1, QPR:$src2), itin, 645 !strconcat(OpcodeStr, "\t$dst1, $dst2"), 646 "$src1 = $dst1, $src2 = $dst2", []>; 647 648// Basic 3-register operations, both double- and quad-register. 649class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 650 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy, 651 SDNode OpNode, bit Commutable> 652 : N3V<op24, op23, op21_20, op11_8, 0, op4, 653 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin, 654 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 655 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> { 656 let isCommutable = Commutable; 657} 658class N3VDSL<bits<2> op21_20, bits<4> op11_8, 659 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode ShOp> 660 : N3V<0, 1, op21_20, op11_8, 1, 0, 661 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), 662 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", 663 [(set (Ty DPR:$dst), 664 (Ty (ShOp (Ty DPR:$src1), 665 (Ty (NEONvduplane (Ty DPR_VFP2:$src2), 666 imm:$lane)))))]> { 667 let isCommutable = 0; 668} 669class N3VDSL16<bits<2> op21_20, bits<4> op11_8, 670 string OpcodeStr, ValueType Ty, SDNode ShOp> 671 : N3V<0, 1, op21_20, op11_8, 1, 0, 672 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane), 673 IIC_VMULi16D, 674 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", 675 [(set (Ty DPR:$dst), 676 (Ty (ShOp (Ty DPR:$src1), 677 (Ty (NEONvduplane (Ty DPR_8:$src2), 678 imm:$lane)))))]> { 679 let isCommutable = 0; 680} 681 682class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 683 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy, 684 SDNode OpNode, bit Commutable> 685 : N3V<op24, op23, op21_20, op11_8, 1, op4, 686 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin, 687 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 688 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> { 689 let isCommutable = Commutable; 690} 691class N3VQSL<bits<2> op21_20, bits<4> op11_8, 692 InstrItinClass itin, string OpcodeStr, 693 ValueType ResTy, ValueType OpTy, SDNode ShOp> 694 : N3V<1, 1, op21_20, op11_8, 1, 0, 695 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), 696 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", 697 [(set (ResTy QPR:$dst), 698 (ResTy (ShOp (ResTy QPR:$src1), 699 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2), 700 imm:$lane)))))]> { 701 let isCommutable = 0; 702} 703class N3VQSL16<bits<2> op21_20, bits<4> op11_8, 704 string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode ShOp> 705 : N3V<1, 1, op21_20, op11_8, 1, 0, 706 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane), 707 IIC_VMULi16Q, 708 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", 709 [(set (ResTy QPR:$dst), 710 (ResTy (ShOp (ResTy QPR:$src1), 711 (ResTy (NEONvduplane (OpTy DPR_8:$src2), 712 imm:$lane)))))]> { 713 let isCommutable = 0; 714} 715 716// Basic 3-register operations, scalar single-precision 717class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 718 string OpcodeStr, ValueType ResTy, ValueType OpTy, 719 SDNode OpNode, bit Commutable> 720 : N3V<op24, op23, op21_20, op11_8, 0, op4, 721 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND, 722 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> { 723 let isCommutable = Commutable; 724} 725class N3VDsPat<SDNode OpNode, NeonI Inst> 726 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)), 727 (EXTRACT_SUBREG 728 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0), 729 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)), 730 arm_ssubreg_0)>; 731 732// Basic 3-register intrinsics, both double- and quad-register. 733class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 734 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy, 735 Intrinsic IntOp, bit Commutable> 736 : N3V<op24, op23, op21_20, op11_8, 0, op4, 737 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin, 738 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 739 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> { 740 let isCommutable = Commutable; 741} 742class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 743 string OpcodeStr, ValueType Ty, Intrinsic IntOp> 744 : N3V<0, 1, op21_20, op11_8, 1, 0, 745 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), 746 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", 747 [(set (Ty DPR:$dst), 748 (Ty (IntOp (Ty DPR:$src1), 749 (Ty (NEONvduplane (Ty DPR_VFP2:$src2), 750 imm:$lane)))))]> { 751 let isCommutable = 0; 752} 753class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 754 string OpcodeStr, ValueType Ty, Intrinsic IntOp> 755 : N3V<0, 1, op21_20, op11_8, 1, 0, 756 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane), 757 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", 758 [(set (Ty DPR:$dst), 759 (Ty (IntOp (Ty DPR:$src1), 760 (Ty (NEONvduplane (Ty DPR_8:$src2), 761 imm:$lane)))))]> { 762 let isCommutable = 0; 763} 764 765class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 766 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy, 767 Intrinsic IntOp, bit Commutable> 768 : N3V<op24, op23, op21_20, op11_8, 1, op4, 769 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin, 770 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 771 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> { 772 let isCommutable = Commutable; 773} 774class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 775 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 776 : N3V<1, 1, op21_20, op11_8, 1, 0, 777 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), 778 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", 779 [(set (ResTy QPR:$dst), 780 (ResTy (IntOp (ResTy QPR:$src1), 781 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2), 782 imm:$lane)))))]> { 783 let isCommutable = 0; 784} 785class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 786 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 787 : N3V<1, 1, op21_20, op11_8, 1, 0, 788 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane), 789 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", 790 [(set (ResTy QPR:$dst), 791 (ResTy (IntOp (ResTy QPR:$src1), 792 (ResTy (NEONvduplane (OpTy DPR_8:$src2), 793 imm:$lane)))))]> { 794 let isCommutable = 0; 795} 796 797// Multiply-Add/Sub operations, both double- and quad-register. 798class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 799 InstrItinClass itin, string OpcodeStr, 800 ValueType Ty, SDNode MulOp, SDNode OpNode> 801 : N3V<op24, op23, op21_20, op11_8, 0, op4, 802 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin, 803 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 804 [(set DPR:$dst, (Ty (OpNode DPR:$src1, 805 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>; 806class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 807 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp> 808 : N3V<0, 1, op21_20, op11_8, 1, 0, 809 (outs DPR:$dst), 810 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin, 811 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", 812 [(set (Ty DPR:$dst), 813 (Ty (ShOp (Ty DPR:$src1), 814 (Ty (MulOp DPR:$src2, 815 (Ty (NEONvduplane (Ty DPR_VFP2:$src3), 816 imm:$lane)))))))]>; 817class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 818 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp> 819 : N3V<0, 1, op21_20, op11_8, 1, 0, 820 (outs DPR:$dst), 821 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin, 822 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", 823 [(set (Ty DPR:$dst), 824 (Ty (ShOp (Ty DPR:$src1), 825 (Ty (MulOp DPR:$src2, 826 (Ty (NEONvduplane (Ty DPR_8:$src3), 827 imm:$lane)))))))]>; 828 829class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 830 InstrItinClass itin, string OpcodeStr, ValueType Ty, 831 SDNode MulOp, SDNode OpNode> 832 : N3V<op24, op23, op21_20, op11_8, 1, op4, 833 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin, 834 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 835 [(set QPR:$dst, (Ty (OpNode QPR:$src1, 836 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>; 837class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 838 string OpcodeStr, ValueType ResTy, ValueType OpTy, 839 SDNode MulOp, SDNode ShOp> 840 : N3V<1, 1, op21_20, op11_8, 1, 0, 841 (outs QPR:$dst), 842 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin, 843 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", 844 [(set (ResTy QPR:$dst), 845 (ResTy (ShOp (ResTy QPR:$src1), 846 (ResTy (MulOp QPR:$src2, 847 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3), 848 imm:$lane)))))))]>; 849class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 850 string OpcodeStr, ValueType ResTy, ValueType OpTy, 851 SDNode MulOp, SDNode ShOp> 852 : N3V<1, 1, op21_20, op11_8, 1, 0, 853 (outs QPR:$dst), 854 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin, 855 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", 856 [(set (ResTy QPR:$dst), 857 (ResTy (ShOp (ResTy QPR:$src1), 858 (ResTy (MulOp QPR:$src2, 859 (ResTy (NEONvduplane (OpTy DPR_8:$src3), 860 imm:$lane)))))))]>; 861 862// Multiply-Add/Sub operations, scalar single-precision 863class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 864 InstrItinClass itin, string OpcodeStr, 865 ValueType Ty, SDNode MulOp, SDNode OpNode> 866 : N3V<op24, op23, op21_20, op11_8, 0, op4, 867 (outs DPR_VFP2:$dst), 868 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin, 869 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>; 870 871class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst> 872 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))), 873 (EXTRACT_SUBREG 874 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0), 875 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0), 876 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)), 877 arm_ssubreg_0)>; 878 879// Neon 3-argument intrinsics, both double- and quad-register. 880// The destination register is also used as the first source operand register. 881class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 882 InstrItinClass itin, string OpcodeStr, 883 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 884 : N3V<op24, op23, op21_20, op11_8, 0, op4, 885 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin, 886 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 887 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), 888 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>; 889class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 890 InstrItinClass itin, string OpcodeStr, 891 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 892 : N3V<op24, op23, op21_20, op11_8, 1, op4, 893 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin, 894 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 895 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), 896 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>; 897 898// Neon Long 3-argument intrinsic. The destination register is 899// a quad-register and is also used as the first source operand register. 900class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 901 InstrItinClass itin, string OpcodeStr, 902 ValueType TyQ, ValueType TyD, Intrinsic IntOp> 903 : N3V<op24, op23, op21_20, op11_8, 0, op4, 904 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin, 905 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 906 [(set QPR:$dst, 907 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>; 908class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 909 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 910 : N3V<op24, 1, op21_20, op11_8, 1, 0, 911 (outs QPR:$dst), 912 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin, 913 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", 914 [(set (ResTy QPR:$dst), 915 (ResTy (IntOp (ResTy QPR:$src1), 916 (OpTy DPR:$src2), 917 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3), 918 imm:$lane)))))]>; 919class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 920 string OpcodeStr, ValueType ResTy, ValueType OpTy, 921 Intrinsic IntOp> 922 : N3V<op24, 1, op21_20, op11_8, 1, 0, 923 (outs QPR:$dst), 924 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin, 925 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", 926 [(set (ResTy QPR:$dst), 927 (ResTy (IntOp (ResTy QPR:$src1), 928 (OpTy DPR:$src2), 929 (OpTy (NEONvduplane (OpTy DPR_8:$src3), 930 imm:$lane)))))]>; 931 932 933// Narrowing 3-register intrinsics. 934class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 935 string OpcodeStr, ValueType TyD, ValueType TyQ, 936 Intrinsic IntOp, bit Commutable> 937 : N3V<op24, op23, op21_20, op11_8, 0, op4, 938 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D, 939 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 940 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> { 941 let isCommutable = Commutable; 942} 943 944// Long 3-register intrinsics. 945class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 946 InstrItinClass itin, string OpcodeStr, ValueType TyQ, ValueType TyD, 947 Intrinsic IntOp, bit Commutable> 948 : N3V<op24, op23, op21_20, op11_8, 0, op4, 949 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin, 950 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 951 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> { 952 let isCommutable = Commutable; 953} 954class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 955 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 956 : N3V<op24, 1, op21_20, op11_8, 1, 0, 957 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), 958 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", 959 [(set (ResTy QPR:$dst), 960 (ResTy (IntOp (OpTy DPR:$src1), 961 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2), 962 imm:$lane)))))]>; 963class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 964 string OpcodeStr, ValueType ResTy, ValueType OpTy, 965 Intrinsic IntOp> 966 : N3V<op24, 1, op21_20, op11_8, 1, 0, 967 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane), 968 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", 969 [(set (ResTy QPR:$dst), 970 (ResTy (IntOp (OpTy DPR:$src1), 971 (OpTy (NEONvduplane (OpTy DPR_8:$src2), 972 imm:$lane)))))]>; 973 974// Wide 3-register intrinsics. 975class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 976 string OpcodeStr, ValueType TyQ, ValueType TyD, 977 Intrinsic IntOp, bit Commutable> 978 : N3V<op24, op23, op21_20, op11_8, 0, op4, 979 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD, 980 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 981 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> { 982 let isCommutable = Commutable; 983} 984 985// Pairwise long 2-register intrinsics, both double- and quad-register. 986class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 987 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 988 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 989 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst), 990 (ins DPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "", 991 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>; 992class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 993 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 994 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 995 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst), 996 (ins QPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "", 997 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>; 998 999// Pairwise long 2-register accumulate intrinsics, 1000// both double- and quad-register. 1001// The destination register is also used as the first source operand register. 1002class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 1003 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 1004 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 1005 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, 1006 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD, 1007 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst", 1008 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>; 1009class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 1010 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 1011 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 1012 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, 1013 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ, 1014 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst", 1015 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>; 1016 1017// Shift by immediate, 1018// both double- and quad-register. 1019class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 1020 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode> 1021 : N2VImm<op24, op23, op11_8, op7, 0, op4, 1022 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin, 1023 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 1024 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>; 1025class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 1026 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode> 1027 : N2VImm<op24, op23, op11_8, op7, 1, op4, 1028 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin, 1029 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 1030 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>; 1031 1032// Long shift by immediate. 1033class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1034 string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode OpNode> 1035 : N2VImm<op24, op23, op11_8, op7, op6, op4, 1036 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD, 1037 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 1038 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src), 1039 (i32 imm:$SIMM))))]>; 1040 1041// Narrow shift by immediate. 1042class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1043 InstrItinClass itin, string OpcodeStr, 1044 ValueType ResTy, ValueType OpTy, SDNode OpNode> 1045 : N2VImm<op24, op23, op11_8, op7, op6, op4, 1046 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin, 1047 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 1048 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src), 1049 (i32 imm:$SIMM))))]>; 1050 1051// Shift right by immediate and accumulate, 1052// both double- and quad-register. 1053class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 1054 string OpcodeStr, ValueType Ty, SDNode ShOp> 1055 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst), 1056 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD, 1057 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 1058 [(set DPR:$dst, (Ty (add DPR:$src1, 1059 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>; 1060class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 1061 string OpcodeStr, ValueType Ty, SDNode ShOp> 1062 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst), 1063 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD, 1064 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 1065 [(set QPR:$dst, (Ty (add QPR:$src1, 1066 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>; 1067 1068// Shift by immediate and insert, 1069// both double- and quad-register. 1070class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 1071 string OpcodeStr, ValueType Ty, SDNode ShOp> 1072 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst), 1073 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD, 1074 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 1075 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>; 1076class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 1077 string OpcodeStr, ValueType Ty, SDNode ShOp> 1078 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst), 1079 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ, 1080 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 1081 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>; 1082 1083// Convert, with fractional bits immediate, 1084// both double- and quad-register. 1085class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 1086 string OpcodeStr, ValueType ResTy, ValueType OpTy, 1087 Intrinsic IntOp> 1088 : N2VImm<op24, op23, op11_8, op7, 0, op4, 1089 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD, 1090 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 1091 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>; 1092class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 1093 string OpcodeStr, ValueType ResTy, ValueType OpTy, 1094 Intrinsic IntOp> 1095 : N2VImm<op24, op23, op11_8, op7, 1, op4, 1096 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ, 1097 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 1098 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>; 1099 1100//===----------------------------------------------------------------------===// 1101// Multiclasses 1102//===----------------------------------------------------------------------===// 1103 1104// Abbreviations used in multiclass suffixes: 1105// Q = quarter int (8 bit) elements 1106// H = half int (16 bit) elements 1107// S = single int (32 bit) elements 1108// D = double int (64 bit) elements 1109 1110// Neon 3-register vector operations. 1111 1112// First with only element sizes of 8, 16 and 32 bits: 1113multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 1114 InstrItinClass itinD16, InstrItinClass itinD32, 1115 InstrItinClass itinQ16, InstrItinClass itinQ32, 1116 string OpcodeStr, SDNode OpNode, bit Commutable = 0> { 1117 // 64-bit vector types. 1118 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16, 1119 !strconcat(OpcodeStr, "8"), v8i8, v8i8, OpNode, Commutable>; 1120 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16, 1121 !strconcat(OpcodeStr, "16"), v4i16, v4i16, OpNode, Commutable>; 1122 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32, 1123 !strconcat(OpcodeStr, "32"), v2i32, v2i32, OpNode, Commutable>; 1124 1125 // 128-bit vector types. 1126 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16, 1127 !strconcat(OpcodeStr, "8"), v16i8, v16i8, OpNode, Commutable>; 1128 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16, 1129 !strconcat(OpcodeStr, "16"), v8i16, v8i16, OpNode, Commutable>; 1130 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32, 1131 !strconcat(OpcodeStr, "32"), v4i32, v4i32, OpNode, Commutable>; 1132} 1133 1134multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> { 1135 def v4i16 : N3VDSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v4i16, ShOp>; 1136 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"), v2i32, ShOp>; 1137 def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v8i16, v4i16, ShOp>; 1138 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"), v4i32, v2i32, ShOp>; 1139} 1140 1141// ....then also with element size 64 bits: 1142multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 1143 InstrItinClass itinD, InstrItinClass itinQ, 1144 string OpcodeStr, SDNode OpNode, bit Commutable = 0> 1145 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ, 1146 OpcodeStr, OpNode, Commutable> { 1147 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD, 1148 !strconcat(OpcodeStr, "64"), v1i64, v1i64, OpNode, Commutable>; 1149 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ, 1150 !strconcat(OpcodeStr, "64"), v2i64, v2i64, OpNode, Commutable>; 1151} 1152 1153 1154// Neon Narrowing 2-register vector intrinsics, 1155// source operand element sizes of 16, 32 and 64 bits: 1156multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 1157 bits<5> op11_7, bit op6, bit op4, 1158 InstrItinClass itin, string OpcodeStr, 1159 Intrinsic IntOp> { 1160 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4, 1161 itin, !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>; 1162 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4, 1163 itin, !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>; 1164 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4, 1165 itin, !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>; 1166} 1167 1168 1169// Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL). 1170// source operand element sizes of 16, 32 and 64 bits: 1171multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4, 1172 string OpcodeStr, Intrinsic IntOp> { 1173 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD, 1174 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>; 1175 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD, 1176 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>; 1177 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD, 1178 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>; 1179} 1180 1181 1182// Neon 3-register vector intrinsics. 1183 1184// First with only element sizes of 16 and 32 bits: 1185multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, 1186 InstrItinClass itinD16, InstrItinClass itinD32, 1187 InstrItinClass itinQ16, InstrItinClass itinQ32, 1188 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { 1189 // 64-bit vector types. 1190 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16, !strconcat(OpcodeStr,"16"), 1191 v4i16, v4i16, IntOp, Commutable>; 1192 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32, !strconcat(OpcodeStr,"32"), 1193 v2i32, v2i32, IntOp, Commutable>; 1194 1195 // 128-bit vector types. 1196 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16, !strconcat(OpcodeStr,"16"), 1197 v8i16, v8i16, IntOp, Commutable>; 1198 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32, !strconcat(OpcodeStr,"32"), 1199 v4i32, v4i32, IntOp, Commutable>; 1200} 1201 1202multiclass N3VIntSL_HS<bits<4> op11_8, 1203 InstrItinClass itinD16, InstrItinClass itinD32, 1204 InstrItinClass itinQ16, InstrItinClass itinQ32, 1205 string OpcodeStr, Intrinsic IntOp> { 1206 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, !strconcat(OpcodeStr, "16"), v4i16, IntOp>; 1207 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, !strconcat(OpcodeStr, "32"), v2i32, IntOp>; 1208 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>; 1209 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>; 1210} 1211 1212// ....then also with element size of 8 bits: 1213multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 1214 InstrItinClass itinD16, InstrItinClass itinD32, 1215 InstrItinClass itinQ16, InstrItinClass itinQ32, 1216 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> 1217 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32, 1218 OpcodeStr, IntOp, Commutable> { 1219 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16, 1220 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp, Commutable>; 1221 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16, 1222 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp, Commutable>; 1223} 1224 1225// ....then also with element size of 64 bits: 1226multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 1227 InstrItinClass itinD16, InstrItinClass itinD32, 1228 InstrItinClass itinQ16, InstrItinClass itinQ32, 1229 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> 1230 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32, 1231 OpcodeStr, IntOp, Commutable> { 1232 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32, 1233 !strconcat(OpcodeStr,"64"), v1i64, v1i64, IntOp, Commutable>; 1234 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32, 1235 !strconcat(OpcodeStr,"64"), v2i64, v2i64, IntOp, Commutable>; 1236} 1237 1238 1239// Neon Narrowing 3-register vector intrinsics, 1240// source operand element sizes of 16, 32 and 64 bits: 1241multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4, 1242 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { 1243 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"), 1244 v8i8, v8i16, IntOp, Commutable>; 1245 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"), 1246 v4i16, v4i32, IntOp, Commutable>; 1247 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"), 1248 v2i32, v2i64, IntOp, Commutable>; 1249} 1250 1251 1252// Neon Long 3-register vector intrinsics. 1253 1254// First with only element sizes of 16 and 32 bits: 1255multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, 1256 InstrItinClass itin, string OpcodeStr, 1257 Intrinsic IntOp, bit Commutable = 0> { 1258 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin, 1259 !strconcat(OpcodeStr,"16"), v4i32, v4i16, IntOp, Commutable>; 1260 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin, 1261 !strconcat(OpcodeStr,"32"), v2i64, v2i32, IntOp, Commutable>; 1262} 1263 1264multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8, 1265 InstrItinClass itin, string OpcodeStr, Intrinsic IntOp> { 1266 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin, 1267 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>; 1268 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin, 1269 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>; 1270} 1271 1272// ....then also with element size of 8 bits: 1273multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 1274 InstrItinClass itin, string OpcodeStr, 1275 Intrinsic IntOp, bit Commutable = 0> 1276 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, IntOp, Commutable> { 1277 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin, 1278 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp, Commutable>; 1279} 1280 1281 1282// Neon Wide 3-register vector intrinsics, 1283// source operand element sizes of 8, 16 and 32 bits: 1284multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 1285 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { 1286 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 1287 v8i16, v8i8, IntOp, Commutable>; 1288 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"), 1289 v4i32, v4i16, IntOp, Commutable>; 1290 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"), 1291 v2i64, v2i32, IntOp, Commutable>; 1292} 1293 1294 1295// Neon Multiply-Op vector operations, 1296// element sizes of 8, 16 and 32 bits: 1297multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 1298 InstrItinClass itinD16, InstrItinClass itinD32, 1299 InstrItinClass itinQ16, InstrItinClass itinQ32, 1300 string OpcodeStr, SDNode OpNode> { 1301 // 64-bit vector types. 1302 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16, 1303 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>; 1304 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16, 1305 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>; 1306 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32, 1307 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>; 1308 1309 // 128-bit vector types. 1310 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16, 1311 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>; 1312 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16, 1313 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>; 1314 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32, 1315 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>; 1316} 1317 1318multiclass N3VMulOpSL_HS<bits<4> op11_8, 1319 InstrItinClass itinD16, InstrItinClass itinD32, 1320 InstrItinClass itinQ16, InstrItinClass itinQ32, 1321 string OpcodeStr, SDNode ShOp> { 1322 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16, 1323 !strconcat(OpcodeStr, "16"), v4i16, mul, ShOp>; 1324 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32, 1325 !strconcat(OpcodeStr, "32"), v2i32, mul, ShOp>; 1326 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16, 1327 !strconcat(OpcodeStr, "16"), v8i16, v4i16, mul, ShOp>; 1328 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32, 1329 !strconcat(OpcodeStr, "32"), v4i32, v2i32, mul, ShOp>; 1330} 1331 1332// Neon 3-argument intrinsics, 1333// element sizes of 8, 16 and 32 bits: 1334multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 1335 string OpcodeStr, Intrinsic IntOp> { 1336 // 64-bit vector types. 1337 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D, 1338 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>; 1339 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D, 1340 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>; 1341 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D, 1342 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>; 1343 1344 // 128-bit vector types. 1345 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q, 1346 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>; 1347 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q, 1348 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>; 1349 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q, 1350 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>; 1351} 1352 1353 1354// Neon Long 3-argument intrinsics. 1355 1356// First with only element sizes of 16 and 32 bits: 1357multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4, 1358 string OpcodeStr, Intrinsic IntOp> { 1359 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D, 1360 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>; 1361 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D, 1362 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>; 1363} 1364 1365multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8, 1366 string OpcodeStr, Intrinsic IntOp> { 1367 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D, 1368 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>; 1369 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D, 1370 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>; 1371} 1372 1373// ....then also with element size of 8 bits: 1374multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 1375 string OpcodeStr, Intrinsic IntOp> 1376 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> { 1377 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D, 1378 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>; 1379} 1380 1381 1382// Neon 2-register vector intrinsics, 1383// element sizes of 8, 16 and 32 bits: 1384multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 1385 bits<5> op11_7, bit op4, 1386 InstrItinClass itinD, InstrItinClass itinQ, 1387 string OpcodeStr, Intrinsic IntOp> { 1388 // 64-bit vector types. 1389 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 1390 itinD, !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>; 1391 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 1392 itinD, !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>; 1393 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 1394 itinD, !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>; 1395 1396 // 128-bit vector types. 1397 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 1398 itinQ, !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>; 1399 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 1400 itinQ, !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>; 1401 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 1402 itinQ, !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>; 1403} 1404 1405 1406// Neon Pairwise long 2-register intrinsics, 1407// element sizes of 8, 16 and 32 bits: 1408multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 1409 bits<5> op11_7, bit op4, 1410 string OpcodeStr, Intrinsic IntOp> { 1411 // 64-bit vector types. 1412 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 1413 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>; 1414 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 1415 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>; 1416 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 1417 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>; 1418 1419 // 128-bit vector types. 1420 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 1421 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>; 1422 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 1423 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>; 1424 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 1425 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>; 1426} 1427 1428 1429// Neon Pairwise long 2-register accumulate intrinsics, 1430// element sizes of 8, 16 and 32 bits: 1431multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 1432 bits<5> op11_7, bit op4, 1433 string OpcodeStr, Intrinsic IntOp> { 1434 // 64-bit vector types. 1435 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 1436 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>; 1437 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 1438 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>; 1439 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 1440 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>; 1441 1442 // 128-bit vector types. 1443 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 1444 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>; 1445 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 1446 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>; 1447 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 1448 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>; 1449} 1450 1451 1452// Neon 2-register vector shift by immediate, 1453// element sizes of 8, 16, 32 and 64 bits: 1454multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 1455 InstrItinClass itin, string OpcodeStr, SDNode OpNode> { 1456 // 64-bit vector types. 1457 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin, 1458 !strconcat(OpcodeStr, "8"), v8i8, OpNode> { 1459 let Inst{21-19} = 0b001; // imm6 = 001xxx 1460 } 1461 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin, 1462 !strconcat(OpcodeStr, "16"), v4i16, OpNode> { 1463 let Inst{21-20} = 0b01; // imm6 = 01xxxx 1464 } 1465 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin, 1466 !strconcat(OpcodeStr, "32"), v2i32, OpNode> { 1467 let Inst{21} = 0b1; // imm6 = 1xxxxx 1468 } 1469 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin, 1470 !strconcat(OpcodeStr, "64"), v1i64, OpNode>; 1471 // imm6 = xxxxxx 1472 1473 // 128-bit vector types. 1474 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin, 1475 !strconcat(OpcodeStr, "8"), v16i8, OpNode> { 1476 let Inst{21-19} = 0b001; // imm6 = 001xxx 1477 } 1478 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin, 1479 !strconcat(OpcodeStr, "16"), v8i16, OpNode> { 1480 let Inst{21-20} = 0b01; // imm6 = 01xxxx 1481 } 1482 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin, 1483 !strconcat(OpcodeStr, "32"), v4i32, OpNode> { 1484 let Inst{21} = 0b1; // imm6 = 1xxxxx 1485 } 1486 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin, 1487 !strconcat(OpcodeStr, "64"), v2i64, OpNode>; 1488 // imm6 = xxxxxx 1489} 1490 1491 1492// Neon Shift-Accumulate vector operations, 1493// element sizes of 8, 16, 32 and 64 bits: 1494multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 1495 string OpcodeStr, SDNode ShOp> { 1496 // 64-bit vector types. 1497 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, 1498 !strconcat(OpcodeStr, "8"), v8i8, ShOp> { 1499 let Inst{21-19} = 0b001; // imm6 = 001xxx 1500 } 1501 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, 1502 !strconcat(OpcodeStr, "16"), v4i16, ShOp> { 1503 let Inst{21-20} = 0b01; // imm6 = 01xxxx 1504 } 1505 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, 1506 !strconcat(OpcodeStr, "32"), v2i32, ShOp> { 1507 let Inst{21} = 0b1; // imm6 = 1xxxxx 1508 } 1509 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, 1510 !strconcat(OpcodeStr, "64"), v1i64, ShOp>; 1511 // imm6 = xxxxxx 1512 1513 // 128-bit vector types. 1514 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, 1515 !strconcat(OpcodeStr, "8"), v16i8, ShOp> { 1516 let Inst{21-19} = 0b001; // imm6 = 001xxx 1517 } 1518 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, 1519 !strconcat(OpcodeStr, "16"), v8i16, ShOp> { 1520 let Inst{21-20} = 0b01; // imm6 = 01xxxx 1521 } 1522 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, 1523 !strconcat(OpcodeStr, "32"), v4i32, ShOp> { 1524 let Inst{21} = 0b1; // imm6 = 1xxxxx 1525 } 1526 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, 1527 !strconcat(OpcodeStr, "64"), v2i64, ShOp>; 1528 // imm6 = xxxxxx 1529} 1530 1531 1532// Neon Shift-Insert vector operations, 1533// element sizes of 8, 16, 32 and 64 bits: 1534multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 1535 string OpcodeStr, SDNode ShOp> { 1536 // 64-bit vector types. 1537 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, 1538 !strconcat(OpcodeStr, "8"), v8i8, ShOp> { 1539 let Inst{21-19} = 0b001; // imm6 = 001xxx 1540 } 1541 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, 1542 !strconcat(OpcodeStr, "16"), v4i16, ShOp> { 1543 let Inst{21-20} = 0b01; // imm6 = 01xxxx 1544 } 1545 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, 1546 !strconcat(OpcodeStr, "32"), v2i32, ShOp> { 1547 let Inst{21} = 0b1; // imm6 = 1xxxxx 1548 } 1549 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, 1550 !strconcat(OpcodeStr, "64"), v1i64, ShOp>; 1551 // imm6 = xxxxxx 1552 1553 // 128-bit vector types. 1554 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, 1555 !strconcat(OpcodeStr, "8"), v16i8, ShOp> { 1556 let Inst{21-19} = 0b001; // imm6 = 001xxx 1557 } 1558 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, 1559 !strconcat(OpcodeStr, "16"), v8i16, ShOp> { 1560 let Inst{21-20} = 0b01; // imm6 = 01xxxx 1561 } 1562 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, 1563 !strconcat(OpcodeStr, "32"), v4i32, ShOp> { 1564 let Inst{21} = 0b1; // imm6 = 1xxxxx 1565 } 1566 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, 1567 !strconcat(OpcodeStr, "64"), v2i64, ShOp>; 1568 // imm6 = xxxxxx 1569} 1570 1571// Neon Shift Long operations, 1572// element sizes of 8, 16, 32 bits: 1573multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, 1574 bit op4, string OpcodeStr, SDNode OpNode> { 1575 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4, 1576 !strconcat(OpcodeStr, "8"), v8i16, v8i8, OpNode> { 1577 let Inst{21-19} = 0b001; // imm6 = 001xxx 1578 } 1579 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4, 1580 !strconcat(OpcodeStr, "16"), v4i32, v4i16, OpNode> { 1581 let Inst{21-20} = 0b01; // imm6 = 01xxxx 1582 } 1583 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4, 1584 !strconcat(OpcodeStr, "32"), v2i64, v2i32, OpNode> { 1585 let Inst{21} = 0b1; // imm6 = 1xxxxx 1586 } 1587} 1588 1589// Neon Shift Narrow operations, 1590// element sizes of 16, 32, 64 bits: 1591multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, 1592 bit op4, InstrItinClass itin, string OpcodeStr, 1593 SDNode OpNode> { 1594 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, 1595 !strconcat(OpcodeStr, "16"), v8i8, v8i16, OpNode> { 1596 let Inst{21-19} = 0b001; // imm6 = 001xxx 1597 } 1598 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, 1599 !strconcat(OpcodeStr, "32"), v4i16, v4i32, OpNode> { 1600 let Inst{21-20} = 0b01; // imm6 = 01xxxx 1601 } 1602 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, 1603 !strconcat(OpcodeStr, "64"), v2i32, v2i64, OpNode> { 1604 let Inst{21} = 0b1; // imm6 = 1xxxxx 1605 } 1606} 1607 1608//===----------------------------------------------------------------------===// 1609// Instruction Definitions. 1610//===----------------------------------------------------------------------===// 1611 1612// Vector Add Operations. 1613 1614// VADD : Vector Add (integer and floating-point) 1615defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i", add, 1>; 1616def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32", v2f32, v2f32, fadd, 1>; 1617def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32", v4f32, v4f32, fadd, 1>; 1618// VADDL : Vector Add Long (Q = D + D) 1619defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s", int_arm_neon_vaddls, 1>; 1620defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u", int_arm_neon_vaddlu, 1>; 1621// VADDW : Vector Add Wide (Q = Q + D) 1622defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>; 1623defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>; 1624// VHADD : Vector Halving Add 1625defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1626 IIC_VBINi4Q, "vhadd.s", int_arm_neon_vhadds, 1>; 1627defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1628 IIC_VBINi4Q, "vhadd.u", int_arm_neon_vhaddu, 1>; 1629// VRHADD : Vector Rounding Halving Add 1630defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1631 IIC_VBINi4Q, "vrhadd.s", int_arm_neon_vrhadds, 1>; 1632defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1633 IIC_VBINi4Q, "vrhadd.u", int_arm_neon_vrhaddu, 1>; 1634// VQADD : Vector Saturating Add 1635defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1636 IIC_VBINi4Q, "vqadd.s", int_arm_neon_vqadds, 1>; 1637defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1638 IIC_VBINi4Q, "vqadd.u", int_arm_neon_vqaddu, 1>; 1639// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q) 1640defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>; 1641// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q) 1642defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>; 1643 1644// Vector Multiply Operations. 1645 1646// VMUL : Vector Multiply (integer, polynomial and floating-point) 1647defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q, 1648 IIC_VMULi32Q, "vmul.i", mul, 1>; 1649def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8", v8i8, v8i8, 1650 int_arm_neon_vmulp, 1>; 1651def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8", v16i8, v16i8, 1652 int_arm_neon_vmulp, 1>; 1653def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32", v2f32, v2f32, fmul, 1>; 1654def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32", v4f32, v4f32, fmul, 1>; 1655defm VMULsl : N3VSL_HS<0b1000, "vmul.i", mul>; 1656def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul.f32", v2f32, fmul>; 1657def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul.f32", v4f32, v2f32, fmul>; 1658def : Pat<(v8i16 (mul (v8i16 QPR:$src1), 1659 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), 1660 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1), 1661 (v4i16 (EXTRACT_SUBREG QPR:$src2, 1662 (DSubReg_i16_reg imm:$lane))), 1663 (SubReg_i16_lane imm:$lane)))>; 1664def : Pat<(v4i32 (mul (v4i32 QPR:$src1), 1665 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), 1666 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1), 1667 (v2i32 (EXTRACT_SUBREG QPR:$src2, 1668 (DSubReg_i32_reg imm:$lane))), 1669 (SubReg_i32_lane imm:$lane)))>; 1670def : Pat<(v4f32 (fmul (v4f32 QPR:$src1), 1671 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))), 1672 (v4f32 (VMULslfq (v4f32 QPR:$src1), 1673 (v2f32 (EXTRACT_SUBREG QPR:$src2, 1674 (DSubReg_i32_reg imm:$lane))), 1675 (SubReg_i32_lane imm:$lane)))>; 1676 1677// VQDMULH : Vector Saturating Doubling Multiply Returning High Half 1678defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D, 1679 IIC_VMULi16Q, IIC_VMULi32Q, 1680 "vqdmulh.s", int_arm_neon_vqdmulh, 1>; 1681defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D, 1682 IIC_VMULi16Q, IIC_VMULi32Q, 1683 "vqdmulh.s", int_arm_neon_vqdmulh>; 1684def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1), 1685 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), 1686 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1), 1687 (v4i16 (EXTRACT_SUBREG QPR:$src2, 1688 (DSubReg_i16_reg imm:$lane))), 1689 (SubReg_i16_lane imm:$lane)))>; 1690def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1), 1691 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), 1692 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1), 1693 (v2i32 (EXTRACT_SUBREG QPR:$src2, 1694 (DSubReg_i32_reg imm:$lane))), 1695 (SubReg_i32_lane imm:$lane)))>; 1696 1697// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half 1698defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D, 1699 IIC_VMULi16Q, IIC_VMULi32Q, 1700 "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>; 1701defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D, 1702 IIC_VMULi16Q, IIC_VMULi32Q, 1703 "vqrdmulh.s", int_arm_neon_vqrdmulh>; 1704def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1), 1705 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), 1706 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1), 1707 (v4i16 (EXTRACT_SUBREG QPR:$src2, 1708 (DSubReg_i16_reg imm:$lane))), 1709 (SubReg_i16_lane imm:$lane)))>; 1710def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1), 1711 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), 1712 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1), 1713 (v2i32 (EXTRACT_SUBREG QPR:$src2, 1714 (DSubReg_i32_reg imm:$lane))), 1715 (SubReg_i32_lane imm:$lane)))>; 1716 1717// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D) 1718defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls, 1>; 1719defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu, 1>; 1720def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8", v8i16, v8i8, 1721 int_arm_neon_vmullp, 1>; 1722defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls>; 1723defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu>; 1724 1725// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D) 1726defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull, 1>; 1727defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull>; 1728 1729// Vector Multiply-Accumulate and Multiply-Subtract Operations. 1730 1731// VMLA : Vector Multiply Accumulate (integer and floating-point) 1732defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, 1733 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>; 1734def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>; 1735def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32", v4f32, fmul, fadd>; 1736defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D, 1737 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>; 1738def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>; 1739def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32", v4f32, v2f32, fmul, fadd>; 1740 1741def : Pat<(v8i16 (add (v8i16 QPR:$src1), 1742 (mul (v8i16 QPR:$src2), 1743 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))), 1744 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), 1745 (v8i16 QPR:$src2), 1746 (v4i16 (EXTRACT_SUBREG QPR:$src3, 1747 (DSubReg_i16_reg imm:$lane))), 1748 (SubReg_i16_lane imm:$lane)))>; 1749 1750def : Pat<(v4i32 (add (v4i32 QPR:$src1), 1751 (mul (v4i32 QPR:$src2), 1752 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), 1753 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), 1754 (v4i32 QPR:$src2), 1755 (v2i32 (EXTRACT_SUBREG QPR:$src3, 1756 (DSubReg_i32_reg imm:$lane))), 1757 (SubReg_i32_lane imm:$lane)))>; 1758 1759def : Pat<(v4f32 (fadd (v4f32 QPR:$src1), 1760 (fmul (v4f32 QPR:$src2), 1761 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), 1762 (v4f32 (VMLAslfq (v4f32 QPR:$src1), 1763 (v4f32 QPR:$src2), 1764 (v2f32 (EXTRACT_SUBREG QPR:$src3, 1765 (DSubReg_i32_reg imm:$lane))), 1766 (SubReg_i32_lane imm:$lane)))>; 1767 1768// VMLAL : Vector Multiply Accumulate Long (Q += D * D) 1769defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>; 1770defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>; 1771 1772defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal.s", int_arm_neon_vmlals>; 1773defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal.u", int_arm_neon_vmlalu>; 1774 1775// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D) 1776defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>; 1777defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal.s", int_arm_neon_vqdmlal>; 1778 1779// VMLS : Vector Multiply Subtract (integer and floating-point) 1780defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, 1781 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>; 1782def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>; 1783def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32", v4f32, fmul, fsub>; 1784defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D, 1785 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>; 1786def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>; 1787def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32", v4f32, v2f32, fmul, fsub>; 1788 1789def : Pat<(v8i16 (sub (v8i16 QPR:$src1), 1790 (mul (v8i16 QPR:$src2), 1791 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))), 1792 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), 1793 (v8i16 QPR:$src2), 1794 (v4i16 (EXTRACT_SUBREG QPR:$src3, 1795 (DSubReg_i16_reg imm:$lane))), 1796 (SubReg_i16_lane imm:$lane)))>; 1797 1798def : Pat<(v4i32 (sub (v4i32 QPR:$src1), 1799 (mul (v4i32 QPR:$src2), 1800 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), 1801 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), 1802 (v4i32 QPR:$src2), 1803 (v2i32 (EXTRACT_SUBREG QPR:$src3, 1804 (DSubReg_i32_reg imm:$lane))), 1805 (SubReg_i32_lane imm:$lane)))>; 1806 1807def : Pat<(v4f32 (fsub (v4f32 QPR:$src1), 1808 (fmul (v4f32 QPR:$src2), 1809 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), 1810 (v4f32 (VMLSslfq (v4f32 QPR:$src1), 1811 (v4f32 QPR:$src2), 1812 (v2f32 (EXTRACT_SUBREG QPR:$src3, 1813 (DSubReg_i32_reg imm:$lane))), 1814 (SubReg_i32_lane imm:$lane)))>; 1815 1816// VMLSL : Vector Multiply Subtract Long (Q -= D * D) 1817defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>; 1818defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>; 1819 1820defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl.s", int_arm_neon_vmlsls>; 1821defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl.u", int_arm_neon_vmlslu>; 1822 1823// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D) 1824defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>; 1825defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl.s", int_arm_neon_vqdmlsl>; 1826 1827// Vector Subtract Operations. 1828 1829// VSUB : Vector Subtract (integer and floating-point) 1830defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, "vsub.i", sub, 0>; 1831def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32", v2f32, v2f32, fsub, 0>; 1832def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32", v4f32, v4f32, fsub, 0>; 1833// VSUBL : Vector Subtract Long (Q = D - D) 1834defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s", int_arm_neon_vsubls, 1>; 1835defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u", int_arm_neon_vsublu, 1>; 1836// VSUBW : Vector Subtract Wide (Q = Q - D) 1837defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>; 1838defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>; 1839// VHSUB : Vector Halving Subtract 1840defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1841 IIC_VBINi4Q, "vhsub.s", int_arm_neon_vhsubs, 0>; 1842defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1843 IIC_VBINi4Q, "vhsub.u", int_arm_neon_vhsubu, 0>; 1844// VQSUB : Vector Saturing Subtract 1845defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1846 IIC_VBINi4Q, "vqsub.s", int_arm_neon_vqsubs, 0>; 1847defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1848 IIC_VBINi4Q, "vqsub.u", int_arm_neon_vqsubu, 0>; 1849// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q) 1850defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>; 1851// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q) 1852defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>; 1853 1854// Vector Comparisons. 1855 1856// VCEQ : Vector Compare Equal 1857defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1858 IIC_VBINi4Q, "vceq.i", NEONvceq, 1>; 1859def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32, NEONvceq, 1>; 1860def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32, NEONvceq, 1>; 1861// VCGE : Vector Compare Greater Than or Equal 1862defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1863 IIC_VBINi4Q, "vcge.s", NEONvcge, 0>; 1864defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1865 IIC_VBINi4Q, "vcge.u", NEONvcgeu, 0>; 1866def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32", v2i32, v2f32, NEONvcge, 0>; 1867def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32, NEONvcge, 0>; 1868// VCGT : Vector Compare Greater Than 1869defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1870 IIC_VBINi4Q, "vcgt.s", NEONvcgt, 0>; 1871defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1872 IIC_VBINi4Q, "vcgt.u", NEONvcgtu, 0>; 1873def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>; 1874def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>; 1875// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE) 1876def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32", v2i32, v2f32, 1877 int_arm_neon_vacged, 0>; 1878def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32", v4i32, v4f32, 1879 int_arm_neon_vacgeq, 0>; 1880// VACGT : Vector Absolute Compare Greater Than (aka VCAGT) 1881def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32", v2i32, v2f32, 1882 int_arm_neon_vacgtd, 0>; 1883def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32", v4i32, v4f32, 1884 int_arm_neon_vacgtq, 0>; 1885// VTST : Vector Test Bits 1886defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1887 IIC_VBINi4Q, "vtst.i", NEONvtst, 1>; 1888 1889// Vector Bitwise Operations. 1890 1891// VAND : Vector Bitwise AND 1892def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", v2i32, v2i32, and, 1>; 1893def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", v4i32, v4i32, and, 1>; 1894 1895// VEOR : Vector Bitwise Exclusive OR 1896def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", v2i32, v2i32, xor, 1>; 1897def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", v4i32, v4i32, xor, 1>; 1898 1899// VORR : Vector Bitwise OR 1900def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", v2i32, v2i32, or, 1>; 1901def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", v4i32, v4i32, or, 1>; 1902 1903// VBIC : Vector Bitwise Bit Clear (AND NOT) 1904def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), 1905 (ins DPR:$src1, DPR:$src2), IIC_VBINiD, 1906 "vbic\t$dst, $src1, $src2", "", 1907 [(set DPR:$dst, (v2i32 (and DPR:$src1, 1908 (vnot_conv DPR:$src2))))]>; 1909def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), 1910 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ, 1911 "vbic\t$dst, $src1, $src2", "", 1912 [(set QPR:$dst, (v4i32 (and QPR:$src1, 1913 (vnot_conv QPR:$src2))))]>; 1914 1915// VORN : Vector Bitwise OR NOT 1916def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst), 1917 (ins DPR:$src1, DPR:$src2), IIC_VBINiD, 1918 "vorn\t$dst, $src1, $src2", "", 1919 [(set DPR:$dst, (v2i32 (or DPR:$src1, 1920 (vnot_conv DPR:$src2))))]>; 1921def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst), 1922 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ, 1923 "vorn\t$dst, $src1, $src2", "", 1924 [(set QPR:$dst, (v4i32 (or QPR:$src1, 1925 (vnot_conv QPR:$src2))))]>; 1926 1927// VMVN : Vector Bitwise NOT 1928def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0, 1929 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD, 1930 "vmvn\t$dst, $src", "", 1931 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>; 1932def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0, 1933 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD, 1934 "vmvn\t$dst, $src", "", 1935 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>; 1936def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>; 1937def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>; 1938 1939// VBSL : Vector Bitwise Select 1940def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), 1941 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD, 1942 "vbsl\t$dst, $src2, $src3", "$src1 = $dst", 1943 [(set DPR:$dst, 1944 (v2i32 (or (and DPR:$src2, DPR:$src1), 1945 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>; 1946def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), 1947 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ, 1948 "vbsl\t$dst, $src2, $src3", "$src1 = $dst", 1949 [(set QPR:$dst, 1950 (v4i32 (or (and QPR:$src2, QPR:$src1), 1951 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>; 1952 1953// VBIF : Vector Bitwise Insert if False 1954// like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst", 1955// VBIT : Vector Bitwise Insert if True 1956// like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst", 1957// These are not yet implemented. The TwoAddress pass will not go looking 1958// for equivalent operations with different register constraints; it just 1959// inserts copies. 1960 1961// Vector Absolute Differences. 1962 1963// VABD : Vector Absolute Difference 1964defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1965 IIC_VBINi4Q, "vabd.s", int_arm_neon_vabds, 0>; 1966defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1967 IIC_VBINi4Q, "vabd.u", int_arm_neon_vabdu, 0>; 1968def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND, "vabd.f32", v2f32, v2f32, 1969 int_arm_neon_vabds, 0>; 1970def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vabd.f32", v4f32, v4f32, 1971 int_arm_neon_vabds, 0>; 1972 1973// VABDL : Vector Absolute Difference Long (Q = | D - D |) 1974defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q, "vabdl.s", int_arm_neon_vabdls, 0>; 1975defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q, "vabdl.u", int_arm_neon_vabdlu, 0>; 1976 1977// VABA : Vector Absolute Difference and Accumulate 1978defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba.s", int_arm_neon_vabas>; 1979defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba.u", int_arm_neon_vabau>; 1980 1981// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |) 1982defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>; 1983defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>; 1984 1985// Vector Maximum and Minimum. 1986 1987// VMAX : Vector Maximum 1988defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1989 IIC_VBINi4Q, "vmax.s", int_arm_neon_vmaxs, 1>; 1990defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1991 IIC_VBINi4Q, "vmax.u", int_arm_neon_vmaxu, 1>; 1992def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax.f32", v2f32, v2f32, 1993 int_arm_neon_vmaxs, 1>; 1994def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax.f32", v4f32, v4f32, 1995 int_arm_neon_vmaxs, 1>; 1996 1997// VMIN : Vector Minimum 1998defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 1999 IIC_VBINi4Q, "vmin.s", int_arm_neon_vmins, 1>; 2000defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 2001 IIC_VBINi4Q, "vmin.u", int_arm_neon_vminu, 1>; 2002def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin.f32", v2f32, v2f32, 2003 int_arm_neon_vmins, 1>; 2004def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin.f32", v4f32, v4f32, 2005 int_arm_neon_vmins, 1>; 2006 2007// Vector Pairwise Operations. 2008 2009// VPADD : Vector Pairwise Add 2010def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd.i8", v8i8, v8i8, 2011 int_arm_neon_vpadd, 0>; 2012def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd.i16", v4i16, v4i16, 2013 int_arm_neon_vpadd, 0>; 2014def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd.i32", v2i32, v2i32, 2015 int_arm_neon_vpadd, 0>; 2016def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd.f32", v2f32, v2f32, 2017 int_arm_neon_vpadd, 0>; 2018 2019// VPADDL : Vector Pairwise Add Long 2020defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s", 2021 int_arm_neon_vpaddls>; 2022defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u", 2023 int_arm_neon_vpaddlu>; 2024 2025// VPADAL : Vector Pairwise Add and Accumulate Long 2026defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal.s", 2027 int_arm_neon_vpadals>; 2028defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal.u", 2029 int_arm_neon_vpadalu>; 2030 2031// VPMAX : Vector Pairwise Maximum 2032def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.s8", v8i8, v8i8, 2033 int_arm_neon_vpmaxs, 0>; 2034def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.s16", v4i16, v4i16, 2035 int_arm_neon_vpmaxs, 0>; 2036def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.s32", v2i32, v2i32, 2037 int_arm_neon_vpmaxs, 0>; 2038def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.u8", v8i8, v8i8, 2039 int_arm_neon_vpmaxu, 0>; 2040def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.u16", v4i16, v4i16, 2041 int_arm_neon_vpmaxu, 0>; 2042def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.u32", v2i32, v2i32, 2043 int_arm_neon_vpmaxu, 0>; 2044def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax.f32", v2f32, v2f32, 2045 int_arm_neon_vpmaxs, 0>; 2046 2047// VPMIN : Vector Pairwise Minimum 2048def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.s8", v8i8, v8i8, 2049 int_arm_neon_vpmins, 0>; 2050def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.s16", v4i16, v4i16, 2051 int_arm_neon_vpmins, 0>; 2052def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.s32", v2i32, v2i32, 2053 int_arm_neon_vpmins, 0>; 2054def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.u8", v8i8, v8i8, 2055 int_arm_neon_vpminu, 0>; 2056def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.u16", v4i16, v4i16, 2057 int_arm_neon_vpminu, 0>; 2058def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.u32", v2i32, v2i32, 2059 int_arm_neon_vpminu, 0>; 2060def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin.f32", v2f32, v2f32, 2061 int_arm_neon_vpmins, 0>; 2062 2063// Vector Reciprocal and Reciprocal Square Root Estimate and Step. 2064 2065// VRECPE : Vector Reciprocal Estimate 2066def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, 2067 IIC_VUNAD, "vrecpe.u32", 2068 v2i32, v2i32, int_arm_neon_vrecpe>; 2069def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, 2070 IIC_VUNAQ, "vrecpe.u32", 2071 v4i32, v4i32, int_arm_neon_vrecpe>; 2072def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, 2073 IIC_VUNAD, "vrecpe.f32", 2074 v2f32, v2f32, int_arm_neon_vrecpe>; 2075def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, 2076 IIC_VUNAQ, "vrecpe.f32", 2077 v4f32, v4f32, int_arm_neon_vrecpe>; 2078 2079// VRECPS : Vector Reciprocal Step 2080def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSD, "vrecps.f32", v2f32, v2f32, 2081 int_arm_neon_vrecps, 1>; 2082def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSQ, "vrecps.f32", v4f32, v4f32, 2083 int_arm_neon_vrecps, 1>; 2084 2085// VRSQRTE : Vector Reciprocal Square Root Estimate 2086def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, 2087 IIC_VUNAD, "vrsqrte.u32", 2088 v2i32, v2i32, int_arm_neon_vrsqrte>; 2089def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, 2090 IIC_VUNAQ, "vrsqrte.u32", 2091 v4i32, v4i32, int_arm_neon_vrsqrte>; 2092def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, 2093 IIC_VUNAD, "vrsqrte.f32", 2094 v2f32, v2f32, int_arm_neon_vrsqrte>; 2095def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, 2096 IIC_VUNAQ, "vrsqrte.f32", 2097 v4f32, v4f32, int_arm_neon_vrsqrte>; 2098 2099// VRSQRTS : Vector Reciprocal Square Root Step 2100def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSD, "vrsqrts.f32", v2f32, v2f32, 2101 int_arm_neon_vrsqrts, 1>; 2102def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSQ, "vrsqrts.f32", v4f32, v4f32, 2103 int_arm_neon_vrsqrts, 1>; 2104 2105// Vector Shifts. 2106 2107// VSHL : Vector Shift 2108defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, 2109 IIC_VSHLiQ, "vshl.s", int_arm_neon_vshifts, 0>; 2110defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, 2111 IIC_VSHLiQ, "vshl.u", int_arm_neon_vshiftu, 0>; 2112// VSHL : Vector Shift Left (Immediate) 2113defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl.i", NEONvshl>; 2114// VSHR : Vector Shift Right (Immediate) 2115defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr.s", NEONvshrs>; 2116defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr.u", NEONvshru>; 2117 2118// VSHLL : Vector Shift Left Long 2119defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll.s", NEONvshlls>; 2120defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll.u", NEONvshllu>; 2121 2122// VSHLL : Vector Shift Left Long (with maximum shift count) 2123class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 2124 bit op6, bit op4, string OpcodeStr, ValueType ResTy, 2125 ValueType OpTy, SDNode OpNode> 2126 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, ResTy, OpTy, OpNode> { 2127 let Inst{21-16} = op21_16; 2128} 2129def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8", 2130 v8i16, v8i8, NEONvshlli>; 2131def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16", 2132 v4i32, v4i16, NEONvshlli>; 2133def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32", 2134 v2i64, v2i32, NEONvshlli>; 2135 2136// VSHRN : Vector Shift Right and Narrow 2137defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn.i", NEONvshrn>; 2138 2139// VRSHL : Vector Rounding Shift 2140defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, 2141 IIC_VSHLi4Q, "vrshl.s", int_arm_neon_vrshifts, 0>; 2142defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, 2143 IIC_VSHLi4Q, "vrshl.u", int_arm_neon_vrshiftu, 0>; 2144// VRSHR : Vector Rounding Shift Right 2145defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.s", NEONvrshrs>; 2146defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.u", NEONvrshru>; 2147 2148// VRSHRN : Vector Rounding Shift Right and Narrow 2149defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn.i", 2150 NEONvrshrn>; 2151 2152// VQSHL : Vector Saturating Shift 2153defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, 2154 IIC_VSHLi4Q, "vqshl.s", int_arm_neon_vqshifts, 0>; 2155defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, 2156 IIC_VSHLi4Q, "vqshl.u", int_arm_neon_vqshiftu, 0>; 2157// VQSHL : Vector Saturating Shift Left (Immediate) 2158defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.s", NEONvqshls>; 2159defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.u", NEONvqshlu>; 2160// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned) 2161defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, IIC_VSHLi4D, "vqshlu.s", NEONvqshlsu>; 2162 2163// VQSHRN : Vector Saturating Shift Right and Narrow 2164defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn.s", 2165 NEONvqshrns>; 2166defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn.u", 2167 NEONvqshrnu>; 2168 2169// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned) 2170defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun.s", 2171 NEONvqshrnsu>; 2172 2173// VQRSHL : Vector Saturating Rounding Shift 2174defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, 2175 IIC_VSHLi4Q, "vqrshl.s", int_arm_neon_vqrshifts, 0>; 2176defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, 2177 IIC_VSHLi4Q, "vqrshl.u", int_arm_neon_vqrshiftu, 0>; 2178 2179// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow 2180defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn.s", 2181 NEONvqrshrns>; 2182defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn.u", 2183 NEONvqrshrnu>; 2184 2185// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned) 2186defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun.s", 2187 NEONvqrshrnsu>; 2188 2189// VSRA : Vector Shift Right and Accumulate 2190defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>; 2191defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>; 2192// VRSRA : Vector Rounding Shift Right and Accumulate 2193defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>; 2194defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>; 2195 2196// VSLI : Vector Shift Left and Insert 2197defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>; 2198// VSRI : Vector Shift Right and Insert 2199defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>; 2200 2201// Vector Absolute and Saturating Absolute. 2202 2203// VABS : Vector Absolute Value 2204defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, 2205 IIC_VUNAiD, IIC_VUNAiQ, "vabs.s", 2206 int_arm_neon_vabs>; 2207def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 2208 IIC_VUNAD, "vabs.f32", 2209 v2f32, v2f32, int_arm_neon_vabs>; 2210def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 2211 IIC_VUNAQ, "vabs.f32", 2212 v4f32, v4f32, int_arm_neon_vabs>; 2213 2214// VQABS : Vector Saturating Absolute Value 2215defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, 2216 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs.s", 2217 int_arm_neon_vqabs>; 2218 2219// Vector Negate. 2220 2221def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>; 2222def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>; 2223 2224class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty> 2225 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src), 2226 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "", 2227 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>; 2228class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty> 2229 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src), 2230 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "", 2231 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>; 2232 2233// VNEG : Vector Negate 2234def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>; 2235def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>; 2236def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>; 2237def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>; 2238def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>; 2239def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>; 2240 2241// VNEG : Vector Negate (floating-point) 2242def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, 2243 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD, 2244 "vneg.f32\t$dst, $src", "", 2245 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>; 2246def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0, 2247 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ, 2248 "vneg.f32\t$dst, $src", "", 2249 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>; 2250 2251def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>; 2252def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>; 2253def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>; 2254def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>; 2255def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>; 2256def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>; 2257 2258// VQNEG : Vector Saturating Negate 2259defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, 2260 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg.s", 2261 int_arm_neon_vqneg>; 2262 2263// Vector Bit Counting Operations. 2264 2265// VCLS : Vector Count Leading Sign Bits 2266defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, 2267 IIC_VCNTiD, IIC_VCNTiQ, "vcls.s", 2268 int_arm_neon_vcls>; 2269// VCLZ : Vector Count Leading Zeros 2270defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, 2271 IIC_VCNTiD, IIC_VCNTiQ, "vclz.i", 2272 int_arm_neon_vclz>; 2273// VCNT : Vector Count One Bits 2274def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, 2275 IIC_VCNTiD, "vcnt.8", 2276 v8i8, v8i8, int_arm_neon_vcnt>; 2277def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, 2278 IIC_VCNTiQ, "vcnt.8", 2279 v16i8, v16i8, int_arm_neon_vcnt>; 2280 2281// Vector Move Operations. 2282 2283// VMOV : Vector Move (Register) 2284 2285def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src), 2286 IIC_VMOVD, "vmov\t$dst, $src", "", []>; 2287def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src), 2288 IIC_VMOVD, "vmov\t$dst, $src", "", []>; 2289 2290// VMOV : Vector Move (Immediate) 2291 2292// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm. 2293def VMOV_get_imm8 : SDNodeXForm<build_vector, [{ 2294 return ARM::getVMOVImm(N, 1, *CurDAG); 2295}]>; 2296def vmovImm8 : PatLeaf<(build_vector), [{ 2297 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0; 2298}], VMOV_get_imm8>; 2299 2300// VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm. 2301def VMOV_get_imm16 : SDNodeXForm<build_vector, [{ 2302 return ARM::getVMOVImm(N, 2, *CurDAG); 2303}]>; 2304def vmovImm16 : PatLeaf<(build_vector), [{ 2305 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0; 2306}], VMOV_get_imm16>; 2307 2308// VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm. 2309def VMOV_get_imm32 : SDNodeXForm<build_vector, [{ 2310 return ARM::getVMOVImm(N, 4, *CurDAG); 2311}]>; 2312def vmovImm32 : PatLeaf<(build_vector), [{ 2313 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0; 2314}], VMOV_get_imm32>; 2315 2316// VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm. 2317def VMOV_get_imm64 : SDNodeXForm<build_vector, [{ 2318 return ARM::getVMOVImm(N, 8, *CurDAG); 2319}]>; 2320def vmovImm64 : PatLeaf<(build_vector), [{ 2321 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0; 2322}], VMOV_get_imm64>; 2323 2324// Note: Some of the cmode bits in the following VMOV instructions need to 2325// be encoded based on the immed values. 2326 2327def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst), 2328 (ins i8imm:$SIMM), IIC_VMOVImm, 2329 "vmov.i8\t$dst, $SIMM", "", 2330 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>; 2331def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst), 2332 (ins i8imm:$SIMM), IIC_VMOVImm, 2333 "vmov.i8\t$dst, $SIMM", "", 2334 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>; 2335 2336def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst), 2337 (ins i16imm:$SIMM), IIC_VMOVImm, 2338 "vmov.i16\t$dst, $SIMM", "", 2339 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>; 2340def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst), 2341 (ins i16imm:$SIMM), IIC_VMOVImm, 2342 "vmov.i16\t$dst, $SIMM", "", 2343 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>; 2344 2345def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst), 2346 (ins i32imm:$SIMM), IIC_VMOVImm, 2347 "vmov.i32\t$dst, $SIMM", "", 2348 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>; 2349def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst), 2350 (ins i32imm:$SIMM), IIC_VMOVImm, 2351 "vmov.i32\t$dst, $SIMM", "", 2352 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>; 2353 2354def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst), 2355 (ins i64imm:$SIMM), IIC_VMOVImm, 2356 "vmov.i64\t$dst, $SIMM", "", 2357 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>; 2358def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst), 2359 (ins i64imm:$SIMM), IIC_VMOVImm, 2360 "vmov.i64\t$dst, $SIMM", "", 2361 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>; 2362 2363// VMOV : Vector Get Lane (move scalar to ARM core register) 2364 2365def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00, 2366 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane), 2367 IIC_VMOVSI, "vmov", ".s8\t$dst, $src[$lane]", 2368 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src), 2369 imm:$lane))]>; 2370def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01, 2371 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane), 2372 IIC_VMOVSI, "vmov", ".s16\t$dst, $src[$lane]", 2373 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src), 2374 imm:$lane))]>; 2375def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00, 2376 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane), 2377 IIC_VMOVSI, "vmov", ".u8\t$dst, $src[$lane]", 2378 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src), 2379 imm:$lane))]>; 2380def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01, 2381 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane), 2382 IIC_VMOVSI, "vmov", ".u16\t$dst, $src[$lane]", 2383 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src), 2384 imm:$lane))]>; 2385def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00, 2386 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane), 2387 IIC_VMOVSI, "vmov", ".32\t$dst, $src[$lane]", 2388 [(set GPR:$dst, (extractelt (v2i32 DPR:$src), 2389 imm:$lane))]>; 2390// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td 2391def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane), 2392 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src, 2393 (DSubReg_i8_reg imm:$lane))), 2394 (SubReg_i8_lane imm:$lane))>; 2395def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane), 2396 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src, 2397 (DSubReg_i16_reg imm:$lane))), 2398 (SubReg_i16_lane imm:$lane))>; 2399def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane), 2400 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src, 2401 (DSubReg_i8_reg imm:$lane))), 2402 (SubReg_i8_lane imm:$lane))>; 2403def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane), 2404 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src, 2405 (DSubReg_i16_reg imm:$lane))), 2406 (SubReg_i16_lane imm:$lane))>; 2407def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane), 2408 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src, 2409 (DSubReg_i32_reg imm:$lane))), 2410 (SubReg_i32_lane imm:$lane))>; 2411def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2), 2412 (EXTRACT_SUBREG (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2), 2413 (SSubReg_f32_reg imm:$src2))>; 2414def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2), 2415 (EXTRACT_SUBREG (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2), 2416 (SSubReg_f32_reg imm:$src2))>; 2417//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2), 2418// (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>; 2419def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2), 2420 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>; 2421 2422 2423// VMOV : Vector Set Lane (move ARM core register to scalar) 2424 2425let Constraints = "$src1 = $dst" in { 2426def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst), 2427 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane), 2428 IIC_VMOVISL, "vmov", ".8\t$dst[$lane], $src2", 2429 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1), 2430 GPR:$src2, imm:$lane))]>; 2431def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst), 2432 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane), 2433 IIC_VMOVISL, "vmov", ".16\t$dst[$lane], $src2", 2434 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1), 2435 GPR:$src2, imm:$lane))]>; 2436def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst), 2437 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane), 2438 IIC_VMOVISL, "vmov", ".32\t$dst[$lane], $src2", 2439 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1), 2440 GPR:$src2, imm:$lane))]>; 2441} 2442def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane), 2443 (v16i8 (INSERT_SUBREG QPR:$src1, 2444 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1, 2445 (DSubReg_i8_reg imm:$lane))), 2446 GPR:$src2, (SubReg_i8_lane imm:$lane)), 2447 (DSubReg_i8_reg imm:$lane)))>; 2448def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane), 2449 (v8i16 (INSERT_SUBREG QPR:$src1, 2450 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1, 2451 (DSubReg_i16_reg imm:$lane))), 2452 GPR:$src2, (SubReg_i16_lane imm:$lane)), 2453 (DSubReg_i16_reg imm:$lane)))>; 2454def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane), 2455 (v4i32 (INSERT_SUBREG QPR:$src1, 2456 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1, 2457 (DSubReg_i32_reg imm:$lane))), 2458 GPR:$src2, (SubReg_i32_lane imm:$lane)), 2459 (DSubReg_i32_reg imm:$lane)))>; 2460 2461def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)), 2462 (INSERT_SUBREG (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2), 2463 SPR:$src2, (SSubReg_f32_reg imm:$src3))>; 2464def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)), 2465 (INSERT_SUBREG (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2), 2466 SPR:$src2, (SSubReg_f32_reg imm:$src3))>; 2467 2468//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), 2469// (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>; 2470def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), 2471 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>; 2472 2473def : Pat<(v2f32 (scalar_to_vector SPR:$src)), 2474 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>; 2475def : Pat<(v2f64 (scalar_to_vector DPR:$src)), 2476 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>; 2477def : Pat<(v4f32 (scalar_to_vector SPR:$src)), 2478 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>; 2479 2480def : Pat<(v8i8 (scalar_to_vector GPR:$src)), 2481 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; 2482def : Pat<(v4i16 (scalar_to_vector GPR:$src)), 2483 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; 2484def : Pat<(v2i32 (scalar_to_vector GPR:$src)), 2485 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; 2486 2487def : Pat<(v16i8 (scalar_to_vector GPR:$src)), 2488 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 2489 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)), 2490 arm_dsubreg_0)>; 2491def : Pat<(v8i16 (scalar_to_vector GPR:$src)), 2492 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 2493 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)), 2494 arm_dsubreg_0)>; 2495def : Pat<(v4i32 (scalar_to_vector GPR:$src)), 2496 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 2497 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)), 2498 arm_dsubreg_0)>; 2499 2500// VDUP : Vector Duplicate (from ARM core register to all elements) 2501 2502class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty> 2503 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src), 2504 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"), 2505 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>; 2506class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty> 2507 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src), 2508 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"), 2509 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>; 2510 2511def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>; 2512def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>; 2513def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>; 2514def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>; 2515def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>; 2516def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>; 2517 2518def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src), 2519 IIC_VMOVIS, "vdup", ".32\t$dst, $src", 2520 [(set DPR:$dst, (v2f32 (NEONvdup 2521 (f32 (bitconvert GPR:$src)))))]>; 2522def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src), 2523 IIC_VMOVIS, "vdup", ".32\t$dst, $src", 2524 [(set QPR:$dst, (v4f32 (NEONvdup 2525 (f32 (bitconvert GPR:$src)))))]>; 2526 2527// VDUP : Vector Duplicate Lane (from scalar to all elements) 2528 2529class VDUPLND<string OpcodeStr, ValueType Ty> 2530 : N2VDup<0b11, 0b11, 0b11000, 0, 0, 2531 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD, 2532 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", 2533 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>; 2534 2535class VDUPLNQ<string OpcodeStr, ValueType ResTy, ValueType OpTy> 2536 : N2VDup<0b11, 0b11, 0b11000, 1, 0, 2537 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD, 2538 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", 2539 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>; 2540 2541// Inst{19-16} is partially specified depending on the element size. 2542 2543def VDUPLN8d : VDUPLND<"vdup.8", v8i8> { let Inst{16} = 1; } 2544def VDUPLN16d : VDUPLND<"vdup.16", v4i16> { let Inst{17-16} = 0b10; } 2545def VDUPLN32d : VDUPLND<"vdup.32", v2i32> { let Inst{18-16} = 0b100; } 2546def VDUPLNfd : VDUPLND<"vdup.32", v2f32> { let Inst{18-16} = 0b100; } 2547def VDUPLN8q : VDUPLNQ<"vdup.8", v16i8, v8i8> { let Inst{16} = 1; } 2548def VDUPLN16q : VDUPLNQ<"vdup.16", v8i16, v4i16> { let Inst{17-16} = 0b10; } 2549def VDUPLN32q : VDUPLNQ<"vdup.32", v4i32, v2i32> { let Inst{18-16} = 0b100; } 2550def VDUPLNfq : VDUPLNQ<"vdup.32", v4f32, v2f32> { let Inst{18-16} = 0b100; } 2551 2552def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)), 2553 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src, 2554 (DSubReg_i8_reg imm:$lane))), 2555 (SubReg_i8_lane imm:$lane)))>; 2556def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)), 2557 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src, 2558 (DSubReg_i16_reg imm:$lane))), 2559 (SubReg_i16_lane imm:$lane)))>; 2560def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)), 2561 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src, 2562 (DSubReg_i32_reg imm:$lane))), 2563 (SubReg_i32_lane imm:$lane)))>; 2564def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)), 2565 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src, 2566 (DSubReg_i32_reg imm:$lane))), 2567 (SubReg_i32_lane imm:$lane)))>; 2568 2569def VDUPfdf : N2VDup<0b11, 0b11, 0b11000, 0, 0, 2570 (outs DPR:$dst), (ins SPR:$src), 2571 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "", 2572 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]> { 2573 let Inst{18-16} = 0b100; 2574} 2575 2576def VDUPfqf : N2VDup<0b11, 0b11, 0b11000, 1, 0, 2577 (outs QPR:$dst), (ins SPR:$src), 2578 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "", 2579 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]> { 2580 let Inst{18-16} = 0b100; 2581} 2582 2583def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)), 2584 (INSERT_SUBREG QPR:$src, 2585 (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))), 2586 (DSubReg_f64_other_reg imm:$lane))>; 2587def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)), 2588 (INSERT_SUBREG QPR:$src, 2589 (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))), 2590 (DSubReg_f64_other_reg imm:$lane))>; 2591 2592// VMOVN : Vector Narrowing Move 2593defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD, "vmovn.i", 2594 int_arm_neon_vmovn>; 2595// VQMOVN : Vector Saturating Narrowing Move 2596defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, "vqmovn.s", 2597 int_arm_neon_vqmovns>; 2598defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD, "vqmovn.u", 2599 int_arm_neon_vqmovnu>; 2600defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD, "vqmovun.s", 2601 int_arm_neon_vqmovnsu>; 2602// VMOVL : Vector Lengthening Move 2603defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl.s", int_arm_neon_vmovls>; 2604defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl.u", int_arm_neon_vmovlu>; 2605 2606// Vector Conversions. 2607 2608// VCVT : Vector Convert Between Floating-Point and Integers 2609def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32", 2610 v2i32, v2f32, fp_to_sint>; 2611def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32", 2612 v2i32, v2f32, fp_to_uint>; 2613def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32", 2614 v2f32, v2i32, sint_to_fp>; 2615def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32", 2616 v2f32, v2i32, uint_to_fp>; 2617 2618def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32", 2619 v4i32, v4f32, fp_to_sint>; 2620def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32", 2621 v4i32, v4f32, fp_to_uint>; 2622def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32", 2623 v4f32, v4i32, sint_to_fp>; 2624def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32", 2625 v4f32, v4i32, uint_to_fp>; 2626 2627// VCVT : Vector Convert Between Floating-Point and Fixed-Point. 2628def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt.s32.f32", 2629 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>; 2630def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt.u32.f32", 2631 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>; 2632def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt.f32.s32", 2633 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>; 2634def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt.f32.u32", 2635 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>; 2636 2637def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt.s32.f32", 2638 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>; 2639def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt.u32.f32", 2640 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>; 2641def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt.f32.s32", 2642 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>; 2643def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt.f32.u32", 2644 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>; 2645 2646// Vector Reverse. 2647 2648// VREV64 : Vector Reverse elements within 64-bit doublewords 2649 2650class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty> 2651 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst), 2652 (ins DPR:$src), IIC_VMOVD, 2653 !strconcat(OpcodeStr, "\t$dst, $src"), "", 2654 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>; 2655class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty> 2656 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst), 2657 (ins QPR:$src), IIC_VMOVD, 2658 !strconcat(OpcodeStr, "\t$dst, $src"), "", 2659 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>; 2660 2661def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>; 2662def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>; 2663def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>; 2664def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>; 2665 2666def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>; 2667def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>; 2668def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>; 2669def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>; 2670 2671// VREV32 : Vector Reverse elements within 32-bit words 2672 2673class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty> 2674 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst), 2675 (ins DPR:$src), IIC_VMOVD, 2676 !strconcat(OpcodeStr, "\t$dst, $src"), "", 2677 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>; 2678class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty> 2679 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst), 2680 (ins QPR:$src), IIC_VMOVD, 2681 !strconcat(OpcodeStr, "\t$dst, $src"), "", 2682 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>; 2683 2684def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>; 2685def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>; 2686 2687def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>; 2688def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>; 2689 2690// VREV16 : Vector Reverse elements within 16-bit halfwords 2691 2692class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty> 2693 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst), 2694 (ins DPR:$src), IIC_VMOVD, 2695 !strconcat(OpcodeStr, "\t$dst, $src"), "", 2696 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>; 2697class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty> 2698 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst), 2699 (ins QPR:$src), IIC_VMOVD, 2700 !strconcat(OpcodeStr, "\t$dst, $src"), "", 2701 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>; 2702 2703def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>; 2704def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>; 2705 2706// Other Vector Shuffles. 2707 2708// VEXT : Vector Extract 2709 2710class VEXTd<string OpcodeStr, ValueType Ty> 2711 : N3VImm<0,1,0b11,0,0, (outs DPR:$dst), 2712 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD, 2713 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "", 2714 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs), 2715 (Ty DPR:$rhs), imm:$index)))]>; 2716 2717class VEXTq<string OpcodeStr, ValueType Ty> 2718 : N3VImm<0,1,0b11,1,0, (outs QPR:$dst), 2719 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ, 2720 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "", 2721 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs), 2722 (Ty QPR:$rhs), imm:$index)))]>; 2723 2724def VEXTd8 : VEXTd<"vext.8", v8i8>; 2725def VEXTd16 : VEXTd<"vext.16", v4i16>; 2726def VEXTd32 : VEXTd<"vext.32", v2i32>; 2727def VEXTdf : VEXTd<"vext.32", v2f32>; 2728 2729def VEXTq8 : VEXTq<"vext.8", v16i8>; 2730def VEXTq16 : VEXTq<"vext.16", v8i16>; 2731def VEXTq32 : VEXTq<"vext.32", v4i32>; 2732def VEXTqf : VEXTq<"vext.32", v4f32>; 2733 2734// VTRN : Vector Transpose 2735 2736def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">; 2737def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">; 2738def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">; 2739 2740def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn.8">; 2741def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn.16">; 2742def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn.32">; 2743 2744// VUZP : Vector Unzip (Deinterleave) 2745 2746def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">; 2747def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">; 2748def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">; 2749 2750def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp.8">; 2751def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp.16">; 2752def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp.32">; 2753 2754// VZIP : Vector Zip (Interleave) 2755 2756def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">; 2757def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">; 2758def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">; 2759 2760def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip.8">; 2761def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip.16">; 2762def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip.32">; 2763 2764// Vector Table Lookup and Table Extension. 2765 2766// VTBL : Vector Table Lookup 2767def VTBL1 2768 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst), 2769 (ins DPR:$tbl1, DPR:$src), IIC_VTB1, 2770 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "", 2771 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>; 2772let hasExtraSrcRegAllocReq = 1 in { 2773def VTBL2 2774 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst), 2775 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2, 2776 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "", 2777 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2 2778 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>; 2779def VTBL3 2780 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst), 2781 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3, 2782 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "", 2783 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3 2784 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>; 2785def VTBL4 2786 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst), 2787 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4, 2788 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "", 2789 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2, 2790 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>; 2791} // hasExtraSrcRegAllocReq = 1 2792 2793// VTBX : Vector Table Extension 2794def VTBX1 2795 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst), 2796 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1, 2797 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst", 2798 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1 2799 DPR:$orig, DPR:$tbl1, DPR:$src)))]>; 2800let hasExtraSrcRegAllocReq = 1 in { 2801def VTBX2 2802 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst), 2803 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2, 2804 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst", 2805 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2 2806 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>; 2807def VTBX3 2808 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst), 2809 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3, 2810 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst", 2811 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1, 2812 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>; 2813def VTBX4 2814 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1, 2815 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4, 2816 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst", 2817 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1, 2818 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>; 2819} // hasExtraSrcRegAllocReq = 1 2820 2821//===----------------------------------------------------------------------===// 2822// NEON instructions for single-precision FP math 2823//===----------------------------------------------------------------------===// 2824 2825// These need separate instructions because they must use DPR_VFP2 register 2826// class which have SPR sub-registers. 2827 2828// Vector Add Operations used for single-precision FP 2829let neverHasSideEffects = 1 in 2830def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>; 2831def : N3VDsPat<fadd, VADDfd_sfp>; 2832 2833// Vector Sub Operations used for single-precision FP 2834let neverHasSideEffects = 1 in 2835def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>; 2836def : N3VDsPat<fsub, VSUBfd_sfp>; 2837 2838// Vector Multiply Operations used for single-precision FP 2839let neverHasSideEffects = 1 in 2840def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>; 2841def : N3VDsPat<fmul, VMULfd_sfp>; 2842 2843// Vector Multiply-Accumulate/Subtract used for single-precision FP 2844let neverHasSideEffects = 1 in 2845def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32,fmul,fadd>; 2846def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>; 2847 2848let neverHasSideEffects = 1 in 2849def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32,fmul,fsub>; 2850def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>; 2851 2852// Vector Absolute used for single-precision FP 2853let neverHasSideEffects = 1 in 2854def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 2855 IIC_VUNAD, "vabs.f32", 2856 v2f32, v2f32, int_arm_neon_vabs>; 2857def : N2VDIntsPat<fabs, VABSfd_sfp>; 2858 2859// Vector Negate used for single-precision FP 2860let neverHasSideEffects = 1 in 2861def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, 2862 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD, 2863 "vneg.f32\t$dst, $src", "", []>; 2864def : N2VDIntsPat<fneg, VNEGf32d_sfp>; 2865 2866// Vector Convert between single-precision FP and integer 2867let neverHasSideEffects = 1 in 2868def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32", 2869 v2i32, v2f32, fp_to_sint>; 2870def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>; 2871 2872let neverHasSideEffects = 1 in 2873def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32", 2874 v2i32, v2f32, fp_to_uint>; 2875def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>; 2876 2877let neverHasSideEffects = 1 in 2878def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32", 2879 v2f32, v2i32, sint_to_fp>; 2880def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>; 2881 2882let neverHasSideEffects = 1 in 2883def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32", 2884 v2f32, v2i32, uint_to_fp>; 2885def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>; 2886 2887//===----------------------------------------------------------------------===// 2888// Non-Instruction Patterns 2889//===----------------------------------------------------------------------===// 2890 2891// bit_convert 2892def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>; 2893def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>; 2894def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>; 2895def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>; 2896def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>; 2897def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>; 2898def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>; 2899def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>; 2900def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>; 2901def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>; 2902def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>; 2903def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>; 2904def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>; 2905def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>; 2906def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>; 2907def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>; 2908def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>; 2909def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>; 2910def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>; 2911def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>; 2912def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>; 2913def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>; 2914def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>; 2915def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>; 2916def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>; 2917def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>; 2918def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>; 2919def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>; 2920def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>; 2921def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>; 2922 2923def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>; 2924def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>; 2925def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>; 2926def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>; 2927def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>; 2928def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>; 2929def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>; 2930def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>; 2931def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>; 2932def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>; 2933def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>; 2934def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>; 2935def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>; 2936def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>; 2937def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>; 2938def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>; 2939def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>; 2940def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>; 2941def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>; 2942def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>; 2943def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>; 2944def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>; 2945def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>; 2946def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>; 2947def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>; 2948def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>; 2949def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>; 2950def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>; 2951def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>; 2952def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>; 2953