ARMInstrNEON.td revision e2be3383447e747354ae2dfe965f8617136f88d6
1//===- ARMInstrNEON.td - NEON support for ARM -----------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM NEON instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// NEON-specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>; 19 20def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>; 21def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>; 22def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>; 23def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>; 24def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>; 25def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>; 26 27// Types for vector shift by immediates. The "SHX" version is for long and 28// narrow operations where the source and destination vectors have different 29// types. The "SHINS" version is for shift and insert operations. 30def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 31 SDTCisVT<2, i32>]>; 32def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, 33 SDTCisVT<2, i32>]>; 34def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; 36 37def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>; 38def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>; 39def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>; 40def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>; 41def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>; 42def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>; 43def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>; 44 45def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>; 46def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>; 47def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>; 48 49def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>; 50def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>; 51def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>; 52def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>; 53def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>; 54def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>; 55 56def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>; 57def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>; 58def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>; 59 60def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>; 61def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>; 62 63def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, 64 SDTCisVT<2, i32>]>; 65def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; 66def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; 67 68def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ", 69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>; 70 71def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 72def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>, 73 SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>; 74def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>, 75 SDTCisSameAs<0, 2>, 76 SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>; 77def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2, 78 [SDNPHasChain, SDNPMayLoad]>; 79def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3, 80 [SDNPHasChain, SDNPMayLoad]>; 81def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4, 82 [SDNPHasChain, SDNPMayLoad]>; 83 84def SDTARMVST2 : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>]>; 85def SDTARMVST3 : SDTypeProfile<0, 4, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 86 SDTCisSameAs<1, 3>]>; 87def SDTARMVST4 : SDTypeProfile<0, 5, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 88 SDTCisSameAs<1, 3>, 89 SDTCisSameAs<1, 4>]>; 90 91def NEONvst2d : SDNode<"ARMISD::VST2D", SDTARMVST2, 92 [SDNPHasChain, SDNPMayStore]>; 93def NEONvst3d : SDNode<"ARMISD::VST3D", SDTARMVST3, 94 [SDNPHasChain, SDNPMayStore]>; 95def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4, 96 [SDNPHasChain, SDNPMayStore]>; 97 98//===----------------------------------------------------------------------===// 99// NEON operand definitions 100//===----------------------------------------------------------------------===// 101 102// addrmode_neonldstm := reg 103// 104/* TODO: Take advantage of vldm. 105def addrmode_neonldstm : Operand<i32>, 106 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> { 107 let PrintMethod = "printAddrNeonLdStMOperand"; 108 let MIOperandInfo = (ops GPR, i32imm); 109} 110*/ 111 112//===----------------------------------------------------------------------===// 113// NEON load / store instructions 114//===----------------------------------------------------------------------===// 115 116/* TODO: Take advantage of vldm. 117let mayLoad = 1 in { 118def VLDMD : NI<(outs), 119 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), 120 NoItinerary, 121 "vldm${addr:submode} ${addr:base}, $dst1", 122 []> { 123 let Inst{27-25} = 0b110; 124 let Inst{20} = 1; 125 let Inst{11-9} = 0b101; 126} 127 128def VLDMS : NI<(outs), 129 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), 130 NoItinerary, 131 "vldm${addr:submode} ${addr:base}, $dst1", 132 []> { 133 let Inst{27-25} = 0b110; 134 let Inst{20} = 1; 135 let Inst{11-9} = 0b101; 136} 137} 138*/ 139 140// Use vldmia to load a Q register as a D register pair. 141def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), 142 NoItinerary, 143 "vldmia $addr, ${dst:dregpair}", 144 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> { 145 let Inst{27-25} = 0b110; 146 let Inst{24} = 0; // P bit 147 let Inst{23} = 1; // U bit 148 let Inst{20} = 1; 149 let Inst{11-9} = 0b101; 150} 151 152// Use vstmia to store a Q register as a D register pair. 153def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), 154 NoItinerary, 155 "vstmia $addr, ${src:dregpair}", 156 [(store (v2f64 QPR:$src), addrmode4:$addr)]> { 157 let Inst{27-25} = 0b110; 158 let Inst{24} = 0; // P bit 159 let Inst{23} = 1; // U bit 160 let Inst{20} = 0; 161 let Inst{11-9} = 0b101; 162} 163 164// VLD1 : Vector Load (multiple single elements) 165class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp> 166 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr), 167 NoItinerary, 168 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), 169 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>; 170class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp> 171 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr), 172 NoItinerary, 173 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), 174 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>; 175 176def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1i>; 177def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1i>; 178def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1i>; 179def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1f>; 180def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1i>; 181 182def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1i>; 183def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1i>; 184def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>; 185def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>; 186def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>; 187 188// VLD2 : Vector Load (multiple 2-element structures) 189class VLD2D<string OpcodeStr> 190 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr), 191 NoItinerary, 192 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>; 193 194def VLD2d8 : VLD2D<"vld2.8">; 195def VLD2d16 : VLD2D<"vld2.16">; 196def VLD2d32 : VLD2D<"vld2.32">; 197 198// VLD3 : Vector Load (multiple 3-element structures) 199class VLD3D<string OpcodeStr> 200 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr), 201 NoItinerary, 202 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>; 203 204def VLD3d8 : VLD3D<"vld3.8">; 205def VLD3d16 : VLD3D<"vld3.16">; 206def VLD3d32 : VLD3D<"vld3.32">; 207 208// VLD4 : Vector Load (multiple 4-element structures) 209class VLD4D<string OpcodeStr> 210 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), 211 (ins addrmode6:$addr), 212 NoItinerary, 213 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>; 214 215def VLD4d8 : VLD4D<"vld4.8">; 216def VLD4d16 : VLD4D<"vld4.16">; 217def VLD4d32 : VLD4D<"vld4.32">; 218 219// VST1 : Vector Store (multiple single elements) 220class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp> 221 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src), 222 NoItinerary, 223 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), 224 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>; 225class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp> 226 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src), 227 NoItinerary, 228 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), 229 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>; 230 231def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>; 232def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>; 233def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>; 234def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>; 235def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>; 236 237def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>; 238def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>; 239def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>; 240def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>; 241def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>; 242 243// VST2 : Vector Store (multiple 2-element structures) 244class VST2D<string OpcodeStr> 245 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary, 246 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), []>; 247 248def VST2d8 : VST2D<"vst2.8">; 249def VST2d16 : VST2D<"vst2.16">; 250def VST2d32 : VST2D<"vst2.32">; 251 252// VST3 : Vector Store (multiple 3-element structures) 253class VST3D<string OpcodeStr> 254 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), 255 NoItinerary, 256 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), []>; 257 258def VST3d8 : VST3D<"vst3.8">; 259def VST3d16 : VST3D<"vst3.16">; 260def VST3d32 : VST3D<"vst3.32">; 261 262// VST4 : Vector Store (multiple 4-element structures) 263class VST4D<string OpcodeStr> 264 : NLdSt<(outs), (ins addrmode6:$addr, 265 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary, 266 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), []>; 267 268def VST4d8 : VST4D<"vst4.8">; 269def VST4d16 : VST4D<"vst4.16">; 270def VST4d32 : VST4D<"vst4.32">; 271 272 273//===----------------------------------------------------------------------===// 274// NEON pattern fragments 275//===----------------------------------------------------------------------===// 276 277// Extract D sub-registers of Q registers. 278// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6) 279def DSubReg_i8_reg : SDNodeXForm<imm, [{ 280 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32); 281}]>; 282def DSubReg_i16_reg : SDNodeXForm<imm, [{ 283 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32); 284}]>; 285def DSubReg_i32_reg : SDNodeXForm<imm, [{ 286 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32); 287}]>; 288def DSubReg_f64_reg : SDNodeXForm<imm, [{ 289 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32); 290}]>; 291 292// Extract S sub-registers of Q registers. 293// (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.) 294def SSubReg_f32_reg : SDNodeXForm<imm, [{ 295 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32); 296}]>; 297 298// Translate lane numbers from Q registers to D subregs. 299def SubReg_i8_lane : SDNodeXForm<imm, [{ 300 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32); 301}]>; 302def SubReg_i16_lane : SDNodeXForm<imm, [{ 303 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32); 304}]>; 305def SubReg_i32_lane : SDNodeXForm<imm, [{ 306 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32); 307}]>; 308 309//===----------------------------------------------------------------------===// 310// Instruction Classes 311//===----------------------------------------------------------------------===// 312 313// Basic 2-register operations, both double- and quad-register. 314class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 315 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 316 ValueType ResTy, ValueType OpTy, SDNode OpNode> 317 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst), 318 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", 319 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>; 320class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 321 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 322 ValueType ResTy, ValueType OpTy, SDNode OpNode> 323 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst), 324 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", 325 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>; 326 327// Basic 2-register intrinsics, both double- and quad-register. 328class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 329 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 330 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 331 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst), 332 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", 333 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>; 334class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 335 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 336 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 337 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst), 338 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", 339 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>; 340 341// Basic 2-register operations, scalar single-precision 342class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 343 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 344 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 345 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, 346 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary, 347 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>; 348 349class N2VDIntsPat<SDNode OpNode, NeonI Inst> 350 : NEONFPPat<(f32 (OpNode SPR:$a)), 351 (EXTRACT_SUBREG 352 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)), 353 arm_ssubreg_0)>; 354 355// Narrow 2-register intrinsics. 356class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 357 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, 358 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp> 359 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst), 360 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", 361 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>; 362 363// Long 2-register intrinsics. (This is currently only used for VMOVL and is 364// derived from N2VImm instead of N2V because of the way the size is encoded.) 365class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 366 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD, 367 Intrinsic IntOp> 368 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst), 369 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", 370 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>; 371 372// 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register. 373class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr> 374 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2), 375 (ins DPR:$src1, DPR:$src2), NoItinerary, 376 !strconcat(OpcodeStr, "\t$dst1, $dst2"), 377 "$src1 = $dst1, $src2 = $dst2", []>; 378class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr> 379 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2), 380 (ins QPR:$src1, QPR:$src2), NoItinerary, 381 !strconcat(OpcodeStr, "\t$dst1, $dst2"), 382 "$src1 = $dst1, $src2 = $dst2", []>; 383 384// Basic 3-register operations, both double- and quad-register. 385class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 386 string OpcodeStr, ValueType ResTy, ValueType OpTy, 387 SDNode OpNode, bit Commutable> 388 : N3V<op24, op23, op21_20, op11_8, 0, op4, 389 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary, 390 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 391 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> { 392 let isCommutable = Commutable; 393} 394class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 395 string OpcodeStr, ValueType ResTy, ValueType OpTy, 396 SDNode OpNode, bit Commutable> 397 : N3V<op24, op23, op21_20, op11_8, 1, op4, 398 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary, 399 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 400 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> { 401 let isCommutable = Commutable; 402} 403 404// Basic 3-register operations, scalar single-precision 405class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 406 string OpcodeStr, ValueType ResTy, ValueType OpTy, 407 SDNode OpNode, bit Commutable> 408 : N3V<op24, op23, op21_20, op11_8, 0, op4, 409 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary, 410 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> { 411 let isCommutable = Commutable; 412} 413class N3VDsPat<SDNode OpNode, NeonI Inst> 414 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)), 415 (EXTRACT_SUBREG 416 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0), 417 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)), 418 arm_ssubreg_0)>; 419 420// Basic 3-register intrinsics, both double- and quad-register. 421class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 422 string OpcodeStr, ValueType ResTy, ValueType OpTy, 423 Intrinsic IntOp, bit Commutable> 424 : N3V<op24, op23, op21_20, op11_8, 0, op4, 425 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary, 426 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 427 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> { 428 let isCommutable = Commutable; 429} 430class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 431 string OpcodeStr, ValueType ResTy, ValueType OpTy, 432 Intrinsic IntOp, bit Commutable> 433 : N3V<op24, op23, op21_20, op11_8, 1, op4, 434 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary, 435 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 436 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> { 437 let isCommutable = Commutable; 438} 439 440// Multiply-Add/Sub operations, both double- and quad-register. 441class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 442 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode> 443 : N3V<op24, op23, op21_20, op11_8, 0, op4, 444 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary, 445 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 446 [(set DPR:$dst, (Ty (OpNode DPR:$src1, 447 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>; 448class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 449 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode> 450 : N3V<op24, op23, op21_20, op11_8, 1, op4, 451 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary, 452 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 453 [(set QPR:$dst, (Ty (OpNode QPR:$src1, 454 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>; 455 456// Multiply-Add/Sub operations, scalar single-precision 457class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 458 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode> 459 : N3V<op24, op23, op21_20, op11_8, 0, op4, 460 (outs DPR_VFP2:$dst), 461 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary, 462 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>; 463 464class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst> 465 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))), 466 (EXTRACT_SUBREG 467 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0), 468 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0), 469 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)), 470 arm_ssubreg_0)>; 471 472// Neon 3-argument intrinsics, both double- and quad-register. 473// The destination register is also used as the first source operand register. 474class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 475 string OpcodeStr, ValueType ResTy, ValueType OpTy, 476 Intrinsic IntOp> 477 : N3V<op24, op23, op21_20, op11_8, 0, op4, 478 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary, 479 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 480 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), 481 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>; 482class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 483 string OpcodeStr, ValueType ResTy, ValueType OpTy, 484 Intrinsic IntOp> 485 : N3V<op24, op23, op21_20, op11_8, 1, op4, 486 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary, 487 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 488 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), 489 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>; 490 491// Neon Long 3-argument intrinsic. The destination register is 492// a quad-register and is also used as the first source operand register. 493class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 494 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp> 495 : N3V<op24, op23, op21_20, op11_8, 0, op4, 496 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary, 497 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 498 [(set QPR:$dst, 499 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>; 500 501// Narrowing 3-register intrinsics. 502class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 503 string OpcodeStr, ValueType TyD, ValueType TyQ, 504 Intrinsic IntOp, bit Commutable> 505 : N3V<op24, op23, op21_20, op11_8, 0, op4, 506 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary, 507 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 508 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> { 509 let isCommutable = Commutable; 510} 511 512// Long 3-register intrinsics. 513class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 514 string OpcodeStr, ValueType TyQ, ValueType TyD, 515 Intrinsic IntOp, bit Commutable> 516 : N3V<op24, op23, op21_20, op11_8, 0, op4, 517 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary, 518 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 519 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> { 520 let isCommutable = Commutable; 521} 522 523// Wide 3-register intrinsics. 524class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 525 string OpcodeStr, ValueType TyQ, ValueType TyD, 526 Intrinsic IntOp, bit Commutable> 527 : N3V<op24, op23, op21_20, op11_8, 0, op4, 528 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary, 529 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 530 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> { 531 let isCommutable = Commutable; 532} 533 534// Pairwise long 2-register intrinsics, both double- and quad-register. 535class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 536 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 537 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 538 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst), 539 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", 540 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>; 541class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 542 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 543 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 544 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst), 545 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", 546 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>; 547 548// Pairwise long 2-register accumulate intrinsics, 549// both double- and quad-register. 550// The destination register is also used as the first source operand register. 551class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 552 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 553 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 554 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, 555 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary, 556 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst", 557 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>; 558class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 559 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 560 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 561 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, 562 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary, 563 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst", 564 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>; 565 566// Shift by immediate, 567// both double- and quad-register. 568class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 569 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode> 570 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4, 571 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary, 572 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 573 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>; 574class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 575 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode> 576 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4, 577 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary, 578 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 579 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>; 580 581// Long shift by immediate. 582class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 583 bit op6, bit op4, string OpcodeStr, ValueType ResTy, 584 ValueType OpTy, SDNode OpNode> 585 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, 586 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary, 587 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 588 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src), 589 (i32 imm:$SIMM))))]>; 590 591// Narrow shift by immediate. 592class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 593 bit op6, bit op4, string OpcodeStr, ValueType ResTy, 594 ValueType OpTy, SDNode OpNode> 595 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, 596 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary, 597 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 598 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src), 599 (i32 imm:$SIMM))))]>; 600 601// Shift right by immediate and accumulate, 602// both double- and quad-register. 603class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 604 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> 605 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4, 606 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), 607 NoItinerary, 608 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 609 [(set DPR:$dst, (Ty (add DPR:$src1, 610 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>; 611class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 612 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> 613 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4, 614 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), 615 NoItinerary, 616 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 617 [(set QPR:$dst, (Ty (add QPR:$src1, 618 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>; 619 620// Shift by immediate and insert, 621// both double- and quad-register. 622class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 623 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> 624 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4, 625 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), 626 NoItinerary, 627 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 628 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>; 629class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 630 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> 631 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4, 632 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), 633 NoItinerary, 634 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 635 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>; 636 637// Convert, with fractional bits immediate, 638// both double- and quad-register. 639class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 640 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, 641 Intrinsic IntOp> 642 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4, 643 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary, 644 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 645 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>; 646class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 647 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, 648 Intrinsic IntOp> 649 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4, 650 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary, 651 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 652 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>; 653 654//===----------------------------------------------------------------------===// 655// Multiclasses 656//===----------------------------------------------------------------------===// 657 658// Neon 3-register vector operations. 659 660// First with only element sizes of 8, 16 and 32 bits: 661multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 662 string OpcodeStr, SDNode OpNode, bit Commutable = 0> { 663 // 64-bit vector types. 664 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 665 v8i8, v8i8, OpNode, Commutable>; 666 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"), 667 v4i16, v4i16, OpNode, Commutable>; 668 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"), 669 v2i32, v2i32, OpNode, Commutable>; 670 671 // 128-bit vector types. 672 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 673 v16i8, v16i8, OpNode, Commutable>; 674 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"), 675 v8i16, v8i16, OpNode, Commutable>; 676 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"), 677 v4i32, v4i32, OpNode, Commutable>; 678} 679 680// ....then also with element size 64 bits: 681multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 682 string OpcodeStr, SDNode OpNode, bit Commutable = 0> 683 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> { 684 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"), 685 v1i64, v1i64, OpNode, Commutable>; 686 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"), 687 v2i64, v2i64, OpNode, Commutable>; 688} 689 690 691// Neon Narrowing 2-register vector intrinsics, 692// source operand element sizes of 16, 32 and 64 bits: 693multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 694 bits<5> op11_7, bit op6, bit op4, string OpcodeStr, 695 Intrinsic IntOp> { 696 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4, 697 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>; 698 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4, 699 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>; 700 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4, 701 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>; 702} 703 704 705// Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL). 706// source operand element sizes of 16, 32 and 64 bits: 707multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, 708 bit op4, string OpcodeStr, Intrinsic IntOp> { 709 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4, 710 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>; 711 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4, 712 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>; 713 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4, 714 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>; 715} 716 717 718// Neon 3-register vector intrinsics. 719 720// First with only element sizes of 16 and 32 bits: 721multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, 722 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { 723 // 64-bit vector types. 724 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"), 725 v4i16, v4i16, IntOp, Commutable>; 726 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"), 727 v2i32, v2i32, IntOp, Commutable>; 728 729 // 128-bit vector types. 730 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"), 731 v8i16, v8i16, IntOp, Commutable>; 732 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"), 733 v4i32, v4i32, IntOp, Commutable>; 734} 735 736// ....then also with element size of 8 bits: 737multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 738 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> 739 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> { 740 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 741 v8i8, v8i8, IntOp, Commutable>; 742 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 743 v16i8, v16i8, IntOp, Commutable>; 744} 745 746// ....then also with element size of 64 bits: 747multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 748 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> 749 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> { 750 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"), 751 v1i64, v1i64, IntOp, Commutable>; 752 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"), 753 v2i64, v2i64, IntOp, Commutable>; 754} 755 756 757// Neon Narrowing 3-register vector intrinsics, 758// source operand element sizes of 16, 32 and 64 bits: 759multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4, 760 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { 761 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"), 762 v8i8, v8i16, IntOp, Commutable>; 763 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"), 764 v4i16, v4i32, IntOp, Commutable>; 765 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"), 766 v2i32, v2i64, IntOp, Commutable>; 767} 768 769 770// Neon Long 3-register vector intrinsics. 771 772// First with only element sizes of 16 and 32 bits: 773multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, 774 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { 775 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"), 776 v4i32, v4i16, IntOp, Commutable>; 777 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"), 778 v2i64, v2i32, IntOp, Commutable>; 779} 780 781// ....then also with element size of 8 bits: 782multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 783 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> 784 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> { 785 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 786 v8i16, v8i8, IntOp, Commutable>; 787} 788 789 790// Neon Wide 3-register vector intrinsics, 791// source operand element sizes of 8, 16 and 32 bits: 792multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 793 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { 794 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 795 v8i16, v8i8, IntOp, Commutable>; 796 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"), 797 v4i32, v4i16, IntOp, Commutable>; 798 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"), 799 v2i64, v2i32, IntOp, Commutable>; 800} 801 802 803// Neon Multiply-Op vector operations, 804// element sizes of 8, 16 and 32 bits: 805multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 806 string OpcodeStr, SDNode OpNode> { 807 // 64-bit vector types. 808 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, 809 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>; 810 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, 811 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>; 812 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, 813 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>; 814 815 // 128-bit vector types. 816 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, 817 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>; 818 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, 819 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>; 820 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, 821 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>; 822} 823 824 825// Neon 3-argument intrinsics, 826// element sizes of 8, 16 and 32 bits: 827multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 828 string OpcodeStr, Intrinsic IntOp> { 829 // 64-bit vector types. 830 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, 831 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>; 832 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, 833 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>; 834 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, 835 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>; 836 837 // 128-bit vector types. 838 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, 839 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>; 840 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, 841 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>; 842 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, 843 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>; 844} 845 846 847// Neon Long 3-argument intrinsics. 848 849// First with only element sizes of 16 and 32 bits: 850multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4, 851 string OpcodeStr, Intrinsic IntOp> { 852 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, 853 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>; 854 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, 855 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>; 856} 857 858// ....then also with element size of 8 bits: 859multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 860 string OpcodeStr, Intrinsic IntOp> 861 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> { 862 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4, 863 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>; 864} 865 866 867// Neon 2-register vector intrinsics, 868// element sizes of 8, 16 and 32 bits: 869multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 870 bits<5> op11_7, bit op4, string OpcodeStr, 871 Intrinsic IntOp> { 872 // 64-bit vector types. 873 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 874 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>; 875 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 876 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>; 877 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 878 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>; 879 880 // 128-bit vector types. 881 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 882 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>; 883 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 884 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>; 885 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 886 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>; 887} 888 889 890// Neon Pairwise long 2-register intrinsics, 891// element sizes of 8, 16 and 32 bits: 892multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 893 bits<5> op11_7, bit op4, 894 string OpcodeStr, Intrinsic IntOp> { 895 // 64-bit vector types. 896 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 897 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>; 898 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 899 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>; 900 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 901 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>; 902 903 // 128-bit vector types. 904 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 905 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>; 906 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 907 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>; 908 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 909 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>; 910} 911 912 913// Neon Pairwise long 2-register accumulate intrinsics, 914// element sizes of 8, 16 and 32 bits: 915multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 916 bits<5> op11_7, bit op4, 917 string OpcodeStr, Intrinsic IntOp> { 918 // 64-bit vector types. 919 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 920 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>; 921 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 922 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>; 923 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 924 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>; 925 926 // 128-bit vector types. 927 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 928 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>; 929 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 930 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>; 931 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 932 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>; 933} 934 935 936// Neon 2-register vector shift by immediate, 937// element sizes of 8, 16, 32 and 64 bits: 938multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 939 string OpcodeStr, SDNode OpNode> { 940 // 64-bit vector types. 941 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4, 942 !strconcat(OpcodeStr, "8"), v8i8, OpNode>; 943 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4, 944 !strconcat(OpcodeStr, "16"), v4i16, OpNode>; 945 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4, 946 !strconcat(OpcodeStr, "32"), v2i32, OpNode>; 947 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4, 948 !strconcat(OpcodeStr, "64"), v1i64, OpNode>; 949 950 // 128-bit vector types. 951 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4, 952 !strconcat(OpcodeStr, "8"), v16i8, OpNode>; 953 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4, 954 !strconcat(OpcodeStr, "16"), v8i16, OpNode>; 955 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4, 956 !strconcat(OpcodeStr, "32"), v4i32, OpNode>; 957 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4, 958 !strconcat(OpcodeStr, "64"), v2i64, OpNode>; 959} 960 961 962// Neon Shift-Accumulate vector operations, 963// element sizes of 8, 16, 32 and 64 bits: 964multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 965 string OpcodeStr, SDNode ShOp> { 966 // 64-bit vector types. 967 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4, 968 !strconcat(OpcodeStr, "8"), v8i8, ShOp>; 969 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4, 970 !strconcat(OpcodeStr, "16"), v4i16, ShOp>; 971 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4, 972 !strconcat(OpcodeStr, "32"), v2i32, ShOp>; 973 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4, 974 !strconcat(OpcodeStr, "64"), v1i64, ShOp>; 975 976 // 128-bit vector types. 977 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4, 978 !strconcat(OpcodeStr, "8"), v16i8, ShOp>; 979 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4, 980 !strconcat(OpcodeStr, "16"), v8i16, ShOp>; 981 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4, 982 !strconcat(OpcodeStr, "32"), v4i32, ShOp>; 983 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4, 984 !strconcat(OpcodeStr, "64"), v2i64, ShOp>; 985} 986 987 988// Neon Shift-Insert vector operations, 989// element sizes of 8, 16, 32 and 64 bits: 990multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 991 string OpcodeStr, SDNode ShOp> { 992 // 64-bit vector types. 993 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4, 994 !strconcat(OpcodeStr, "8"), v8i8, ShOp>; 995 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4, 996 !strconcat(OpcodeStr, "16"), v4i16, ShOp>; 997 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4, 998 !strconcat(OpcodeStr, "32"), v2i32, ShOp>; 999 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4, 1000 !strconcat(OpcodeStr, "64"), v1i64, ShOp>; 1001 1002 // 128-bit vector types. 1003 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4, 1004 !strconcat(OpcodeStr, "8"), v16i8, ShOp>; 1005 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4, 1006 !strconcat(OpcodeStr, "16"), v8i16, ShOp>; 1007 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4, 1008 !strconcat(OpcodeStr, "32"), v4i32, ShOp>; 1009 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4, 1010 !strconcat(OpcodeStr, "64"), v2i64, ShOp>; 1011} 1012 1013//===----------------------------------------------------------------------===// 1014// Instruction Definitions. 1015//===----------------------------------------------------------------------===// 1016 1017// Vector Add Operations. 1018 1019// VADD : Vector Add (integer and floating-point) 1020defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>; 1021def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>; 1022def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>; 1023// VADDL : Vector Add Long (Q = D + D) 1024defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>; 1025defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>; 1026// VADDW : Vector Add Wide (Q = Q + D) 1027defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>; 1028defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>; 1029// VHADD : Vector Halving Add 1030defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>; 1031defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>; 1032// VRHADD : Vector Rounding Halving Add 1033defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>; 1034defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>; 1035// VQADD : Vector Saturating Add 1036defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>; 1037defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>; 1038// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q) 1039defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>; 1040// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q) 1041defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>; 1042 1043// Vector Multiply Operations. 1044 1045// VMUL : Vector Multiply (integer, polynomial and floating-point) 1046defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>; 1047def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8, 1048 int_arm_neon_vmulp, 1>; 1049def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8, 1050 int_arm_neon_vmulp, 1>; 1051def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>; 1052def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>; 1053// VQDMULH : Vector Saturating Doubling Multiply Returning High Half 1054defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>; 1055// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half 1056defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>; 1057// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D) 1058defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>; 1059defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>; 1060def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8, 1061 int_arm_neon_vmullp, 1>; 1062// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D) 1063defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>; 1064 1065// Vector Multiply-Accumulate and Multiply-Subtract Operations. 1066 1067// VMLA : Vector Multiply Accumulate (integer and floating-point) 1068defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>; 1069def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>; 1070def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>; 1071// VMLAL : Vector Multiply Accumulate Long (Q += D * D) 1072defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>; 1073defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>; 1074// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D) 1075defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>; 1076// VMLS : Vector Multiply Subtract (integer and floating-point) 1077defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>; 1078def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>; 1079def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>; 1080// VMLSL : Vector Multiply Subtract Long (Q -= D * D) 1081defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>; 1082defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>; 1083// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D) 1084defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>; 1085 1086// Vector Subtract Operations. 1087 1088// VSUB : Vector Subtract (integer and floating-point) 1089defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>; 1090def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>; 1091def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>; 1092// VSUBL : Vector Subtract Long (Q = D - D) 1093defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>; 1094defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>; 1095// VSUBW : Vector Subtract Wide (Q = Q - D) 1096defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>; 1097defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>; 1098// VHSUB : Vector Halving Subtract 1099defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>; 1100defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>; 1101// VQSUB : Vector Saturing Subtract 1102defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>; 1103defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>; 1104// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q) 1105defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>; 1106// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q) 1107defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>; 1108 1109// Vector Comparisons. 1110 1111// VCEQ : Vector Compare Equal 1112defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>; 1113def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>; 1114def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>; 1115// VCGE : Vector Compare Greater Than or Equal 1116defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>; 1117defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>; 1118def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>; 1119def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>; 1120// VCGT : Vector Compare Greater Than 1121defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>; 1122defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>; 1123def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>; 1124def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>; 1125// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE) 1126def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32, 1127 int_arm_neon_vacged, 0>; 1128def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32, 1129 int_arm_neon_vacgeq, 0>; 1130// VACGT : Vector Absolute Compare Greater Than (aka VCAGT) 1131def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32, 1132 int_arm_neon_vacgtd, 0>; 1133def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32, 1134 int_arm_neon_vacgtq, 0>; 1135// VTST : Vector Test Bits 1136defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>; 1137 1138// Vector Bitwise Operations. 1139 1140// VAND : Vector Bitwise AND 1141def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>; 1142def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>; 1143 1144// VEOR : Vector Bitwise Exclusive OR 1145def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>; 1146def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>; 1147 1148// VORR : Vector Bitwise OR 1149def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>; 1150def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>; 1151 1152// VBIC : Vector Bitwise Bit Clear (AND NOT) 1153def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), 1154 (ins DPR:$src1, DPR:$src2), NoItinerary, 1155 "vbic\t$dst, $src1, $src2", "", 1156 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>; 1157def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), 1158 (ins QPR:$src1, QPR:$src2), NoItinerary, 1159 "vbic\t$dst, $src1, $src2", "", 1160 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>; 1161 1162// VORN : Vector Bitwise OR NOT 1163def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst), 1164 (ins DPR:$src1, DPR:$src2), NoItinerary, 1165 "vorn\t$dst, $src1, $src2", "", 1166 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>; 1167def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst), 1168 (ins QPR:$src1, QPR:$src2), NoItinerary, 1169 "vorn\t$dst, $src1, $src2", "", 1170 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>; 1171 1172// VMVN : Vector Bitwise NOT 1173def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0, 1174 (outs DPR:$dst), (ins DPR:$src), NoItinerary, 1175 "vmvn\t$dst, $src", "", 1176 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>; 1177def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0, 1178 (outs QPR:$dst), (ins QPR:$src), NoItinerary, 1179 "vmvn\t$dst, $src", "", 1180 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>; 1181def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>; 1182def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>; 1183 1184// VBSL : Vector Bitwise Select 1185def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), 1186 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary, 1187 "vbsl\t$dst, $src2, $src3", "$src1 = $dst", 1188 [(set DPR:$dst, 1189 (v2i32 (or (and DPR:$src2, DPR:$src1), 1190 (and DPR:$src3, (vnot DPR:$src1)))))]>; 1191def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), 1192 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary, 1193 "vbsl\t$dst, $src2, $src3", "$src1 = $dst", 1194 [(set QPR:$dst, 1195 (v4i32 (or (and QPR:$src2, QPR:$src1), 1196 (and QPR:$src3, (vnot QPR:$src1)))))]>; 1197 1198// VBIF : Vector Bitwise Insert if False 1199// like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst", 1200// VBIT : Vector Bitwise Insert if True 1201// like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst", 1202// These are not yet implemented. The TwoAddress pass will not go looking 1203// for equivalent operations with different register constraints; it just 1204// inserts copies. 1205 1206// Vector Absolute Differences. 1207 1208// VABD : Vector Absolute Difference 1209defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>; 1210defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>; 1211def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32, 1212 int_arm_neon_vabdf, 0>; 1213def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32, 1214 int_arm_neon_vabdf, 0>; 1215 1216// VABDL : Vector Absolute Difference Long (Q = | D - D |) 1217defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>; 1218defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>; 1219 1220// VABA : Vector Absolute Difference and Accumulate 1221defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>; 1222defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>; 1223 1224// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |) 1225defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>; 1226defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>; 1227 1228// Vector Maximum and Minimum. 1229 1230// VMAX : Vector Maximum 1231defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>; 1232defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>; 1233def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32, 1234 int_arm_neon_vmaxf, 1>; 1235def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32, 1236 int_arm_neon_vmaxf, 1>; 1237 1238// VMIN : Vector Minimum 1239defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>; 1240defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>; 1241def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32, 1242 int_arm_neon_vminf, 1>; 1243def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32, 1244 int_arm_neon_vminf, 1>; 1245 1246// Vector Pairwise Operations. 1247 1248// VPADD : Vector Pairwise Add 1249def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8, 1250 int_arm_neon_vpaddi, 0>; 1251def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16, 1252 int_arm_neon_vpaddi, 0>; 1253def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32, 1254 int_arm_neon_vpaddi, 0>; 1255def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32, 1256 int_arm_neon_vpaddf, 0>; 1257 1258// VPADDL : Vector Pairwise Add Long 1259defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s", 1260 int_arm_neon_vpaddls>; 1261defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u", 1262 int_arm_neon_vpaddlu>; 1263 1264// VPADAL : Vector Pairwise Add and Accumulate Long 1265defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s", 1266 int_arm_neon_vpadals>; 1267defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u", 1268 int_arm_neon_vpadalu>; 1269 1270// VPMAX : Vector Pairwise Maximum 1271def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8, 1272 int_arm_neon_vpmaxs, 0>; 1273def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16, 1274 int_arm_neon_vpmaxs, 0>; 1275def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32, 1276 int_arm_neon_vpmaxs, 0>; 1277def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8, 1278 int_arm_neon_vpmaxu, 0>; 1279def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16, 1280 int_arm_neon_vpmaxu, 0>; 1281def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32, 1282 int_arm_neon_vpmaxu, 0>; 1283def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32, 1284 int_arm_neon_vpmaxf, 0>; 1285 1286// VPMIN : Vector Pairwise Minimum 1287def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8, 1288 int_arm_neon_vpmins, 0>; 1289def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16, 1290 int_arm_neon_vpmins, 0>; 1291def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32, 1292 int_arm_neon_vpmins, 0>; 1293def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8, 1294 int_arm_neon_vpminu, 0>; 1295def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16, 1296 int_arm_neon_vpminu, 0>; 1297def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32, 1298 int_arm_neon_vpminu, 0>; 1299def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32, 1300 int_arm_neon_vpminf, 0>; 1301 1302// Vector Reciprocal and Reciprocal Square Root Estimate and Step. 1303 1304// VRECPE : Vector Reciprocal Estimate 1305def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32", 1306 v2i32, v2i32, int_arm_neon_vrecpe>; 1307def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32", 1308 v4i32, v4i32, int_arm_neon_vrecpe>; 1309def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32", 1310 v2f32, v2f32, int_arm_neon_vrecpef>; 1311def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32", 1312 v4f32, v4f32, int_arm_neon_vrecpef>; 1313 1314// VRECPS : Vector Reciprocal Step 1315def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32, 1316 int_arm_neon_vrecps, 1>; 1317def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32, 1318 int_arm_neon_vrecps, 1>; 1319 1320// VRSQRTE : Vector Reciprocal Square Root Estimate 1321def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32", 1322 v2i32, v2i32, int_arm_neon_vrsqrte>; 1323def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32", 1324 v4i32, v4i32, int_arm_neon_vrsqrte>; 1325def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32", 1326 v2f32, v2f32, int_arm_neon_vrsqrtef>; 1327def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32", 1328 v4f32, v4f32, int_arm_neon_vrsqrtef>; 1329 1330// VRSQRTS : Vector Reciprocal Square Root Step 1331def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32, 1332 int_arm_neon_vrsqrts, 1>; 1333def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32, 1334 int_arm_neon_vrsqrts, 1>; 1335 1336// Vector Shifts. 1337 1338// VSHL : Vector Shift 1339defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>; 1340defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>; 1341// VSHL : Vector Shift Left (Immediate) 1342defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>; 1343// VSHR : Vector Shift Right (Immediate) 1344defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>; 1345defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>; 1346 1347// VSHLL : Vector Shift Left Long 1348def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8", 1349 v8i16, v8i8, NEONvshlls>; 1350def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16", 1351 v4i32, v4i16, NEONvshlls>; 1352def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32", 1353 v2i64, v2i32, NEONvshlls>; 1354def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8", 1355 v8i16, v8i8, NEONvshllu>; 1356def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16", 1357 v4i32, v4i16, NEONvshllu>; 1358def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32", 1359 v2i64, v2i32, NEONvshllu>; 1360 1361// VSHLL : Vector Shift Left Long (with maximum shift count) 1362def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8", 1363 v8i16, v8i8, NEONvshlli>; 1364def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16", 1365 v4i32, v4i16, NEONvshlli>; 1366def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32", 1367 v2i64, v2i32, NEONvshlli>; 1368 1369// VSHRN : Vector Shift Right and Narrow 1370def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16", 1371 v8i8, v8i16, NEONvshrn>; 1372def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32", 1373 v4i16, v4i32, NEONvshrn>; 1374def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64", 1375 v2i32, v2i64, NEONvshrn>; 1376 1377// VRSHL : Vector Rounding Shift 1378defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>; 1379defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>; 1380// VRSHR : Vector Rounding Shift Right 1381defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>; 1382defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>; 1383 1384// VRSHRN : Vector Rounding Shift Right and Narrow 1385def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16", 1386 v8i8, v8i16, NEONvrshrn>; 1387def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32", 1388 v4i16, v4i32, NEONvrshrn>; 1389def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64", 1390 v2i32, v2i64, NEONvrshrn>; 1391 1392// VQSHL : Vector Saturating Shift 1393defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>; 1394defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>; 1395// VQSHL : Vector Saturating Shift Left (Immediate) 1396defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>; 1397defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>; 1398// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned) 1399defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>; 1400 1401// VQSHRN : Vector Saturating Shift Right and Narrow 1402def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16", 1403 v8i8, v8i16, NEONvqshrns>; 1404def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32", 1405 v4i16, v4i32, NEONvqshrns>; 1406def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64", 1407 v2i32, v2i64, NEONvqshrns>; 1408def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16", 1409 v8i8, v8i16, NEONvqshrnu>; 1410def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32", 1411 v4i16, v4i32, NEONvqshrnu>; 1412def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64", 1413 v2i32, v2i64, NEONvqshrnu>; 1414 1415// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned) 1416def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16", 1417 v8i8, v8i16, NEONvqshrnsu>; 1418def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32", 1419 v4i16, v4i32, NEONvqshrnsu>; 1420def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64", 1421 v2i32, v2i64, NEONvqshrnsu>; 1422 1423// VQRSHL : Vector Saturating Rounding Shift 1424defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s", 1425 int_arm_neon_vqrshifts, 0>; 1426defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u", 1427 int_arm_neon_vqrshiftu, 0>; 1428 1429// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow 1430def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16", 1431 v8i8, v8i16, NEONvqrshrns>; 1432def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32", 1433 v4i16, v4i32, NEONvqrshrns>; 1434def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64", 1435 v2i32, v2i64, NEONvqrshrns>; 1436def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16", 1437 v8i8, v8i16, NEONvqrshrnu>; 1438def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32", 1439 v4i16, v4i32, NEONvqrshrnu>; 1440def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64", 1441 v2i32, v2i64, NEONvqrshrnu>; 1442 1443// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned) 1444def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16", 1445 v8i8, v8i16, NEONvqrshrnsu>; 1446def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32", 1447 v4i16, v4i32, NEONvqrshrnsu>; 1448def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64", 1449 v2i32, v2i64, NEONvqrshrnsu>; 1450 1451// VSRA : Vector Shift Right and Accumulate 1452defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>; 1453defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>; 1454// VRSRA : Vector Rounding Shift Right and Accumulate 1455defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>; 1456defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>; 1457 1458// VSLI : Vector Shift Left and Insert 1459defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>; 1460// VSRI : Vector Shift Right and Insert 1461defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>; 1462 1463// Vector Absolute and Saturating Absolute. 1464 1465// VABS : Vector Absolute Value 1466defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s", 1467 int_arm_neon_vabs>; 1468def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32", 1469 v2f32, v2f32, int_arm_neon_vabsf>; 1470def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32", 1471 v4f32, v4f32, int_arm_neon_vabsf>; 1472 1473// VQABS : Vector Saturating Absolute Value 1474defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s", 1475 int_arm_neon_vqabs>; 1476 1477// Vector Negate. 1478 1479def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>; 1480def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>; 1481 1482class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty> 1483 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src), 1484 NoItinerary, 1485 !strconcat(OpcodeStr, "\t$dst, $src"), "", 1486 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>; 1487class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty> 1488 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src), 1489 NoItinerary, 1490 !strconcat(OpcodeStr, "\t$dst, $src"), "", 1491 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>; 1492 1493// VNEG : Vector Negate 1494def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>; 1495def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>; 1496def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>; 1497def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>; 1498def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>; 1499def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>; 1500 1501// VNEG : Vector Negate (floating-point) 1502def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, 1503 (outs DPR:$dst), (ins DPR:$src), NoItinerary, 1504 "vneg.f32\t$dst, $src", "", 1505 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>; 1506def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0, 1507 (outs QPR:$dst), (ins QPR:$src), NoItinerary, 1508 "vneg.f32\t$dst, $src", "", 1509 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>; 1510 1511def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>; 1512def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>; 1513def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>; 1514def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>; 1515def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>; 1516def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>; 1517 1518// VQNEG : Vector Saturating Negate 1519defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s", 1520 int_arm_neon_vqneg>; 1521 1522// Vector Bit Counting Operations. 1523 1524// VCLS : Vector Count Leading Sign Bits 1525defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s", 1526 int_arm_neon_vcls>; 1527// VCLZ : Vector Count Leading Zeros 1528defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i", 1529 int_arm_neon_vclz>; 1530// VCNT : Vector Count One Bits 1531def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8", 1532 v8i8, v8i8, int_arm_neon_vcnt>; 1533def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8", 1534 v16i8, v16i8, int_arm_neon_vcnt>; 1535 1536// Vector Move Operations. 1537 1538// VMOV : Vector Move (Register) 1539 1540def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src), 1541 NoItinerary, "vmov\t$dst, $src", "", []>; 1542def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src), 1543 NoItinerary, "vmov\t$dst, $src", "", []>; 1544 1545// VMOV : Vector Move (Immediate) 1546 1547// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm. 1548def VMOV_get_imm8 : SDNodeXForm<build_vector, [{ 1549 return ARM::getVMOVImm(N, 1, *CurDAG); 1550}]>; 1551def vmovImm8 : PatLeaf<(build_vector), [{ 1552 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0; 1553}], VMOV_get_imm8>; 1554 1555// VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm. 1556def VMOV_get_imm16 : SDNodeXForm<build_vector, [{ 1557 return ARM::getVMOVImm(N, 2, *CurDAG); 1558}]>; 1559def vmovImm16 : PatLeaf<(build_vector), [{ 1560 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0; 1561}], VMOV_get_imm16>; 1562 1563// VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm. 1564def VMOV_get_imm32 : SDNodeXForm<build_vector, [{ 1565 return ARM::getVMOVImm(N, 4, *CurDAG); 1566}]>; 1567def vmovImm32 : PatLeaf<(build_vector), [{ 1568 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0; 1569}], VMOV_get_imm32>; 1570 1571// VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm. 1572def VMOV_get_imm64 : SDNodeXForm<build_vector, [{ 1573 return ARM::getVMOVImm(N, 8, *CurDAG); 1574}]>; 1575def vmovImm64 : PatLeaf<(build_vector), [{ 1576 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0; 1577}], VMOV_get_imm64>; 1578 1579// Note: Some of the cmode bits in the following VMOV instructions need to 1580// be encoded based on the immed values. 1581 1582def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst), 1583 (ins i8imm:$SIMM), NoItinerary, 1584 "vmov.i8\t$dst, $SIMM", "", 1585 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>; 1586def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst), 1587 (ins i8imm:$SIMM), NoItinerary, 1588 "vmov.i8\t$dst, $SIMM", "", 1589 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>; 1590 1591def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst), 1592 (ins i16imm:$SIMM), NoItinerary, 1593 "vmov.i16\t$dst, $SIMM", "", 1594 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>; 1595def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst), 1596 (ins i16imm:$SIMM), NoItinerary, 1597 "vmov.i16\t$dst, $SIMM", "", 1598 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>; 1599 1600def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst), 1601 (ins i32imm:$SIMM), NoItinerary, 1602 "vmov.i32\t$dst, $SIMM", "", 1603 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>; 1604def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst), 1605 (ins i32imm:$SIMM), NoItinerary, 1606 "vmov.i32\t$dst, $SIMM", "", 1607 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>; 1608 1609def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst), 1610 (ins i64imm:$SIMM), NoItinerary, 1611 "vmov.i64\t$dst, $SIMM", "", 1612 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>; 1613def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst), 1614 (ins i64imm:$SIMM), NoItinerary, 1615 "vmov.i64\t$dst, $SIMM", "", 1616 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>; 1617 1618// VMOV : Vector Get Lane (move scalar to ARM core register) 1619 1620def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00, 1621 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane), 1622 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]", 1623 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src), 1624 imm:$lane))]>; 1625def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01, 1626 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane), 1627 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]", 1628 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src), 1629 imm:$lane))]>; 1630def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00, 1631 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane), 1632 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]", 1633 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src), 1634 imm:$lane))]>; 1635def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01, 1636 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane), 1637 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]", 1638 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src), 1639 imm:$lane))]>; 1640def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00, 1641 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane), 1642 NoItinerary, "vmov", ".32\t$dst, $src[$lane]", 1643 [(set GPR:$dst, (extractelt (v2i32 DPR:$src), 1644 imm:$lane))]>; 1645// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td 1646def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane), 1647 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src, 1648 (DSubReg_i8_reg imm:$lane))), 1649 (SubReg_i8_lane imm:$lane))>; 1650def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane), 1651 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src, 1652 (DSubReg_i16_reg imm:$lane))), 1653 (SubReg_i16_lane imm:$lane))>; 1654def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane), 1655 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src, 1656 (DSubReg_i8_reg imm:$lane))), 1657 (SubReg_i8_lane imm:$lane))>; 1658def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane), 1659 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src, 1660 (DSubReg_i16_reg imm:$lane))), 1661 (SubReg_i16_lane imm:$lane))>; 1662def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane), 1663 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src, 1664 (DSubReg_i32_reg imm:$lane))), 1665 (SubReg_i32_lane imm:$lane))>; 1666def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2), 1667 (EXTRACT_SUBREG QPR:$src1, (SSubReg_f32_reg imm:$src2))>; 1668//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2), 1669// (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>; 1670def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2), 1671 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>; 1672 1673 1674// VMOV : Vector Set Lane (move ARM core register to scalar) 1675 1676let Constraints = "$src1 = $dst" in { 1677def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst), 1678 (ins DPR:$src1, GPR:$src2, lane_cst:$lane), 1679 NoItinerary, "vmov", ".8\t$dst[$lane], $src2", 1680 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1), 1681 GPR:$src2, imm:$lane))]>; 1682def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst), 1683 (ins DPR:$src1, GPR:$src2, lane_cst:$lane), 1684 NoItinerary, "vmov", ".16\t$dst[$lane], $src2", 1685 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1), 1686 GPR:$src2, imm:$lane))]>; 1687def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst), 1688 (ins DPR:$src1, GPR:$src2, lane_cst:$lane), 1689 NoItinerary, "vmov", ".32\t$dst[$lane], $src2", 1690 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1), 1691 GPR:$src2, imm:$lane))]>; 1692} 1693def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane), 1694 (v16i8 (INSERT_SUBREG QPR:$src1, 1695 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1, 1696 (DSubReg_i8_reg imm:$lane))), 1697 GPR:$src2, (SubReg_i8_lane imm:$lane)), 1698 (DSubReg_i8_reg imm:$lane)))>; 1699def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane), 1700 (v8i16 (INSERT_SUBREG QPR:$src1, 1701 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1, 1702 (DSubReg_i16_reg imm:$lane))), 1703 GPR:$src2, (SubReg_i16_lane imm:$lane)), 1704 (DSubReg_i16_reg imm:$lane)))>; 1705def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane), 1706 (v4i32 (INSERT_SUBREG QPR:$src1, 1707 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1, 1708 (DSubReg_i32_reg imm:$lane))), 1709 GPR:$src2, (SubReg_i32_lane imm:$lane)), 1710 (DSubReg_i32_reg imm:$lane)))>; 1711 1712def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)), 1713 (INSERT_SUBREG QPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>; 1714 1715//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), 1716// (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>; 1717def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), 1718 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>; 1719 1720// VDUP : Vector Duplicate (from ARM core register to all elements) 1721 1722def splat_lo : PatFrag<(ops node:$lhs, node:$rhs), 1723 (vector_shuffle node:$lhs, node:$rhs), [{ 1724 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1725 return SVOp->isSplat() && SVOp->getSplatIndex() == 0; 1726}]>; 1727 1728class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty> 1729 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src), 1730 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"), 1731 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>; 1732class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty> 1733 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src), 1734 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"), 1735 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>; 1736 1737def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>; 1738def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>; 1739def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>; 1740def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>; 1741def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>; 1742def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>; 1743 1744def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src), 1745 NoItinerary, "vdup", ".32\t$dst, $src", 1746 [(set DPR:$dst, (v2f32 (splat_lo 1747 (scalar_to_vector 1748 (f32 (bitconvert GPR:$src))), 1749 undef)))]>; 1750def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src), 1751 NoItinerary, "vdup", ".32\t$dst, $src", 1752 [(set QPR:$dst, (v4f32 (splat_lo 1753 (scalar_to_vector 1754 (f32 (bitconvert GPR:$src))), 1755 undef)))]>; 1756 1757// VDUP : Vector Duplicate Lane (from scalar to all elements) 1758 1759def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{ 1760 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1761 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32); 1762}]>; 1763 1764def splat_lane : PatFrag<(ops node:$lhs, node:$rhs), 1765 (vector_shuffle node:$lhs, node:$rhs), [{ 1766 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1767 return SVOp->isSplat(); 1768}], SHUFFLE_get_splat_lane>; 1769 1770class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty> 1771 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0, 1772 (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary, 1773 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", 1774 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>; 1775 1776// vector_shuffle requires that the source and destination types match, so 1777// VDUP to a 128-bit result uses a target-specific VDUPLANEQ node. 1778class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, 1779 ValueType ResTy, ValueType OpTy> 1780 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0, 1781 (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary, 1782 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", 1783 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>; 1784 1785def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>; 1786def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>; 1787def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>; 1788def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>; 1789def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>; 1790def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>; 1791def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>; 1792def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>; 1793 1794def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0, 1795 (outs DPR:$dst), (ins SPR:$src), 1796 NoItinerary, "vdup.32\t$dst, ${src:lane}", "", 1797 [(set DPR:$dst, (v2f32 (splat_lo 1798 (scalar_to_vector SPR:$src), 1799 undef)))]>; 1800 1801def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0, 1802 (outs QPR:$dst), (ins SPR:$src), 1803 NoItinerary, "vdup.32\t$dst, ${src:lane}", "", 1804 [(set QPR:$dst, (v4f32 (splat_lo 1805 (scalar_to_vector SPR:$src), 1806 undef)))]>; 1807 1808// VMOVN : Vector Narrowing Move 1809defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i", 1810 int_arm_neon_vmovn>; 1811// VQMOVN : Vector Saturating Narrowing Move 1812defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s", 1813 int_arm_neon_vqmovns>; 1814defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u", 1815 int_arm_neon_vqmovnu>; 1816defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s", 1817 int_arm_neon_vqmovnsu>; 1818// VMOVL : Vector Lengthening Move 1819defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>; 1820defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>; 1821 1822// Vector Conversions. 1823 1824// VCVT : Vector Convert Between Floating-Point and Integers 1825def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32", 1826 v2i32, v2f32, fp_to_sint>; 1827def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32", 1828 v2i32, v2f32, fp_to_uint>; 1829def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32", 1830 v2f32, v2i32, sint_to_fp>; 1831def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32", 1832 v2f32, v2i32, uint_to_fp>; 1833 1834def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32", 1835 v4i32, v4f32, fp_to_sint>; 1836def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32", 1837 v4i32, v4f32, fp_to_uint>; 1838def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32", 1839 v4f32, v4i32, sint_to_fp>; 1840def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32", 1841 v4f32, v4i32, uint_to_fp>; 1842 1843// VCVT : Vector Convert Between Floating-Point and Fixed-Point. 1844// Note: Some of the opcode bits in the following VCVT instructions need to 1845// be encoded based on the immed values. 1846def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32", 1847 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>; 1848def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32", 1849 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>; 1850def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32", 1851 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>; 1852def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32", 1853 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>; 1854 1855def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32", 1856 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>; 1857def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32", 1858 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>; 1859def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32", 1860 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>; 1861def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32", 1862 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>; 1863 1864// VREV : Vector Reverse 1865 1866def vrev64_shuffle : PatFrag<(ops node:$in), 1867 (vector_shuffle node:$in, undef), [{ 1868 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1869 return ARM::isVREVMask(SVOp, 64); 1870}]>; 1871 1872def vrev32_shuffle : PatFrag<(ops node:$in), 1873 (vector_shuffle node:$in, undef), [{ 1874 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1875 return ARM::isVREVMask(SVOp, 32); 1876}]>; 1877 1878def vrev16_shuffle : PatFrag<(ops node:$in), 1879 (vector_shuffle node:$in, undef), [{ 1880 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1881 return ARM::isVREVMask(SVOp, 16); 1882}]>; 1883 1884// VREV64 : Vector Reverse elements within 64-bit doublewords 1885 1886class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1887 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst), 1888 (ins DPR:$src), NoItinerary, 1889 !strconcat(OpcodeStr, "\t$dst, $src"), "", 1890 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>; 1891class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1892 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst), 1893 (ins QPR:$src), NoItinerary, 1894 !strconcat(OpcodeStr, "\t$dst, $src"), "", 1895 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>; 1896 1897def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>; 1898def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>; 1899def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>; 1900def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>; 1901 1902def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>; 1903def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>; 1904def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>; 1905def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>; 1906 1907// VREV32 : Vector Reverse elements within 32-bit words 1908 1909class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1910 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst), 1911 (ins DPR:$src), NoItinerary, 1912 !strconcat(OpcodeStr, "\t$dst, $src"), "", 1913 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>; 1914class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1915 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst), 1916 (ins QPR:$src), NoItinerary, 1917 !strconcat(OpcodeStr, "\t$dst, $src"), "", 1918 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>; 1919 1920def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>; 1921def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>; 1922 1923def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>; 1924def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>; 1925 1926// VREV16 : Vector Reverse elements within 16-bit halfwords 1927 1928class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1929 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst), 1930 (ins DPR:$src), NoItinerary, 1931 !strconcat(OpcodeStr, "\t$dst, $src"), "", 1932 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>; 1933class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1934 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst), 1935 (ins QPR:$src), NoItinerary, 1936 !strconcat(OpcodeStr, "\t$dst, $src"), "", 1937 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>; 1938 1939def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>; 1940def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>; 1941 1942// VTRN : Vector Transpose 1943 1944def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">; 1945def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">; 1946def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">; 1947 1948def VTRNq8 : N2VQShuffle<0b00, 0b00001, "vtrn.8">; 1949def VTRNq16 : N2VQShuffle<0b01, 0b00001, "vtrn.16">; 1950def VTRNq32 : N2VQShuffle<0b10, 0b00001, "vtrn.32">; 1951 1952// VUZP : Vector Unzip (Deinterleave) 1953 1954def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">; 1955def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">; 1956def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">; 1957 1958def VUZPq8 : N2VQShuffle<0b00, 0b00010, "vuzp.8">; 1959def VUZPq16 : N2VQShuffle<0b01, 0b00010, "vuzp.16">; 1960def VUZPq32 : N2VQShuffle<0b10, 0b00010, "vuzp.32">; 1961 1962// VZIP : Vector Zip (Interleave) 1963 1964def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">; 1965def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">; 1966def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">; 1967 1968def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">; 1969def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">; 1970def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">; 1971 1972//===----------------------------------------------------------------------===// 1973// NEON instructions for single-precision FP math 1974//===----------------------------------------------------------------------===// 1975 1976// These need separate instructions because they must use DPR_VFP2 register 1977// class which have SPR sub-registers. 1978 1979// Vector Add Operations used for single-precision FP 1980let neverHasSideEffects = 1 in 1981def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>; 1982def : N3VDsPat<fadd, VADDfd_sfp>; 1983 1984// Vector Multiply Operations used for single-precision FP 1985let neverHasSideEffects = 1 in 1986def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>; 1987def : N3VDsPat<fmul, VMULfd_sfp>; 1988 1989// Vector Multiply-Accumulate/Subtract used for single-precision FP 1990let neverHasSideEffects = 1 in 1991def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>; 1992def : N3VDMulOpsPat<fmul, fadd, VMLAfd>; 1993 1994let neverHasSideEffects = 1 in 1995def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>; 1996def : N3VDMulOpsPat<fmul, fsub, VMLSfd>; 1997 1998// Vector Sub Operations used for single-precision FP 1999let neverHasSideEffects = 1 in 2000def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>; 2001def : N3VDsPat<fsub, VSUBfd_sfp>; 2002 2003// Vector Absolute for single-precision FP 2004let neverHasSideEffects = 1 in 2005def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32", 2006 v2f32, v2f32, int_arm_neon_vabsf>; 2007def : N2VDIntsPat<fabs, VABSfd_sfp>; 2008 2009// Vector Negate for single-precision FP 2010 2011let neverHasSideEffects = 1 in 2012def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, 2013 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary, 2014 "vneg.f32\t$dst, $src", "", []>; 2015def : N2VDIntsPat<fneg, VNEGf32d_sfp>; 2016 2017//===----------------------------------------------------------------------===// 2018// Non-Instruction Patterns 2019//===----------------------------------------------------------------------===// 2020 2021// bit_convert 2022def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>; 2023def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>; 2024def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>; 2025def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>; 2026def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>; 2027def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>; 2028def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>; 2029def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>; 2030def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>; 2031def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>; 2032def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>; 2033def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>; 2034def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>; 2035def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>; 2036def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>; 2037def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>; 2038def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>; 2039def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>; 2040def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>; 2041def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>; 2042def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>; 2043def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>; 2044def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>; 2045def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>; 2046def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>; 2047def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>; 2048def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>; 2049def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>; 2050def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>; 2051def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>; 2052 2053def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>; 2054def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>; 2055def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>; 2056def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>; 2057def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>; 2058def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>; 2059def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>; 2060def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>; 2061def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>; 2062def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>; 2063def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>; 2064def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>; 2065def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>; 2066def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>; 2067def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>; 2068def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>; 2069def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>; 2070def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>; 2071def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>; 2072def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>; 2073def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>; 2074def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>; 2075def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>; 2076def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>; 2077def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>; 2078def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>; 2079def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>; 2080def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>; 2081def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>; 2082def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>; 2083