ARMInstrThumb.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22def imm_sr_XFORM: SDNodeXForm<imm, [{ 23 unsigned Imm = N->getZExtValue(); 24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32); 25}]>; 26def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 27def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 28 uint64_t Imm = N->getZExtValue(); 29 return Imm > 0 && Imm <= 32; 30}], imm_sr_XFORM> { 31 let PrintMethod = "printThumbSRImm"; 32 let ParserMatchClass = ThumbSRImmAsmOperand; 33} 34 35def imm_comp_XFORM : SDNodeXForm<imm, [{ 36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 37}]>; 38 39def imm0_7_neg : PatLeaf<(i32 imm), [{ 40 return (uint32_t)-N->getZExtValue() < 8; 41}], imm_neg_XFORM>; 42 43def imm0_255_comp : PatLeaf<(i32 imm), [{ 44 return ~((uint32_t)N->getZExtValue()) < 256; 45}]>; 46 47def imm8_255 : ImmLeaf<i32, [{ 48 return Imm >= 8 && Imm < 256; 49}]>; 50def imm8_255_neg : PatLeaf<(i32 imm), [{ 51 unsigned Val = -N->getZExtValue(); 52 return Val >= 8 && Val < 256; 53}], imm_neg_XFORM>; 54 55// Break imm's up into two pieces: an immediate + a left shift. This uses 56// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 57// to get the val/shift pieces. 58def thumb_immshifted : PatLeaf<(imm), [{ 59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 60}]>; 61 62def thumb_immshifted_val : SDNodeXForm<imm, [{ 63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 64 return CurDAG->getTargetConstant(V, MVT::i32); 65}]>; 66 67def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 69 return CurDAG->getTargetConstant(V, MVT::i32); 70}]>; 71 72// Scaled 4 immediate. 73def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 74def t_imm0_1020s4 : Operand<i32> { 75 let PrintMethod = "printThumbS4ImmOperand"; 76 let ParserMatchClass = t_imm0_1020s4_asmoperand; 77 let OperandType = "OPERAND_IMMEDIATE"; 78} 79 80def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 81def t_imm0_508s4 : Operand<i32> { 82 let PrintMethod = "printThumbS4ImmOperand"; 83 let ParserMatchClass = t_imm0_508s4_asmoperand; 84 let OperandType = "OPERAND_IMMEDIATE"; 85} 86// Alias use only, so no printer is necessary. 87def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 88def t_imm0_508s4_neg : Operand<i32> { 89 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 90 let OperandType = "OPERAND_IMMEDIATE"; 91} 92 93// Define Thumb specific addressing modes. 94 95// unsigned 8-bit, 2-scaled memory offset 96class OperandUnsignedOffset_b8s2 : AsmOperandClass { 97 let Name = "UnsignedOffset_b8s2"; 98 let PredicateMethod = "isUnsignedOffset<8, 2>"; 99} 100 101def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2; 102 103// thumb style PC relative operand. signed, 8 bits magnitude, 104// two bits shift. can be represented as either [pc, #imm], #imm, 105// or relocatable expression... 106def ThumbMemPC : AsmOperandClass { 107 let Name = "ThumbMemPC"; 108} 109 110let OperandType = "OPERAND_PCREL" in { 111def t_brtarget : Operand<OtherVT> { 112 let EncoderMethod = "getThumbBRTargetOpValue"; 113 let DecoderMethod = "DecodeThumbBROperand"; 114} 115 116// ADR instruction labels. 117def t_adrlabel : Operand<i32> { 118 let EncoderMethod = "getThumbAdrLabelOpValue"; 119 let PrintMethod = "printAdrLabelOperand<2>"; 120 let ParserMatchClass = UnsignedOffset_b8s2; 121} 122 123def t_bcctarget : Operand<i32> { 124 let EncoderMethod = "getThumbBCCTargetOpValue"; 125 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 126} 127 128def t_cbtarget : Operand<i32> { 129 let EncoderMethod = "getThumbCBTargetOpValue"; 130 let DecoderMethod = "DecodeThumbCmpBROperand"; 131} 132 133def t_bltarget : Operand<i32> { 134 let EncoderMethod = "getThumbBLTargetOpValue"; 135 let DecoderMethod = "DecodeThumbBLTargetOperand"; 136} 137 138def t_blxtarget : Operand<i32> { 139 let EncoderMethod = "getThumbBLXTargetOpValue"; 140 let DecoderMethod = "DecodeThumbBLXOffset"; 141} 142 143// t_addrmode_pc := <label> => pc + imm8 * 4 144// 145def t_addrmode_pc : Operand<i32> { 146 let EncoderMethod = "getAddrModePCOpValue"; 147 let DecoderMethod = "DecodeThumbAddrModePC"; 148 let PrintMethod = "printThumbLdrLabelOperand"; 149 let ParserMatchClass = ThumbMemPC; 150} 151} 152 153// t_addrmode_rr := reg + reg 154// 155def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 156def t_addrmode_rr : Operand<i32>, 157 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 158 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 159 let PrintMethod = "printThumbAddrModeRROperand"; 160 let DecoderMethod = "DecodeThumbAddrModeRR"; 161 let ParserMatchClass = t_addrmode_rr_asm_operand; 162 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 163} 164 165// t_addrmode_rrs := reg + reg 166// 167// We use separate scaled versions because the Select* functions need 168// to explicitly check for a matching constant and return false here so that 169// the reg+imm forms will match instead. This is a horrible way to do that, 170// as it forces tight coupling between the methods, but it's how selectiondag 171// currently works. 172def t_addrmode_rrs1 : Operand<i32>, 173 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 174 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 175 let PrintMethod = "printThumbAddrModeRROperand"; 176 let DecoderMethod = "DecodeThumbAddrModeRR"; 177 let ParserMatchClass = t_addrmode_rr_asm_operand; 178 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 179} 180def t_addrmode_rrs2 : Operand<i32>, 181 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 182 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 183 let DecoderMethod = "DecodeThumbAddrModeRR"; 184 let PrintMethod = "printThumbAddrModeRROperand"; 185 let ParserMatchClass = t_addrmode_rr_asm_operand; 186 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 187} 188def t_addrmode_rrs4 : Operand<i32>, 189 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 190 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 191 let DecoderMethod = "DecodeThumbAddrModeRR"; 192 let PrintMethod = "printThumbAddrModeRROperand"; 193 let ParserMatchClass = t_addrmode_rr_asm_operand; 194 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 195} 196 197// t_addrmode_is4 := reg + imm5 * 4 198// 199def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 200def t_addrmode_is4 : Operand<i32>, 201 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 202 let EncoderMethod = "getAddrModeISOpValue"; 203 let DecoderMethod = "DecodeThumbAddrModeIS"; 204 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 205 let ParserMatchClass = t_addrmode_is4_asm_operand; 206 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 207} 208 209// t_addrmode_is2 := reg + imm5 * 2 210// 211def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 212def t_addrmode_is2 : Operand<i32>, 213 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 214 let EncoderMethod = "getAddrModeISOpValue"; 215 let DecoderMethod = "DecodeThumbAddrModeIS"; 216 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 217 let ParserMatchClass = t_addrmode_is2_asm_operand; 218 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 219} 220 221// t_addrmode_is1 := reg + imm5 222// 223def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 224def t_addrmode_is1 : Operand<i32>, 225 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 226 let EncoderMethod = "getAddrModeISOpValue"; 227 let DecoderMethod = "DecodeThumbAddrModeIS"; 228 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 229 let ParserMatchClass = t_addrmode_is1_asm_operand; 230 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 231} 232 233// t_addrmode_sp := sp + imm8 * 4 234// 235// FIXME: This really shouldn't have an explicit SP operand at all. It should 236// be implicit, just like in the instruction encoding itself. 237def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 238def t_addrmode_sp : Operand<i32>, 239 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 240 let EncoderMethod = "getAddrModeThumbSPOpValue"; 241 let DecoderMethod = "DecodeThumbAddrModeSP"; 242 let PrintMethod = "printThumbAddrModeSPOperand"; 243 let ParserMatchClass = t_addrmode_sp_asm_operand; 244 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 245} 246 247//===----------------------------------------------------------------------===// 248// Miscellaneous Instructions. 249// 250 251// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 252// from removing one half of the matched pairs. That breaks PEI, which assumes 253// these will always be in pairs, and asserts if it finds otherwise. Better way? 254let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 255def tADJCALLSTACKUP : 256 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 257 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 258 Requires<[IsThumb, IsThumb1Only]>; 259 260def tADJCALLSTACKDOWN : 261 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 262 [(ARMcallseq_start imm:$amt)]>, 263 Requires<[IsThumb, IsThumb1Only]>; 264} 265 266class T1SystemEncoding<bits<8> opc> 267 : T1Encoding<0b101111> { 268 let Inst{9-8} = 0b11; 269 let Inst{7-0} = opc; 270} 271 272def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", 273 [(int_arm_hint imm0_15:$imm)]>, 274 T1SystemEncoding<0x00>, 275 Requires<[IsThumb, HasV6M]> { 276 bits<4> imm; 277 let Inst{7-4} = imm; 278} 279 280class tHintAlias<string Asm, dag Result> : tInstAlias<Asm, Result> { 281 let Predicates = [IsThumb, HasV6M]; 282} 283 284def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110 285def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410 286def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408 287def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409 288def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157 289def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> { 290 let Predicates = [IsThumb2, HasV8]; 291} 292 293// The imm operand $val can be used by a debugger to store more information 294// about the breakpoint. 295def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 296 []>, 297 T1Encoding<0b101111> { 298 let Inst{9-8} = 0b10; 299 // A8.6.22 300 bits<8> val; 301 let Inst{7-0} = val; 302} 303// default immediate for breakpoint mnemonic 304def : InstAlias<"bkpt", (tBKPT 0)>, Requires<[IsThumb]>; 305 306def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val", 307 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> { 308 let Inst{9-6} = 0b1010; 309 bits<6> val; 310 let Inst{5-0} = val; 311} 312 313def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 314 []>, T1Encoding<0b101101>, Deprecated<HasV8Ops> { 315 bits<1> end; 316 // A8.6.156 317 let Inst{9-5} = 0b10010; 318 let Inst{4} = 1; 319 let Inst{3} = end; 320 let Inst{2-0} = 0b000; 321} 322 323// Change Processor State is a system instruction -- for disassembly only. 324def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 325 NoItinerary, "cps$imod $iflags", []>, 326 T1Misc<0b0110011> { 327 // A8.6.38 & B6.1.1 328 bit imod; 329 bits<3> iflags; 330 331 let Inst{4} = imod; 332 let Inst{3} = 0; 333 let Inst{2-0} = iflags; 334 let DecoderMethod = "DecodeThumbCPS"; 335} 336 337// For both thumb1 and thumb2. 338let isNotDuplicable = 1, isCodeGenOnly = 1 in 339def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 340 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 341 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 342 // A8.6.6 343 bits<3> dst; 344 let Inst{6-3} = 0b1111; // Rm = pc 345 let Inst{2-0} = dst; 346} 347 348// ADD <Rd>, sp, #<imm8> 349// FIXME: This should not be marked as having side effects, and it should be 350// rematerializable. Clearing the side effect bit causes miscompilations, 351// probably because the instruction can be moved around. 352def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 353 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 354 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> { 355 // A6.2 & A8.6.8 356 bits<3> dst; 357 bits<8> imm; 358 let Inst{10-8} = dst; 359 let Inst{7-0} = imm; 360 let DecoderMethod = "DecodeThumbAddSpecialReg"; 361} 362 363// ADD sp, sp, #<imm7> 364def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 365 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 366 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> { 367 // A6.2.5 & A8.6.8 368 bits<7> imm; 369 let Inst{6-0} = imm; 370 let DecoderMethod = "DecodeThumbAddSPImm"; 371} 372 373// SUB sp, sp, #<imm7> 374// FIXME: The encoding and the ASM string don't match up. 375def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 376 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 377 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> { 378 // A6.2.5 & A8.6.214 379 bits<7> imm; 380 let Inst{6-0} = imm; 381 let DecoderMethod = "DecodeThumbAddSPImm"; 382} 383 384def : tInstAlias<"add${p} sp, $imm", 385 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 386def : tInstAlias<"add${p} sp, sp, $imm", 387 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 388 389// Can optionally specify SP as a three operand instruction. 390def : tInstAlias<"add${p} sp, sp, $imm", 391 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 392def : tInstAlias<"sub${p} sp, sp, $imm", 393 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 394 395// ADD <Rm>, sp 396def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 397 "add", "\t$Rdn, $sp, $Rn", []>, 398 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 399 // A8.6.9 Encoding T1 400 bits<4> Rdn; 401 let Inst{7} = Rdn{3}; 402 let Inst{6-3} = 0b1101; 403 let Inst{2-0} = Rdn{2-0}; 404 let DecoderMethod = "DecodeThumbAddSPReg"; 405} 406 407// ADD sp, <Rm> 408def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 409 "add", "\t$Rdn, $Rm", []>, 410 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 411 // A8.6.9 Encoding T2 412 bits<4> Rm; 413 let Inst{7} = 1; 414 let Inst{6-3} = Rm; 415 let Inst{2-0} = 0b101; 416 let DecoderMethod = "DecodeThumbAddSPReg"; 417} 418 419//===----------------------------------------------------------------------===// 420// Control Flow Instructions. 421// 422 423// Indirect branches 424let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 425 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 426 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 427 // A6.2.3 & A8.6.25 428 bits<4> Rm; 429 let Inst{6-3} = Rm; 430 let Inst{2-0} = 0b000; 431 let Unpredictable{2-0} = 0b111; 432 } 433} 434 435let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 436 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 437 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>; 438 439 // Alternative return instruction used by vararg functions. 440 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 441 2, IIC_Br, [], 442 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 443} 444 445// All calls clobber the non-callee saved registers. SP is marked as a use to 446// prevent stack-pointer assignments that appear immediately before calls from 447// potentially appearing dead. 448let isCall = 1, 449 Defs = [LR], Uses = [SP] in { 450 // Also used for Thumb2 451 def tBL : TIx2<0b11110, 0b11, 1, 452 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br, 453 "bl${p}\t$func", 454 [(ARMtcall tglobaladdr:$func)]>, 455 Requires<[IsThumb]>, Sched<[WriteBrL]> { 456 bits<24> func; 457 let Inst{26} = func{23}; 458 let Inst{25-16} = func{20-11}; 459 let Inst{13} = func{22}; 460 let Inst{11} = func{21}; 461 let Inst{10-0} = func{10-0}; 462 } 463 464 // ARMv5T and above, also used for Thumb2 465 def tBLXi : TIx2<0b11110, 0b11, 0, 466 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br, 467 "blx${p}\t$func", 468 [(ARMcall tglobaladdr:$func)]>, 469 Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> { 470 bits<24> func; 471 let Inst{26} = func{23}; 472 let Inst{25-16} = func{20-11}; 473 let Inst{13} = func{22}; 474 let Inst{11} = func{21}; 475 let Inst{10-1} = func{10-1}; 476 let Inst{0} = 0; // func{0} is assumed zero 477 } 478 479 // Also used for Thumb2 480 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 481 "blx${p}\t$func", 482 [(ARMtcall GPR:$func)]>, 483 Requires<[IsThumb, HasV5T]>, 484 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24; 485 bits<4> func; 486 let Inst{6-3} = func; 487 let Inst{2-0} = 0b000; 488 } 489 490 // ARMv4T 491 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 492 4, IIC_Br, 493 [(ARMcall_nolink tGPR:$func)]>, 494 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>; 495} 496 497let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 498 let isPredicable = 1 in 499 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 500 "b", "\t$target", [(br bb:$target)]>, 501 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> { 502 bits<11> target; 503 let Inst{10-0} = target; 504 let AsmMatchConverter = "cvtThumbBranches"; 505 } 506 507 // Far jump 508 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 509 // the clobber of LR. 510 let Defs = [LR] in 511 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), 512 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>, 513 Sched<[WriteBrTbl]>; 514 515 def tBR_JTr : tPseudoInst<(outs), 516 (ins tGPR:$target, i32imm:$jt, i32imm:$id), 517 0, IIC_Br, 518 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>, 519 Sched<[WriteBrTbl]> { 520 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 521 } 522} 523 524// FIXME: should be able to write a pattern for ARMBrcond, but can't use 525// a two-value operand where a dag node expects two operands. :( 526let isBranch = 1, isTerminator = 1 in 527 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 528 "b${p}\t$target", 529 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 530 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> { 531 bits<4> p; 532 bits<8> target; 533 let Inst{11-8} = p; 534 let Inst{7-0} = target; 535 let AsmMatchConverter = "cvtThumbBranches"; 536} 537 538 539// Tail calls 540let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 541 // IOS versions. 542 let Uses = [SP] in { 543 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 544 4, IIC_Br, [], 545 (tBX GPR:$dst, (ops 14, zero_reg))>, 546 Requires<[IsThumb]>, Sched<[WriteBr]>; 547 } 548 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls 549 // on MachO), so it's in ARMInstrThumb2.td. 550 // Non-MachO version: 551 let Uses = [SP] in { 552 def tTAILJMPdND : tPseudoExpand<(outs), 553 (ins t_brtarget:$dst, pred:$p), 554 4, IIC_Br, [], 555 (tB t_brtarget:$dst, pred:$p)>, 556 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>; 557 } 558} 559 560 561// A8.6.218 Supervisor Call (Software Interrupt) 562// A8.6.16 B: Encoding T1 563// If Inst{11-8} == 0b1111 then SEE SVC 564let isCall = 1, Uses = [SP] in 565def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 566 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> { 567 bits<8> imm; 568 let Inst{15-12} = 0b1101; 569 let Inst{11-8} = 0b1111; 570 let Inst{7-0} = imm; 571} 572 573// The assembler uses 0xDEFE for a trap instruction. 574let isBarrier = 1, isTerminator = 1 in 575def tTRAP : TI<(outs), (ins), IIC_Br, 576 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> { 577 let Inst = 0xdefe; 578} 579 580//===----------------------------------------------------------------------===// 581// Load Store Instructions. 582// 583 584// Loads: reg/reg and reg/imm5 585let canFoldAsLoad = 1, isReMaterializable = 1 in 586multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 587 Operand AddrMode_r, Operand AddrMode_i, 588 AddrMode am, InstrItinClass itin_r, 589 InstrItinClass itin_i, string asm, 590 PatFrag opnode> { 591 def r : // reg/reg 592 T1pILdStEncode<reg_opc, 593 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 594 am, itin_r, asm, "\t$Rt, $addr", 595 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 596 def i : // reg/imm5 597 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 598 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 599 am, itin_i, asm, "\t$Rt, $addr", 600 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 601} 602// Stores: reg/reg and reg/imm5 603multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 604 Operand AddrMode_r, Operand AddrMode_i, 605 AddrMode am, InstrItinClass itin_r, 606 InstrItinClass itin_i, string asm, 607 PatFrag opnode> { 608 def r : // reg/reg 609 T1pILdStEncode<reg_opc, 610 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 611 am, itin_r, asm, "\t$Rt, $addr", 612 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 613 def i : // reg/imm5 614 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 615 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 616 am, itin_i, asm, "\t$Rt, $addr", 617 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 618} 619 620// A8.6.57 & A8.6.60 621defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4, 622 t_addrmode_is4, AddrModeT1_4, 623 IIC_iLoad_r, IIC_iLoad_i, "ldr", 624 UnOpFrag<(load node:$Src)>>; 625 626// A8.6.64 & A8.6.61 627defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1, 628 t_addrmode_is1, AddrModeT1_1, 629 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 630 UnOpFrag<(zextloadi8 node:$Src)>>; 631 632// A8.6.76 & A8.6.73 633defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2, 634 t_addrmode_is2, AddrModeT1_2, 635 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 636 UnOpFrag<(zextloadi16 node:$Src)>>; 637 638let AddedComplexity = 10 in 639def tLDRSB : // A8.6.80 640 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 641 AddrModeT1_1, IIC_iLoad_bh_r, 642 "ldrsb", "\t$Rt, $addr", 643 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 644 645let AddedComplexity = 10 in 646def tLDRSH : // A8.6.84 647 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 648 AddrModeT1_2, IIC_iLoad_bh_r, 649 "ldrsh", "\t$Rt, $addr", 650 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 651 652let canFoldAsLoad = 1 in 653def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 654 "ldr", "\t$Rt, $addr", 655 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 656 T1LdStSP<{1,?,?}> { 657 bits<3> Rt; 658 bits<8> addr; 659 let Inst{10-8} = Rt; 660 let Inst{7-0} = addr; 661} 662 663let canFoldAsLoad = 1, isReMaterializable = 1 in 664def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 665 "ldr", "\t$Rt, $addr", 666 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 667 T1Encoding<{0,1,0,0,1,?}> { 668 // A6.2 & A8.6.59 669 bits<3> Rt; 670 bits<8> addr; 671 let Inst{10-8} = Rt; 672 let Inst{7-0} = addr; 673} 674 675// A8.6.194 & A8.6.192 676defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, 677 t_addrmode_is4, AddrModeT1_4, 678 IIC_iStore_r, IIC_iStore_i, "str", 679 BinOpFrag<(store node:$LHS, node:$RHS)>>; 680 681// A8.6.197 & A8.6.195 682defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1, 683 t_addrmode_is1, AddrModeT1_1, 684 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 685 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 686 687// A8.6.207 & A8.6.205 688defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2, 689 t_addrmode_is2, AddrModeT1_2, 690 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 691 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 692 693 694def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 695 "str", "\t$Rt, $addr", 696 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 697 T1LdStSP<{0,?,?}> { 698 bits<3> Rt; 699 bits<8> addr; 700 let Inst{10-8} = Rt; 701 let Inst{7-0} = addr; 702} 703 704//===----------------------------------------------------------------------===// 705// Load / store multiple Instructions. 706// 707 708// These require base address to be written back or one of the loaded regs. 709let neverHasSideEffects = 1 in { 710 711let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 712def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 713 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 714 bits<3> Rn; 715 bits<8> regs; 716 let Inst{10-8} = Rn; 717 let Inst{7-0} = regs; 718} 719 720// Writeback version is just a pseudo, as there's no encoding difference. 721// Writeback happens iff the base register is not in the destination register 722// list. 723def tLDMIA_UPD : 724 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 725 "$Rn = $wb", IIC_iLoad_mu>, 726 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 727 let Size = 2; 728 let OutOperandList = (outs GPR:$wb); 729 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 730 let Pattern = []; 731 let isCodeGenOnly = 1; 732 let isPseudo = 1; 733 list<Predicate> Predicates = [IsThumb]; 734} 735 736// There is no non-writeback version of STM for Thumb. 737let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 738def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 739 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 740 AddrModeNone, 2, IIC_iStore_mu, 741 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 742 T1Encoding<{1,1,0,0,0,?}> { 743 bits<3> Rn; 744 bits<8> regs; 745 let Inst{10-8} = Rn; 746 let Inst{7-0} = regs; 747} 748 749} // neverHasSideEffects 750 751def : InstAlias<"ldm${p} $Rn!, $regs", 752 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, 753 Requires<[IsThumb, IsThumb1Only]>; 754 755let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 756def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 757 IIC_iPop, 758 "pop${p}\t$regs", []>, 759 T1Misc<{1,1,0,?,?,?,?}> { 760 bits<16> regs; 761 let Inst{8} = regs{15}; 762 let Inst{7-0} = regs{7-0}; 763} 764 765let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 766def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 767 IIC_iStore_m, 768 "push${p}\t$regs", []>, 769 T1Misc<{0,1,0,?,?,?,?}> { 770 bits<16> regs; 771 let Inst{8} = regs{14}; 772 let Inst{7-0} = regs{7-0}; 773} 774 775//===----------------------------------------------------------------------===// 776// Arithmetic Instructions. 777// 778 779// Helper classes for encoding T1pI patterns: 780class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 781 string opc, string asm, list<dag> pattern> 782 : T1pI<oops, iops, itin, opc, asm, pattern>, 783 T1DataProcessing<opA> { 784 bits<3> Rm; 785 bits<3> Rn; 786 let Inst{5-3} = Rm; 787 let Inst{2-0} = Rn; 788} 789class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 790 string opc, string asm, list<dag> pattern> 791 : T1pI<oops, iops, itin, opc, asm, pattern>, 792 T1Misc<opA> { 793 bits<3> Rm; 794 bits<3> Rd; 795 let Inst{5-3} = Rm; 796 let Inst{2-0} = Rd; 797} 798 799// Helper classes for encoding T1sI patterns: 800class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 801 string opc, string asm, list<dag> pattern> 802 : T1sI<oops, iops, itin, opc, asm, pattern>, 803 T1DataProcessing<opA> { 804 bits<3> Rd; 805 bits<3> Rn; 806 let Inst{5-3} = Rn; 807 let Inst{2-0} = Rd; 808} 809class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 810 string opc, string asm, list<dag> pattern> 811 : T1sI<oops, iops, itin, opc, asm, pattern>, 812 T1General<opA> { 813 bits<3> Rm; 814 bits<3> Rn; 815 bits<3> Rd; 816 let Inst{8-6} = Rm; 817 let Inst{5-3} = Rn; 818 let Inst{2-0} = Rd; 819} 820class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 821 string opc, string asm, list<dag> pattern> 822 : T1sI<oops, iops, itin, opc, asm, pattern>, 823 T1General<opA> { 824 bits<3> Rd; 825 bits<3> Rm; 826 let Inst{5-3} = Rm; 827 let Inst{2-0} = Rd; 828} 829 830// Helper classes for encoding T1sIt patterns: 831class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 832 string opc, string asm, list<dag> pattern> 833 : T1sIt<oops, iops, itin, opc, asm, pattern>, 834 T1DataProcessing<opA> { 835 bits<3> Rdn; 836 bits<3> Rm; 837 let Inst{5-3} = Rm; 838 let Inst{2-0} = Rdn; 839} 840class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 841 string opc, string asm, list<dag> pattern> 842 : T1sIt<oops, iops, itin, opc, asm, pattern>, 843 T1General<opA> { 844 bits<3> Rdn; 845 bits<8> imm8; 846 let Inst{10-8} = Rdn; 847 let Inst{7-0} = imm8; 848} 849 850// Add with carry register 851let isCommutable = 1, Uses = [CPSR] in 852def tADC : // A8.6.2 853 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 854 "adc", "\t$Rdn, $Rm", 855 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 856 857// Add immediate 858def tADDi3 : // A8.6.4 T1 859 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 860 IIC_iALUi, 861 "add", "\t$Rd, $Rm, $imm3", 862 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>, 863 Sched<[WriteALU]> { 864 bits<3> imm3; 865 let Inst{8-6} = imm3; 866} 867 868def tADDi8 : // A8.6.4 T2 869 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 870 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 871 "add", "\t$Rdn, $imm8", 872 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>, 873 Sched<[WriteALU]>; 874 875// Add register 876let isCommutable = 1 in 877def tADDrr : // A8.6.6 T1 878 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 879 IIC_iALUr, 880 "add", "\t$Rd, $Rn, $Rm", 881 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 882 883let neverHasSideEffects = 1 in 884def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 885 "add", "\t$Rdn, $Rm", []>, 886 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 887 // A8.6.6 T2 888 bits<4> Rdn; 889 bits<4> Rm; 890 let Inst{7} = Rdn{3}; 891 let Inst{6-3} = Rm; 892 let Inst{2-0} = Rdn{2-0}; 893} 894 895// AND register 896let isCommutable = 1 in 897def tAND : // A8.6.12 898 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 899 IIC_iBITr, 900 "and", "\t$Rdn, $Rm", 901 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 902 903// ASR immediate 904def tASRri : // A8.6.14 905 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 906 IIC_iMOVsi, 907 "asr", "\t$Rd, $Rm, $imm5", 908 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 909 Sched<[WriteALU]> { 910 bits<5> imm5; 911 let Inst{10-6} = imm5; 912} 913 914// ASR register 915def tASRrr : // A8.6.15 916 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 917 IIC_iMOVsr, 918 "asr", "\t$Rdn, $Rm", 919 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 920 921// BIC register 922def tBIC : // A8.6.20 923 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 924 IIC_iBITr, 925 "bic", "\t$Rdn, $Rm", 926 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>, 927 Sched<[WriteALU]>; 928 929// CMN register 930let isCompare = 1, Defs = [CPSR] in { 931//FIXME: Disable CMN, as CCodes are backwards from compare expectations 932// Compare-to-zero still works out, just not the relationals 933//def tCMN : // A8.6.33 934// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 935// IIC_iCMPr, 936// "cmn", "\t$lhs, $rhs", 937// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 938 939def tCMNz : // A8.6.33 940 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 941 IIC_iCMPr, 942 "cmn", "\t$Rn, $Rm", 943 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>; 944 945} // isCompare = 1, Defs = [CPSR] 946 947// CMP immediate 948let isCompare = 1, Defs = [CPSR] in { 949def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 950 "cmp", "\t$Rn, $imm8", 951 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 952 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> { 953 // A8.6.35 954 bits<3> Rn; 955 bits<8> imm8; 956 let Inst{10-8} = Rn; 957 let Inst{7-0} = imm8; 958} 959 960// CMP register 961def tCMPr : // A8.6.36 T1 962 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 963 IIC_iCMPr, 964 "cmp", "\t$Rn, $Rm", 965 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>; 966 967def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 968 "cmp", "\t$Rn, $Rm", []>, 969 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> { 970 // A8.6.36 T2 971 bits<4> Rm; 972 bits<4> Rn; 973 let Inst{7} = Rn{3}; 974 let Inst{6-3} = Rm; 975 let Inst{2-0} = Rn{2-0}; 976} 977} // isCompare = 1, Defs = [CPSR] 978 979 980// XOR register 981let isCommutable = 1 in 982def tEOR : // A8.6.45 983 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 984 IIC_iBITr, 985 "eor", "\t$Rdn, $Rm", 986 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 987 988// LSL immediate 989def tLSLri : // A8.6.88 990 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 991 IIC_iMOVsi, 992 "lsl", "\t$Rd, $Rm, $imm5", 993 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>, 994 Sched<[WriteALU]> { 995 bits<5> imm5; 996 let Inst{10-6} = imm5; 997} 998 999// LSL register 1000def tLSLrr : // A8.6.89 1001 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1002 IIC_iMOVsr, 1003 "lsl", "\t$Rdn, $Rm", 1004 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1005 1006// LSR immediate 1007def tLSRri : // A8.6.90 1008 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 1009 IIC_iMOVsi, 1010 "lsr", "\t$Rd, $Rm, $imm5", 1011 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 1012 Sched<[WriteALU]> { 1013 bits<5> imm5; 1014 let Inst{10-6} = imm5; 1015} 1016 1017// LSR register 1018def tLSRrr : // A8.6.91 1019 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1020 IIC_iMOVsr, 1021 "lsr", "\t$Rdn, $Rm", 1022 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1023 1024// Move register 1025let isMoveImm = 1 in 1026def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1027 "mov", "\t$Rd, $imm8", 1028 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1029 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> { 1030 // A8.6.96 1031 bits<3> Rd; 1032 bits<8> imm8; 1033 let Inst{10-8} = Rd; 1034 let Inst{7-0} = imm8; 1035} 1036// Because we have an explicit tMOVSr below, we need an alias to handle 1037// the immediate "movs" form here. Blech. 1038def : tInstAlias <"movs $Rdn, $imm", 1039 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1040 1041// A7-73: MOV(2) - mov setting flag. 1042 1043let neverHasSideEffects = 1 in { 1044def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1045 2, IIC_iMOVr, 1046 "mov", "\t$Rd, $Rm", "", []>, 1047 T1Special<{1,0,?,?}>, Sched<[WriteALU]> { 1048 // A8.6.97 1049 bits<4> Rd; 1050 bits<4> Rm; 1051 let Inst{7} = Rd{3}; 1052 let Inst{6-3} = Rm; 1053 let Inst{2-0} = Rd{2-0}; 1054} 1055let Defs = [CPSR] in 1056def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1057 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> { 1058 // A8.6.97 1059 bits<3> Rd; 1060 bits<3> Rm; 1061 let Inst{15-6} = 0b0000000000; 1062 let Inst{5-3} = Rm; 1063 let Inst{2-0} = Rd; 1064} 1065} // neverHasSideEffects 1066 1067// Multiply register 1068let isCommutable = 1 in 1069def tMUL : // A8.6.105 T1 1070 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1071 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1072 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1073 T1DataProcessing<0b1101> { 1074 bits<3> Rd; 1075 bits<3> Rn; 1076 let Inst{5-3} = Rn; 1077 let Inst{2-0} = Rd; 1078 let AsmMatchConverter = "cvtThumbMultiply"; 1079} 1080 1081def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1082 pred:$p)>; 1083 1084// Move inverse register 1085def tMVN : // A8.6.107 1086 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1087 "mvn", "\t$Rd, $Rn", 1088 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>; 1089 1090// Bitwise or register 1091let isCommutable = 1 in 1092def tORR : // A8.6.114 1093 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1094 IIC_iBITr, 1095 "orr", "\t$Rdn, $Rm", 1096 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1097 1098// Swaps 1099def tREV : // A8.6.134 1100 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1101 IIC_iUNAr, 1102 "rev", "\t$Rd, $Rm", 1103 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1104 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1105 1106def tREV16 : // A8.6.135 1107 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1108 IIC_iUNAr, 1109 "rev16", "\t$Rd, $Rm", 1110 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1111 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1112 1113def tREVSH : // A8.6.136 1114 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1115 IIC_iUNAr, 1116 "revsh", "\t$Rd, $Rm", 1117 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1118 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1119 1120// Rotate right register 1121def tROR : // A8.6.139 1122 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1123 IIC_iMOVsr, 1124 "ror", "\t$Rdn, $Rm", 1125 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>, 1126 Sched<[WriteALU]>; 1127 1128// Negate register 1129def tRSB : // A8.6.141 1130 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1131 IIC_iALUi, 1132 "rsb", "\t$Rd, $Rn, #0", 1133 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>; 1134 1135// Subtract with carry register 1136let Uses = [CPSR] in 1137def tSBC : // A8.6.151 1138 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1139 IIC_iALUr, 1140 "sbc", "\t$Rdn, $Rm", 1141 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>, 1142 Sched<[WriteALU]>; 1143 1144// Subtract immediate 1145def tSUBi3 : // A8.6.210 T1 1146 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1147 IIC_iALUi, 1148 "sub", "\t$Rd, $Rm, $imm3", 1149 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>, 1150 Sched<[WriteALU]> { 1151 bits<3> imm3; 1152 let Inst{8-6} = imm3; 1153} 1154 1155def tSUBi8 : // A8.6.210 T2 1156 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1157 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1158 "sub", "\t$Rdn, $imm8", 1159 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>, 1160 Sched<[WriteALU]>; 1161 1162// Subtract register 1163def tSUBrr : // A8.6.212 1164 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1165 IIC_iALUr, 1166 "sub", "\t$Rd, $Rn, $Rm", 1167 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>, 1168 Sched<[WriteALU]>; 1169 1170// Sign-extend byte 1171def tSXTB : // A8.6.222 1172 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1173 IIC_iUNAr, 1174 "sxtb", "\t$Rd, $Rm", 1175 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1176 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1177 Sched<[WriteALU]>; 1178 1179// Sign-extend short 1180def tSXTH : // A8.6.224 1181 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1182 IIC_iUNAr, 1183 "sxth", "\t$Rd, $Rm", 1184 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1185 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1186 Sched<[WriteALU]>; 1187 1188// Test 1189let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1190def tTST : // A8.6.230 1191 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1192 "tst", "\t$Rn, $Rm", 1193 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>, 1194 Sched<[WriteALU]>; 1195 1196// A8.8.247 UDF - Undefined (Encoding T1) 1197def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", 1198 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 { 1199 bits<8> imm8; 1200 let Inst{15-12} = 0b1101; 1201 let Inst{11-8} = 0b1110; 1202 let Inst{7-0} = imm8; 1203} 1204 1205// Zero-extend byte 1206def tUXTB : // A8.6.262 1207 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1208 IIC_iUNAr, 1209 "uxtb", "\t$Rd, $Rm", 1210 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1211 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1212 Sched<[WriteALU]>; 1213 1214// Zero-extend short 1215def tUXTH : // A8.6.264 1216 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1217 IIC_iUNAr, 1218 "uxth", "\t$Rd, $Rm", 1219 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1220 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1221 1222// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1223// Expanded after instruction selection into a branch sequence. 1224let usesCustomInserter = 1 in // Expanded after instruction selection. 1225 def tMOVCCr_pseudo : 1226 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p), 1227 NoItinerary, 1228 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>; 1229 1230// tLEApcrel - Load a pc-relative address into a register without offending the 1231// assembler. 1232 1233def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1234 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1235 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> { 1236 bits<3> Rd; 1237 bits<8> addr; 1238 let Inst{10-8} = Rd; 1239 let Inst{7-0} = addr; 1240 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1241} 1242 1243let neverHasSideEffects = 1, isReMaterializable = 1 in 1244def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1245 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1246 1247let hasSideEffects = 1 in 1248def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1249 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1250 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1251 1252//===----------------------------------------------------------------------===// 1253// TLS Instructions 1254// 1255 1256// __aeabi_read_tp preserves the registers r1-r3. 1257// This is a pseudo inst so that we can get the encoding right, 1258// complete with fixup for the aeabi_read_tp function. 1259let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1260def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1261 [(set R0, ARMthread_pointer)]>, 1262 Sched<[WriteBr]>; 1263 1264//===----------------------------------------------------------------------===// 1265// SJLJ Exception handling intrinsics 1266// 1267 1268// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1269// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1270// from some other function to get here, and we're using the stack frame for the 1271// containing function to save/restore registers, we can't keep anything live in 1272// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1273// tromped upon when we get here from a longjmp(). We force everything out of 1274// registers except for our own input by listing the relevant registers in 1275// Defs. By doing so, we also cause the prologue/epilogue code to actively 1276// preserve all of the callee-saved resgisters, which is exactly what we want. 1277// $val is a scratch register for our use. 1278let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1279 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1280 usesCustomInserter = 1 in 1281def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1282 AddrModeNone, 0, NoItinerary, "","", 1283 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1284 1285// FIXME: Non-IOS version(s) 1286let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1287 Defs = [ R7, LR, SP ] in 1288def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1289 AddrModeNone, 0, IndexModeNone, 1290 Pseudo, NoItinerary, "", "", 1291 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1292 Requires<[IsThumb, IsIOS]>; 1293 1294//===----------------------------------------------------------------------===// 1295// Non-Instruction Patterns 1296// 1297 1298// Comparisons 1299def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1300 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1301def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1302 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1303 1304// Add with carry 1305def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1306 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1307def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1308 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1309def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1310 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1311 1312// Subtract with carry 1313def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1314 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1315def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1316 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1317def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1318 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1319 1320// Bswap 16 with load/store 1321def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rrs2:$addr)), (i32 16)), 1322 (tREV16 (tLDRHr t_addrmode_rrs2:$addr))>; 1323def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)), 1324 (tREV16 (tLDRHi t_addrmode_is2:$addr))>; 1325def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1326 t_addrmode_rrs2:$addr), 1327 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rrs2:$addr)>; 1328def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1329 t_addrmode_is2:$addr), 1330 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>; 1331 1332// ConstantPool 1333def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1334 1335// GlobalAddress 1336def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr), 1337 IIC_iLoadiALU, 1338 [(set tGPR:$dst, 1339 (ARMWrapperPIC tglobaladdr:$addr))]>, 1340 Requires<[IsThumb, DontUseMovt]>; 1341 1342def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src), 1343 IIC_iLoad_i, 1344 [(set tGPR:$dst, 1345 (ARMWrapper tglobaladdr:$src))]>, 1346 Requires<[IsThumb, DontUseMovt]>; 1347 1348 1349// JumpTable 1350def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1351 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 1352 1353// Direct calls 1354def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1355 Requires<[IsThumb]>; 1356 1357def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1358 Requires<[IsThumb, HasV5T]>; 1359 1360// Indirect calls to ARM routines 1361def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1362 Requires<[IsThumb, HasV5T]>; 1363 1364// zextload i1 -> zextload i8 1365def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), 1366 (tLDRBr t_addrmode_rrs1:$addr)>; 1367def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1368 (tLDRBi t_addrmode_is1:$addr)>; 1369 1370// extload -> zextload 1371def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1372def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1373def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1374def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1375def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>; 1376def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1377 1378// If it's impossible to use [r,r] address mode for sextload, select to 1379// ldr{b|h} + sxt{b|h} instead. 1380def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1381 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1382 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1383def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1384 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>, 1385 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1386def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1387 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1388 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1389def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1390 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>, 1391 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1392 1393def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1394 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>; 1395def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1396 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1397def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1398 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>; 1399def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1400 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1401 1402def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1403 (tLDRBi t_addrmode_is1:$src)>; 1404def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src), 1405 (tLDRBr t_addrmode_rrs1:$src)>; 1406def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1407 (tLDRHi t_addrmode_is2:$src)>; 1408def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src), 1409 (tLDRHr t_addrmode_rrs2:$src)>; 1410def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1411 (tLDRi t_addrmode_is4:$src)>; 1412def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src), 1413 (tLDRr t_addrmode_rrs4:$src)>; 1414def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1415 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1416def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val), 1417 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>; 1418def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1419 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1420def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val), 1421 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>; 1422def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1423 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1424def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val), 1425 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>; 1426 1427// Large immediate handling. 1428 1429// Two piece imms. 1430def : T1Pat<(i32 thumb_immshifted:$src), 1431 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1432 (thumb_immshifted_shamt imm:$src))>; 1433 1434def : T1Pat<(i32 imm0_255_comp:$src), 1435 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1436 1437// Pseudo instruction that combines ldr from constpool and add pc. This should 1438// be expanded into two instructions late to allow if-conversion and 1439// scheduling. 1440let isReMaterializable = 1 in 1441def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1442 NoItinerary, 1443 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1444 imm:$cp))]>, 1445 Requires<[IsThumb, IsThumb1Only]>; 1446 1447// Pseudo-instruction for merged POP and return. 1448// FIXME: remove when we have a way to marking a MI with these properties. 1449let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1450 hasExtraDefRegAllocReq = 1 in 1451def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1452 2, IIC_iPop_Br, [], 1453 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; 1454 1455// Indirect branch using "mov pc, $Rm" 1456let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1457 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1458 2, IIC_Br, [(brind GPR:$Rm)], 1459 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 1460} 1461 1462 1463// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1464// encoding is available on ARMv6K, but we don't differentiate that finely. 1465def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>; 1466 1467 1468// For round-trip assembly/disassembly, we have to handle a CPS instruction 1469// without any iflags. That's not, strictly speaking, valid syntax, but it's 1470// a useful extension and assembles to defined behaviour (the insn does 1471// nothing). 1472def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1473def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1474 1475// "neg" is and alias for "rsb rd, rn, #0" 1476def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1477 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1478 1479 1480// Implied destination operand forms for shifts. 1481def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1482 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1483def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1484 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1485def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1486 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1487