ARMInstrThumb.td revision ed8384806e56952c44f8a717c1ef54a8468d2c8d
1//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22def imm_neg_XFORM : SDNodeXForm<imm, [{ 23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 24}]>; 25def imm_comp_XFORM : SDNodeXForm<imm, [{ 26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 27}]>; 28 29def imm0_7_neg : PatLeaf<(i32 imm), [{ 30 return (uint32_t)-N->getZExtValue() < 8; 31}], imm_neg_XFORM>; 32 33def imm0_255_asmoperand : AsmOperandClass { let Name = "Imm0_255"; } 34def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 35 let ParserMatchClass = imm0_255_asmoperand; 36} 37def imm0_255_comp : PatLeaf<(i32 imm), [{ 38 return ~((uint32_t)N->getZExtValue()) < 256; 39}]>; 40 41def imm8_255 : ImmLeaf<i32, [{ 42 return Imm >= 8 && Imm < 256; 43}]>; 44def imm8_255_neg : PatLeaf<(i32 imm), [{ 45 unsigned Val = -N->getZExtValue(); 46 return Val >= 8 && Val < 256; 47}], imm_neg_XFORM>; 48 49// Break imm's up into two pieces: an immediate + a left shift. This uses 50// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 51// to get the val/shift pieces. 52def thumb_immshifted : PatLeaf<(imm), [{ 53 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 54}]>; 55 56def thumb_immshifted_val : SDNodeXForm<imm, [{ 57 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 58 return CurDAG->getTargetConstant(V, MVT::i32); 59}]>; 60 61def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 62 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 63 return CurDAG->getTargetConstant(V, MVT::i32); 64}]>; 65 66// ADR instruction labels. 67def t_adrlabel : Operand<i32> { 68 let EncoderMethod = "getThumbAdrLabelOpValue"; 69} 70 71// Scaled 4 immediate. 72def t_imm_s4 : Operand<i32> { 73 let PrintMethod = "printThumbS4ImmOperand"; 74 let OperandType = "OPERAND_IMMEDIATE"; 75} 76 77// Define Thumb specific addressing modes. 78 79let OperandType = "OPERAND_PCREL" in { 80def t_brtarget : Operand<OtherVT> { 81 let EncoderMethod = "getThumbBRTargetOpValue"; 82} 83 84def t_bcctarget : Operand<i32> { 85 let EncoderMethod = "getThumbBCCTargetOpValue"; 86} 87 88def t_cbtarget : Operand<i32> { 89 let EncoderMethod = "getThumbCBTargetOpValue"; 90} 91 92def t_bltarget : Operand<i32> { 93 let EncoderMethod = "getThumbBLTargetOpValue"; 94} 95 96def t_blxtarget : Operand<i32> { 97 let EncoderMethod = "getThumbBLXTargetOpValue"; 98} 99} 100 101def MemModeRegThumbAsmOperand : AsmOperandClass { 102 let Name = "MemModeRegThumb"; 103 let SuperClasses = []; 104} 105 106def MemModeImmThumbAsmOperand : AsmOperandClass { 107 let Name = "MemModeImmThumb"; 108 let SuperClasses = []; 109} 110 111// t_addrmode_rr := reg + reg 112// 113def t_addrmode_rr : Operand<i32>, 114 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 115 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 116 let PrintMethod = "printThumbAddrModeRROperand"; 117 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 118} 119 120// t_addrmode_rrs := reg + reg 121// 122def t_addrmode_rrs1 : Operand<i32>, 123 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 124 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 125 let PrintMethod = "printThumbAddrModeRROperand"; 126 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 127 let ParserMatchClass = MemModeRegThumbAsmOperand; 128} 129def t_addrmode_rrs2 : Operand<i32>, 130 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 131 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 132 let PrintMethod = "printThumbAddrModeRROperand"; 133 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 134 let ParserMatchClass = MemModeRegThumbAsmOperand; 135} 136def t_addrmode_rrs4 : Operand<i32>, 137 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 138 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 139 let PrintMethod = "printThumbAddrModeRROperand"; 140 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 141 let ParserMatchClass = MemModeRegThumbAsmOperand; 142} 143 144// t_addrmode_is4 := reg + imm5 * 4 145// 146def t_addrmode_is4 : Operand<i32>, 147 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 148 let EncoderMethod = "getAddrModeISOpValue"; 149 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 150 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 151 let ParserMatchClass = MemModeImmThumbAsmOperand; 152} 153 154// t_addrmode_is2 := reg + imm5 * 2 155// 156def t_addrmode_is2 : Operand<i32>, 157 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 158 let EncoderMethod = "getAddrModeISOpValue"; 159 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 160 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 161 let ParserMatchClass = MemModeImmThumbAsmOperand; 162} 163 164// t_addrmode_is1 := reg + imm5 165// 166def t_addrmode_is1 : Operand<i32>, 167 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 168 let EncoderMethod = "getAddrModeISOpValue"; 169 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 170 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 171 let ParserMatchClass = MemModeImmThumbAsmOperand; 172} 173 174// t_addrmode_sp := sp + imm8 * 4 175// 176def t_addrmode_sp : Operand<i32>, 177 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 178 let EncoderMethod = "getAddrModeThumbSPOpValue"; 179 let PrintMethod = "printThumbAddrModeSPOperand"; 180 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 181 let ParserMatchClass = MemModeImmThumbAsmOperand; 182} 183 184// t_addrmode_pc := <label> => pc + imm8 * 4 185// 186def t_addrmode_pc : Operand<i32> { 187 let EncoderMethod = "getAddrModePCOpValue"; 188 let ParserMatchClass = MemModeImmThumbAsmOperand; 189} 190 191//===----------------------------------------------------------------------===// 192// Miscellaneous Instructions. 193// 194 195// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 196// from removing one half of the matched pairs. That breaks PEI, which assumes 197// these will always be in pairs, and asserts if it finds otherwise. Better way? 198let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 199def tADJCALLSTACKUP : 200 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 201 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 202 Requires<[IsThumb, IsThumb1Only]>; 203 204def tADJCALLSTACKDOWN : 205 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 206 [(ARMcallseq_start imm:$amt)]>, 207 Requires<[IsThumb, IsThumb1Only]>; 208} 209 210// T1Disassembly - A simple class to make encoding some disassembly patterns 211// easier and less verbose. 212class T1Disassembly<bits<2> op1, bits<8> op2> 213 : T1Encoding<0b101111> { 214 let Inst{9-8} = op1; 215 let Inst{7-0} = op2; 216} 217 218def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", 219 [/* For disassembly only; pattern left blank */]>, 220 T1Disassembly<0b11, 0x00>; // A8.6.110 221 222def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", 223 [/* For disassembly only; pattern left blank */]>, 224 T1Disassembly<0b11, 0x10>; // A8.6.410 225 226def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", 227 [/* For disassembly only; pattern left blank */]>, 228 T1Disassembly<0b11, 0x20>; // A8.6.408 229 230def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", 231 [/* For disassembly only; pattern left blank */]>, 232 T1Disassembly<0b11, 0x30>; // A8.6.409 233 234def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", 235 [/* For disassembly only; pattern left blank */]>, 236 T1Disassembly<0b11, 0x40>; // A8.6.157 237 238// The i32imm operand $val can be used by a debugger to store more information 239// about the breakpoint. 240def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val", 241 [/* For disassembly only; pattern left blank */]>, 242 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> { 243 // A8.6.22 244 bits<8> val; 245 let Inst{7-0} = val; 246} 247 248def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 249 []>, T1Encoding<0b101101> { 250 bits<1> end; 251 // A8.6.156 252 let Inst{9-5} = 0b10010; 253 let Inst{4} = 1; 254 let Inst{3} = end; 255 let Inst{2-0} = 0b000; 256} 257 258// Change Processor State is a system instruction -- for disassembly only. 259def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 260 NoItinerary, "cps$imod $iflags", 261 [/* For disassembly only; pattern left blank */]>, 262 T1Misc<0b0110011> { 263 // A8.6.38 & B6.1.1 264 bit imod; 265 bits<3> iflags; 266 267 let Inst{4} = imod; 268 let Inst{3} = 0; 269 let Inst{2-0} = iflags; 270} 271 272// For both thumb1 and thumb2. 273let isNotDuplicable = 1, isCodeGenOnly = 1 in 274def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 275 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 276 T1Special<{0,0,?,?}> { 277 // A8.6.6 278 bits<3> dst; 279 let Inst{6-3} = 0b1111; // Rm = pc 280 let Inst{2-0} = dst; 281} 282 283// PC relative add (ADR). 284def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi, 285 "add\t$dst, pc, $rhs", []>, 286 T1Encoding<{1,0,1,0,0,?}> { 287 // A6.2 & A8.6.10 288 bits<3> dst; 289 bits<8> rhs; 290 let Inst{10-8} = dst; 291 let Inst{7-0} = rhs; 292} 293 294// ADD <Rd>, sp, #<imm8> 295// This is rematerializable, which is particularly useful for taking the 296// address of locals. 297let isReMaterializable = 1 in 298def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi, 299 "add\t$dst, $sp, $rhs", []>, 300 T1Encoding<{1,0,1,0,1,?}> { 301 // A6.2 & A8.6.8 302 bits<3> dst; 303 bits<8> rhs; 304 let Inst{10-8} = dst; 305 let Inst{7-0} = rhs; 306} 307 308// ADD sp, sp, #<imm7> 309def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 310 "add\t$dst, $rhs", []>, 311 T1Misc<{0,0,0,0,0,?,?}> { 312 // A6.2.5 & A8.6.8 313 bits<7> rhs; 314 let Inst{6-0} = rhs; 315} 316 317// SUB sp, sp, #<imm7> 318// FIXME: The encoding and the ASM string don't match up. 319def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 320 "sub\t$dst, $rhs", []>, 321 T1Misc<{0,0,0,0,1,?,?}> { 322 // A6.2.5 & A8.6.214 323 bits<7> rhs; 324 let Inst{6-0} = rhs; 325} 326 327// ADD <Rm>, sp 328def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 329 "add\t$dst, $rhs", []>, 330 T1Special<{0,0,?,?}> { 331 // A8.6.9 Encoding T1 332 bits<4> dst; 333 let Inst{7} = dst{3}; 334 let Inst{6-3} = 0b1101; 335 let Inst{2-0} = dst{2-0}; 336} 337 338// ADD sp, <Rm> 339def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 340 "add\t$dst, $rhs", []>, 341 T1Special<{0,0,?,?}> { 342 // A8.6.9 Encoding T2 343 bits<4> dst; 344 let Inst{7} = 1; 345 let Inst{6-3} = dst; 346 let Inst{2-0} = 0b101; 347} 348 349//===----------------------------------------------------------------------===// 350// Control Flow Instructions. 351// 352 353// Indirect branches 354let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 355 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 356 T1Special<{1,1,0,?}> { 357 // A6.2.3 & A8.6.25 358 bits<4> Rm; 359 let Inst{6-3} = Rm; 360 let Inst{2-0} = 0b000; 361 } 362} 363 364let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 365 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 366 [(ARMretflag)], (tBX LR, pred:$p)>; 367 368 // Alternative return instruction used by vararg functions. 369 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 370 2, IIC_Br, [], 371 (tBX GPR:$Rm, pred:$p)>; 372} 373 374// All calls clobber the non-callee saved registers. SP is marked as a use to 375// prevent stack-pointer assignments that appear immediately before calls from 376// potentially appearing dead. 377let isCall = 1, 378 // On non-Darwin platforms R9 is callee-saved. 379 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], 380 Uses = [SP] in { 381 // Also used for Thumb2 382 def tBL : TIx2<0b11110, 0b11, 1, 383 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br, 384 "bl${p}\t$func", 385 [(ARMtcall tglobaladdr:$func)]>, 386 Requires<[IsThumb, IsNotDarwin]> { 387 bits<21> func; 388 let Inst{25-16} = func{20-11}; 389 let Inst{13} = 1; 390 let Inst{11} = 1; 391 let Inst{10-0} = func{10-0}; 392 } 393 394 // ARMv5T and above, also used for Thumb2 395 def tBLXi : TIx2<0b11110, 0b11, 0, 396 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br, 397 "blx${p}\t$func", 398 [(ARMcall tglobaladdr:$func)]>, 399 Requires<[IsThumb, HasV5T, IsNotDarwin]> { 400 bits<21> func; 401 let Inst{25-16} = func{20-11}; 402 let Inst{13} = 1; 403 let Inst{11} = 1; 404 let Inst{10-1} = func{10-1}; 405 let Inst{0} = 0; // func{0} is assumed zero 406 } 407 408 // Also used for Thumb2 409 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br, 410 "blx${p}\t$func", 411 [(ARMtcall GPR:$func)]>, 412 Requires<[IsThumb, HasV5T, IsNotDarwin]>, 413 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24; 414 bits<4> func; 415 let Inst{6-3} = func; 416 let Inst{2-0} = 0b000; 417 } 418 419 // ARMv4T 420 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), 421 4, IIC_Br, 422 [(ARMcall_nolink tGPR:$func)]>, 423 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>; 424} 425 426let isCall = 1, 427 // On Darwin R9 is call-clobbered. 428 // R7 is marked as a use to prevent frame-pointer assignments from being 429 // moved above / below calls. 430 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], 431 Uses = [R7, SP] in { 432 // Also used for Thumb2 433 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops), 434 4, IIC_Br, [(ARMtcall tglobaladdr:$func)], 435 (tBL pred:$p, t_bltarget:$func)>, 436 Requires<[IsThumb, IsDarwin]>; 437 438 // ARMv5T and above, also used for Thumb2 439 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops), 440 4, IIC_Br, [(ARMcall tglobaladdr:$func)], 441 (tBLXi pred:$p, t_blxtarget:$func)>, 442 Requires<[IsThumb, HasV5T, IsDarwin]>; 443 444 // Also used for Thumb2 445 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops), 446 2, IIC_Br, [(ARMtcall GPR:$func)], 447 (tBLXr pred:$p, GPR:$func)>, 448 Requires<[IsThumb, HasV5T, IsDarwin]>; 449 450 // ARMv4T 451 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), 452 4, IIC_Br, 453 [(ARMcall_nolink tGPR:$func)]>, 454 Requires<[IsThumb, IsThumb1Only, IsDarwin]>; 455} 456 457let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 458 let isPredicable = 1 in 459 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br, 460 "b\t$target", [(br bb:$target)]>, 461 T1Encoding<{1,1,1,0,0,?}> { 462 bits<11> target; 463 let Inst{10-0} = target; 464 } 465 466 // Far jump 467 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 468 // the clobber of LR. 469 let Defs = [LR] in 470 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), 471 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>; 472 473 def tBR_JTr : tPseudoInst<(outs), 474 (ins tGPR:$target, i32imm:$jt, i32imm:$id), 475 0, IIC_Br, 476 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> { 477 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 478 } 479} 480 481// FIXME: should be able to write a pattern for ARMBrcond, but can't use 482// a two-value operand where a dag node expects two operands. :( 483let isBranch = 1, isTerminator = 1 in 484 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 485 "b${p}\t$target", 486 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 487 T1BranchCond<{1,1,0,1}> { 488 bits<4> p; 489 bits<8> target; 490 let Inst{11-8} = p; 491 let Inst{7-0} = target; 492} 493 494// Compare and branch on zero / non-zero 495let isBranch = 1, isTerminator = 1 in { 496 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br, 497 "cbz\t$Rn, $target", []>, 498 T1Misc<{0,0,?,1,?,?,?}> { 499 // A8.6.27 500 bits<6> target; 501 bits<3> Rn; 502 let Inst{9} = target{5}; 503 let Inst{7-3} = target{4-0}; 504 let Inst{2-0} = Rn; 505 } 506 507 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br, 508 "cbnz\t$cmp, $target", []>, 509 T1Misc<{1,0,?,1,?,?,?}> { 510 // A8.6.27 511 bits<6> target; 512 bits<3> Rn; 513 let Inst{9} = target{5}; 514 let Inst{7-3} = target{4-0}; 515 let Inst{2-0} = Rn; 516 } 517} 518 519// Tail calls 520let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 521 // Darwin versions. 522 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], 523 Uses = [SP] in { 524 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls 525 // on Darwin), so it's in ARMInstrThumb2.td. 526 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 527 4, IIC_Br, [], 528 (tBX GPR:$dst, (ops 14, zero_reg))>, 529 Requires<[IsThumb, IsDarwin]>; 530 } 531 // Non-Darwin versions (the difference is R9). 532 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC], 533 Uses = [SP] in { 534 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops), 535 4, IIC_Br, [], 536 (tB t_brtarget:$dst)>, 537 Requires<[IsThumb, IsNotDarwin]>; 538 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 539 4, IIC_Br, [], 540 (tBX GPR:$dst, (ops 14, zero_reg))>, 541 Requires<[IsThumb, IsNotDarwin]>; 542 } 543} 544 545 546// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only 547// A8.6.16 B: Encoding T1 548// If Inst{11-8} == 0b1111 then SEE SVC 549let isCall = 1, Uses = [SP] in 550def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 551 "svc", "\t$imm", []>, Encoding16 { 552 bits<8> imm; 553 let Inst{15-12} = 0b1101; 554 let Inst{11-8} = 0b1111; 555 let Inst{7-0} = imm; 556} 557 558// The assembler uses 0xDEFE for a trap instruction. 559let isBarrier = 1, isTerminator = 1 in 560def tTRAP : TI<(outs), (ins), IIC_Br, 561 "trap", [(trap)]>, Encoding16 { 562 let Inst = 0xdefe; 563} 564 565//===----------------------------------------------------------------------===// 566// Load Store Instructions. 567// 568 569// Loads: reg/reg and reg/imm5 570let canFoldAsLoad = 1, isReMaterializable = 1 in 571multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 572 Operand AddrMode_r, Operand AddrMode_i, 573 AddrMode am, InstrItinClass itin_r, 574 InstrItinClass itin_i, string asm, 575 PatFrag opnode> { 576 def r : // reg/reg 577 T1pILdStEncode<reg_opc, 578 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 579 am, itin_r, asm, "\t$Rt, $addr", 580 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 581 def i : // reg/imm5 582 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 583 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 584 am, itin_i, asm, "\t$Rt, $addr", 585 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 586} 587// Stores: reg/reg and reg/imm5 588multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 589 Operand AddrMode_r, Operand AddrMode_i, 590 AddrMode am, InstrItinClass itin_r, 591 InstrItinClass itin_i, string asm, 592 PatFrag opnode> { 593 def r : // reg/reg 594 T1pILdStEncode<reg_opc, 595 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 596 am, itin_r, asm, "\t$Rt, $addr", 597 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 598 def i : // reg/imm5 599 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 600 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 601 am, itin_i, asm, "\t$Rt, $addr", 602 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 603} 604 605// A8.6.57 & A8.6.60 606defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4, 607 t_addrmode_is4, AddrModeT1_4, 608 IIC_iLoad_r, IIC_iLoad_i, "ldr", 609 UnOpFrag<(load node:$Src)>>; 610 611// A8.6.64 & A8.6.61 612defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1, 613 t_addrmode_is1, AddrModeT1_1, 614 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 615 UnOpFrag<(zextloadi8 node:$Src)>>; 616 617// A8.6.76 & A8.6.73 618defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2, 619 t_addrmode_is2, AddrModeT1_2, 620 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 621 UnOpFrag<(zextloadi16 node:$Src)>>; 622 623let AddedComplexity = 10 in 624def tLDRSB : // A8.6.80 625 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr), 626 AddrModeT1_1, IIC_iLoad_bh_r, 627 "ldrsb", "\t$dst, $addr", 628 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>; 629 630let AddedComplexity = 10 in 631def tLDRSH : // A8.6.84 632 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr), 633 AddrModeT1_2, IIC_iLoad_bh_r, 634 "ldrsh", "\t$dst, $addr", 635 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>; 636 637let canFoldAsLoad = 1 in 638def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 639 "ldr", "\t$Rt, $addr", 640 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 641 T1LdStSP<{1,?,?}> { 642 bits<3> Rt; 643 bits<8> addr; 644 let Inst{10-8} = Rt; 645 let Inst{7-0} = addr; 646} 647 648// Load tconstpool 649// FIXME: Use ldr.n to work around a Darwin assembler bug. 650let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in 651def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 652 "ldr", ".n\t$Rt, $addr", 653 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 654 T1Encoding<{0,1,0,0,1,?}> { 655 // A6.2 & A8.6.59 656 bits<3> Rt; 657 bits<8> addr; 658 let Inst{10-8} = Rt; 659 let Inst{7-0} = addr; 660} 661 662// FIXME: Remove this entry when the above ldr.n workaround is fixed. 663// For disassembly use only. 664def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 665 "ldr", "\t$Rt, $addr", 666 [/* disassembly only */]>, 667 T1Encoding<{0,1,0,0,1,?}> { 668 // A6.2 & A8.6.59 669 bits<3> Rt; 670 bits<8> addr; 671 let Inst{10-8} = Rt; 672 let Inst{7-0} = addr; 673} 674 675// A8.6.194 & A8.6.192 676defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, 677 t_addrmode_is4, AddrModeT1_4, 678 IIC_iStore_r, IIC_iStore_i, "str", 679 BinOpFrag<(store node:$LHS, node:$RHS)>>; 680 681// A8.6.197 & A8.6.195 682defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1, 683 t_addrmode_is1, AddrModeT1_1, 684 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 685 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 686 687// A8.6.207 & A8.6.205 688defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2, 689 t_addrmode_is2, AddrModeT1_2, 690 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 691 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 692 693 694def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 695 "str", "\t$Rt, $addr", 696 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 697 T1LdStSP<{0,?,?}> { 698 bits<3> Rt; 699 bits<8> addr; 700 let Inst{10-8} = Rt; 701 let Inst{7-0} = addr; 702} 703 704//===----------------------------------------------------------------------===// 705// Load / store multiple Instructions. 706// 707 708multiclass thumb_ldst_mult<string asm, InstrItinClass itin, 709 InstrItinClass itin_upd, bits<6> T1Enc, 710 bit L_bit, string baseOpc> { 711 def IA : 712 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 713 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>, 714 T1Encoding<T1Enc> { 715 bits<3> Rn; 716 bits<8> regs; 717 let Inst{10-8} = Rn; 718 let Inst{7-0} = regs; 719 } 720 721 def IA_UPD : 722 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 723 "$Rn = $wb", itin_upd>, 724 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA")) 725 GPR:$Rn, pred:$p, reglist:$regs)> { 726 let Size = 2; 727 let OutOperandList = (outs GPR:$wb); 728 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 729 let Pattern = []; 730 let isCodeGenOnly = 1; 731 let isPseudo = 1; 732 list<Predicate> Predicates = [IsThumb]; 733 } 734} 735 736// These require base address to be written back or one of the loaded regs. 737let neverHasSideEffects = 1 in { 738 739let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 740defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 741 {1,1,0,0,1,?}, 1, "tLDM">; 742 743let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 744defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 745 {1,1,0,0,0,?}, 0, "tSTM">; 746 747} // neverHasSideEffects 748 749let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 750def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 751 IIC_iPop, 752 "pop${p}\t$regs", []>, 753 T1Misc<{1,1,0,?,?,?,?}> { 754 bits<16> regs; 755 let Inst{8} = regs{15}; 756 let Inst{7-0} = regs{7-0}; 757} 758 759let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 760def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 761 IIC_iStore_m, 762 "push${p}\t$regs", []>, 763 T1Misc<{0,1,0,?,?,?,?}> { 764 bits<16> regs; 765 let Inst{8} = regs{14}; 766 let Inst{7-0} = regs{7-0}; 767} 768 769//===----------------------------------------------------------------------===// 770// Arithmetic Instructions. 771// 772 773// Helper classes for encoding T1pI patterns: 774class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 775 string opc, string asm, list<dag> pattern> 776 : T1pI<oops, iops, itin, opc, asm, pattern>, 777 T1DataProcessing<opA> { 778 bits<3> Rm; 779 bits<3> Rn; 780 let Inst{5-3} = Rm; 781 let Inst{2-0} = Rn; 782} 783class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 784 string opc, string asm, list<dag> pattern> 785 : T1pI<oops, iops, itin, opc, asm, pattern>, 786 T1Misc<opA> { 787 bits<3> Rm; 788 bits<3> Rd; 789 let Inst{5-3} = Rm; 790 let Inst{2-0} = Rd; 791} 792 793// Helper classes for encoding T1sI patterns: 794class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 795 string opc, string asm, list<dag> pattern> 796 : T1sI<oops, iops, itin, opc, asm, pattern>, 797 T1DataProcessing<opA> { 798 bits<3> Rd; 799 bits<3> Rn; 800 let Inst{5-3} = Rn; 801 let Inst{2-0} = Rd; 802} 803class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 804 string opc, string asm, list<dag> pattern> 805 : T1sI<oops, iops, itin, opc, asm, pattern>, 806 T1General<opA> { 807 bits<3> Rm; 808 bits<3> Rn; 809 bits<3> Rd; 810 let Inst{8-6} = Rm; 811 let Inst{5-3} = Rn; 812 let Inst{2-0} = Rd; 813} 814class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 815 string opc, string asm, list<dag> pattern> 816 : T1sI<oops, iops, itin, opc, asm, pattern>, 817 T1General<opA> { 818 bits<3> Rd; 819 bits<3> Rm; 820 let Inst{5-3} = Rm; 821 let Inst{2-0} = Rd; 822} 823 824// Helper classes for encoding T1sIt patterns: 825class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 826 string opc, string asm, list<dag> pattern> 827 : T1sIt<oops, iops, itin, opc, asm, pattern>, 828 T1DataProcessing<opA> { 829 bits<3> Rdn; 830 bits<3> Rm; 831 let Inst{5-3} = Rm; 832 let Inst{2-0} = Rdn; 833} 834class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 835 string opc, string asm, list<dag> pattern> 836 : T1sIt<oops, iops, itin, opc, asm, pattern>, 837 T1General<opA> { 838 bits<3> Rdn; 839 bits<8> imm8; 840 let Inst{10-8} = Rdn; 841 let Inst{7-0} = imm8; 842} 843 844// Add with carry register 845let isCommutable = 1, Uses = [CPSR] in 846def tADC : // A8.6.2 847 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 848 "adc", "\t$Rdn, $Rm", 849 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>; 850 851// Add immediate 852def tADDi3 : // A8.6.4 T1 853 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), 854 IIC_iALUi, 855 "add", "\t$Rd, $Rm, $imm3", 856 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> { 857 bits<3> imm3; 858 let Inst{8-6} = imm3; 859} 860 861def tADDi8 : // A8.6.4 T2 862 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), 863 IIC_iALUi, 864 "add", "\t$Rdn, $imm8", 865 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>; 866 867// Add register 868let isCommutable = 1 in 869def tADDrr : // A8.6.6 T1 870 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 871 IIC_iALUr, 872 "add", "\t$Rd, $Rn, $Rm", 873 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>; 874 875let neverHasSideEffects = 1 in 876def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 877 "add", "\t$Rdn, $Rm", []>, 878 T1Special<{0,0,?,?}> { 879 // A8.6.6 T2 880 bits<4> Rdn; 881 bits<4> Rm; 882 let Inst{7} = Rdn{3}; 883 let Inst{6-3} = Rm; 884 let Inst{2-0} = Rdn{2-0}; 885} 886 887// AND register 888let isCommutable = 1 in 889def tAND : // A8.6.12 890 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 891 IIC_iBITr, 892 "and", "\t$Rdn, $Rm", 893 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>; 894 895// ASR immediate 896def tASRri : // A8.6.14 897 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), 898 IIC_iMOVsi, 899 "asr", "\t$Rd, $Rm, $imm5", 900 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> { 901 bits<5> imm5; 902 let Inst{10-6} = imm5; 903} 904 905// ASR register 906def tASRrr : // A8.6.15 907 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 908 IIC_iMOVsr, 909 "asr", "\t$Rdn, $Rm", 910 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>; 911 912// BIC register 913def tBIC : // A8.6.20 914 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 915 IIC_iBITr, 916 "bic", "\t$Rdn, $Rm", 917 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>; 918 919// CMN register 920let isCompare = 1, Defs = [CPSR] in { 921//FIXME: Disable CMN, as CCodes are backwards from compare expectations 922// Compare-to-zero still works out, just not the relationals 923//def tCMN : // A8.6.33 924// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 925// IIC_iCMPr, 926// "cmn", "\t$lhs, $rhs", 927// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 928 929def tCMNz : // A8.6.33 930 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 931 IIC_iCMPr, 932 "cmn", "\t$Rn, $Rm", 933 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>; 934 935} // isCompare = 1, Defs = [CPSR] 936 937// CMP immediate 938let isCompare = 1, Defs = [CPSR] in { 939def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi, 940 "cmp", "\t$Rn, $imm8", 941 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 942 T1General<{1,0,1,?,?}> { 943 // A8.6.35 944 bits<3> Rn; 945 bits<8> imm8; 946 let Inst{10-8} = Rn; 947 let Inst{7-0} = imm8; 948} 949 950// CMP register 951def tCMPr : // A8.6.36 T1 952 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 953 IIC_iCMPr, 954 "cmp", "\t$Rn, $Rm", 955 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>; 956 957def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 958 "cmp", "\t$Rn, $Rm", []>, 959 T1Special<{0,1,?,?}> { 960 // A8.6.36 T2 961 bits<4> Rm; 962 bits<4> Rn; 963 let Inst{7} = Rn{3}; 964 let Inst{6-3} = Rm; 965 let Inst{2-0} = Rn{2-0}; 966} 967} // isCompare = 1, Defs = [CPSR] 968 969 970// XOR register 971let isCommutable = 1 in 972def tEOR : // A8.6.45 973 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 974 IIC_iBITr, 975 "eor", "\t$Rdn, $Rm", 976 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>; 977 978// LSL immediate 979def tLSLri : // A8.6.88 980 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), 981 IIC_iMOVsi, 982 "lsl", "\t$Rd, $Rm, $imm5", 983 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> { 984 bits<5> imm5; 985 let Inst{10-6} = imm5; 986} 987 988// LSL register 989def tLSLrr : // A8.6.89 990 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 991 IIC_iMOVsr, 992 "lsl", "\t$Rdn, $Rm", 993 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>; 994 995// LSR immediate 996def tLSRri : // A8.6.90 997 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), 998 IIC_iMOVsi, 999 "lsr", "\t$Rd, $Rm, $imm5", 1000 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> { 1001 bits<5> imm5; 1002 let Inst{10-6} = imm5; 1003} 1004 1005// LSR register 1006def tLSRrr : // A8.6.91 1007 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1008 IIC_iMOVsr, 1009 "lsr", "\t$Rdn, $Rm", 1010 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>; 1011 1012// Move register 1013let isMoveImm = 1 in 1014def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1015 "mov", "\t$Rd, $imm8", 1016 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1017 T1General<{1,0,0,?,?}> { 1018 // A8.6.96 1019 bits<3> Rd; 1020 bits<8> imm8; 1021 let Inst{10-8} = Rd; 1022 let Inst{7-0} = imm8; 1023} 1024 1025// A7-73: MOV(2) - mov setting flag. 1026 1027let neverHasSideEffects = 1 in { 1028def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1029 2, IIC_iMOVr, 1030 "mov", "\t$Rd, $Rm", "", []>, 1031 T1Special<{1,0,?,?}> { 1032 // A8.6.97 1033 bits<4> Rd; 1034 bits<4> Rm; 1035 let Inst{7} = Rd{3}; 1036 let Inst{6-3} = Rm; 1037 let Inst{2-0} = Rd{2-0}; 1038} 1039let Defs = [CPSR] in 1040def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1041 "movs\t$Rd, $Rm", []>, Encoding16 { 1042 // A8.6.97 1043 bits<3> Rd; 1044 bits<3> Rm; 1045 let Inst{15-6} = 0b0000000000; 1046 let Inst{5-3} = Rm; 1047 let Inst{2-0} = Rd; 1048} 1049} // neverHasSideEffects 1050 1051// Multiply register 1052let isCommutable = 1 in 1053def tMUL : // A8.6.105 T1 1054 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1055 IIC_iMUL32, 1056 "mul", "\t$Rdn, $Rm, $Rdn", 1057 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>; 1058 1059// Move inverse register 1060def tMVN : // A8.6.107 1061 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1062 "mvn", "\t$Rd, $Rn", 1063 [(set tGPR:$Rd, (not tGPR:$Rn))]>; 1064 1065// Bitwise or register 1066let isCommutable = 1 in 1067def tORR : // A8.6.114 1068 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1069 IIC_iBITr, 1070 "orr", "\t$Rdn, $Rm", 1071 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>; 1072 1073// Swaps 1074def tREV : // A8.6.134 1075 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1076 IIC_iUNAr, 1077 "rev", "\t$Rd, $Rm", 1078 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1079 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1080 1081def tREV16 : // A8.6.135 1082 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1083 IIC_iUNAr, 1084 "rev16", "\t$Rd, $Rm", 1085 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1086 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1087 1088def tREVSH : // A8.6.136 1089 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1090 IIC_iUNAr, 1091 "revsh", "\t$Rd, $Rm", 1092 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1093 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1094 1095// Rotate right register 1096def tROR : // A8.6.139 1097 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1098 IIC_iMOVsr, 1099 "ror", "\t$Rdn, $Rm", 1100 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>; 1101 1102// Negate register 1103def tRSB : // A8.6.141 1104 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1105 IIC_iALUi, 1106 "rsb", "\t$Rd, $Rn, #0", 1107 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>; 1108 1109// Subtract with carry register 1110let Uses = [CPSR] in 1111def tSBC : // A8.6.151 1112 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1113 IIC_iALUr, 1114 "sbc", "\t$Rdn, $Rm", 1115 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>; 1116 1117// Subtract immediate 1118def tSUBi3 : // A8.6.210 T1 1119 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), 1120 IIC_iALUi, 1121 "sub", "\t$Rd, $Rm, $imm3", 1122 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> { 1123 bits<3> imm3; 1124 let Inst{8-6} = imm3; 1125} 1126 1127def tSUBi8 : // A8.6.210 T2 1128 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), 1129 IIC_iALUi, 1130 "sub", "\t$Rdn, $imm8", 1131 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>; 1132 1133// Subtract register 1134def tSUBrr : // A8.6.212 1135 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1136 IIC_iALUr, 1137 "sub", "\t$Rd, $Rn, $Rm", 1138 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>; 1139 1140// TODO: A7-96: STMIA - store multiple. 1141 1142// Sign-extend byte 1143def tSXTB : // A8.6.222 1144 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1145 IIC_iUNAr, 1146 "sxtb", "\t$Rd, $Rm", 1147 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1148 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1149 1150// Sign-extend short 1151def tSXTH : // A8.6.224 1152 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1153 IIC_iUNAr, 1154 "sxth", "\t$Rd, $Rm", 1155 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1156 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1157 1158// Test 1159let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1160def tTST : // A8.6.230 1161 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1162 "tst", "\t$Rn, $Rm", 1163 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>; 1164 1165// Zero-extend byte 1166def tUXTB : // A8.6.262 1167 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1168 IIC_iUNAr, 1169 "uxtb", "\t$Rd, $Rm", 1170 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1171 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1172 1173// Zero-extend short 1174def tUXTH : // A8.6.264 1175 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1176 IIC_iUNAr, 1177 "uxth", "\t$Rd, $Rm", 1178 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1179 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1180 1181// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1182// Expanded after instruction selection into a branch sequence. 1183let usesCustomInserter = 1 in // Expanded after instruction selection. 1184 def tMOVCCr_pseudo : 1185 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 1186 NoItinerary, 1187 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 1188 1189// tLEApcrel - Load a pc-relative address into a register without offending the 1190// assembler. 1191 1192def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1193 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>, 1194 T1Encoding<{1,0,1,0,0,?}> { 1195 bits<3> Rd; 1196 bits<8> addr; 1197 let Inst{10-8} = Rd; 1198 let Inst{7-0} = addr; 1199} 1200 1201let neverHasSideEffects = 1, isReMaterializable = 1 in 1202def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1203 2, IIC_iALUi, []>; 1204 1205def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1206 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1207 2, IIC_iALUi, []>; 1208 1209//===----------------------------------------------------------------------===// 1210// TLS Instructions 1211// 1212 1213// __aeabi_read_tp preserves the registers r1-r3. 1214// This is a pseudo inst so that we can get the encoding right, 1215// complete with fixup for the aeabi_read_tp function. 1216let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1217def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1218 [(set R0, ARMthread_pointer)]>; 1219 1220//===----------------------------------------------------------------------===// 1221// SJLJ Exception handling intrinsics 1222// 1223 1224// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1225// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1226// from some other function to get here, and we're using the stack frame for the 1227// containing function to save/restore registers, we can't keep anything live in 1228// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1229// tromped upon when we get here from a longjmp(). We force everything out of 1230// registers except for our own input by listing the relevant registers in 1231// Defs. By doing so, we also cause the prologue/epilogue code to actively 1232// preserve all of the callee-saved resgisters, which is exactly what we want. 1233// $val is a scratch register for our use. 1234let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1235 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in 1236def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1237 AddrModeNone, 0, NoItinerary, "","", 1238 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1239 1240// FIXME: Non-Darwin version(s) 1241let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1242 Defs = [ R7, LR, SP ] in 1243def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1244 AddrModeNone, 0, IndexModeNone, 1245 Pseudo, NoItinerary, "", "", 1246 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1247 Requires<[IsThumb, IsDarwin]>; 1248 1249//===----------------------------------------------------------------------===// 1250// Non-Instruction Patterns 1251// 1252 1253// Comparisons 1254def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1255 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1256def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1257 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1258 1259// Add with carry 1260def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1261 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1262def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1263 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1264def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1265 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1266 1267// Subtract with carry 1268def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1269 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1270def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1271 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1272def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1273 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1274 1275// ConstantPool, GlobalAddress 1276def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 1277def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1278 1279// JumpTable 1280def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1281 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 1282 1283// Direct calls 1284def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1285 Requires<[IsThumb, IsNotDarwin]>; 1286def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>, 1287 Requires<[IsThumb, IsDarwin]>; 1288 1289def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1290 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 1291def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>, 1292 Requires<[IsThumb, HasV5T, IsDarwin]>; 1293 1294// Indirect calls to ARM routines 1295def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1296 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 1297def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>, 1298 Requires<[IsThumb, HasV5T, IsDarwin]>; 1299 1300// zextload i1 -> zextload i8 1301def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), 1302 (tLDRBr t_addrmode_rrs1:$addr)>; 1303def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1304 (tLDRBi t_addrmode_is1:$addr)>; 1305 1306// extload -> zextload 1307def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1308def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1309def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1310def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1311def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>; 1312def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1313 1314// If it's impossible to use [r,r] address mode for sextload, select to 1315// ldr{b|h} + sxt{b|h} instead. 1316def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1317 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1318 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1319def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1320 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>, 1321 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1322def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1323 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1324 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1325def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1326 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>, 1327 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1328 1329def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1330 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>; 1331def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1332 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1333def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1334 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>; 1335def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1336 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1337 1338// Large immediate handling. 1339 1340// Two piece imms. 1341def : T1Pat<(i32 thumb_immshifted:$src), 1342 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1343 (thumb_immshifted_shamt imm:$src))>; 1344 1345def : T1Pat<(i32 imm0_255_comp:$src), 1346 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1347 1348// Pseudo instruction that combines ldr from constpool and add pc. This should 1349// be expanded into two instructions late to allow if-conversion and 1350// scheduling. 1351let isReMaterializable = 1 in 1352def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1353 NoItinerary, 1354 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1355 imm:$cp))]>, 1356 Requires<[IsThumb, IsThumb1Only]>; 1357 1358// Pseudo-instruction for merged POP and return. 1359// FIXME: remove when we have a way to marking a MI with these properties. 1360let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1361 hasExtraDefRegAllocReq = 1 in 1362def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1363 2, IIC_iPop_Br, [], 1364 (tPOP pred:$p, reglist:$regs)>; 1365 1366// Indirect branch using "mov pc, $Rm" 1367let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1368 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1369 2, IIC_Br, [(brind GPR:$Rm)], 1370 (tMOVr PC, GPR:$Rm, pred:$p)>; 1371} 1372