ARMInstrThumb.td revision f1f6dcefa8c445fa6bd2bba3d72a3e6adff16ca1
1//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22def imm_sr_XFORM: SDNodeXForm<imm, [{ 23 unsigned Imm = N->getZExtValue(); 24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32); 25}]>; 26def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 27def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 28 uint64_t Imm = N->getZExtValue(); 29 return Imm > 0 && Imm <= 32; 30}], imm_sr_XFORM> { 31 let PrintMethod = "printThumbSRImm"; 32 let ParserMatchClass = ThumbSRImmAsmOperand; 33} 34 35def imm_comp_XFORM : SDNodeXForm<imm, [{ 36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 37}]>; 38 39def imm0_7_neg : PatLeaf<(i32 imm), [{ 40 return (uint32_t)-N->getZExtValue() < 8; 41}], imm_neg_XFORM>; 42 43def imm0_255_comp : PatLeaf<(i32 imm), [{ 44 return ~((uint32_t)N->getZExtValue()) < 256; 45}]>; 46 47def imm8_255 : ImmLeaf<i32, [{ 48 return Imm >= 8 && Imm < 256; 49}]>; 50def imm8_255_neg : PatLeaf<(i32 imm), [{ 51 unsigned Val = -N->getZExtValue(); 52 return Val >= 8 && Val < 256; 53}], imm_neg_XFORM>; 54 55// Break imm's up into two pieces: an immediate + a left shift. This uses 56// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 57// to get the val/shift pieces. 58def thumb_immshifted : PatLeaf<(imm), [{ 59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 60}]>; 61 62def thumb_immshifted_val : SDNodeXForm<imm, [{ 63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 64 return CurDAG->getTargetConstant(V, MVT::i32); 65}]>; 66 67def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 69 return CurDAG->getTargetConstant(V, MVT::i32); 70}]>; 71 72// ADR instruction labels. 73def t_adrlabel : Operand<i32> { 74 let EncoderMethod = "getThumbAdrLabelOpValue"; 75} 76 77// Scaled 4 immediate. 78def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 79def t_imm0_1020s4 : Operand<i32> { 80 let PrintMethod = "printThumbS4ImmOperand"; 81 let ParserMatchClass = t_imm0_1020s4_asmoperand; 82 let OperandType = "OPERAND_IMMEDIATE"; 83} 84 85def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 86def t_imm0_508s4 : Operand<i32> { 87 let PrintMethod = "printThumbS4ImmOperand"; 88 let ParserMatchClass = t_imm0_508s4_asmoperand; 89 let OperandType = "OPERAND_IMMEDIATE"; 90} 91// Alias use only, so no printer is necessary. 92def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 93def t_imm0_508s4_neg : Operand<i32> { 94 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 95 let OperandType = "OPERAND_IMMEDIATE"; 96} 97 98// Define Thumb specific addressing modes. 99 100let OperandType = "OPERAND_PCREL" in { 101def t_brtarget : Operand<OtherVT> { 102 let EncoderMethod = "getThumbBRTargetOpValue"; 103 let DecoderMethod = "DecodeThumbBROperand"; 104} 105 106def t_bcctarget : Operand<i32> { 107 let EncoderMethod = "getThumbBCCTargetOpValue"; 108 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 109} 110 111def t_cbtarget : Operand<i32> { 112 let EncoderMethod = "getThumbCBTargetOpValue"; 113 let DecoderMethod = "DecodeThumbCmpBROperand"; 114} 115 116def t_bltarget : Operand<i32> { 117 let EncoderMethod = "getThumbBLTargetOpValue"; 118 let DecoderMethod = "DecodeThumbBLTargetOperand"; 119} 120 121def t_blxtarget : Operand<i32> { 122 let EncoderMethod = "getThumbBLXTargetOpValue"; 123 let DecoderMethod = "DecodeThumbBLXOffset"; 124} 125} 126 127// t_addrmode_rr := reg + reg 128// 129def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 130def t_addrmode_rr : Operand<i32>, 131 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 132 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 133 let PrintMethod = "printThumbAddrModeRROperand"; 134 let DecoderMethod = "DecodeThumbAddrModeRR"; 135 let ParserMatchClass = t_addrmode_rr_asm_operand; 136 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 137} 138 139// t_addrmode_rrs := reg + reg 140// 141// We use separate scaled versions because the Select* functions need 142// to explicitly check for a matching constant and return false here so that 143// the reg+imm forms will match instead. This is a horrible way to do that, 144// as it forces tight coupling between the methods, but it's how selectiondag 145// currently works. 146def t_addrmode_rrs1 : Operand<i32>, 147 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 148 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 149 let PrintMethod = "printThumbAddrModeRROperand"; 150 let DecoderMethod = "DecodeThumbAddrModeRR"; 151 let ParserMatchClass = t_addrmode_rr_asm_operand; 152 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 153} 154def t_addrmode_rrs2 : Operand<i32>, 155 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 156 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 157 let DecoderMethod = "DecodeThumbAddrModeRR"; 158 let PrintMethod = "printThumbAddrModeRROperand"; 159 let ParserMatchClass = t_addrmode_rr_asm_operand; 160 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 161} 162def t_addrmode_rrs4 : Operand<i32>, 163 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 164 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 165 let DecoderMethod = "DecodeThumbAddrModeRR"; 166 let PrintMethod = "printThumbAddrModeRROperand"; 167 let ParserMatchClass = t_addrmode_rr_asm_operand; 168 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 169} 170 171// t_addrmode_is4 := reg + imm5 * 4 172// 173def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 174def t_addrmode_is4 : Operand<i32>, 175 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 176 let EncoderMethod = "getAddrModeISOpValue"; 177 let DecoderMethod = "DecodeThumbAddrModeIS"; 178 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 179 let ParserMatchClass = t_addrmode_is4_asm_operand; 180 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 181} 182 183// t_addrmode_is2 := reg + imm5 * 2 184// 185def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 186def t_addrmode_is2 : Operand<i32>, 187 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 188 let EncoderMethod = "getAddrModeISOpValue"; 189 let DecoderMethod = "DecodeThumbAddrModeIS"; 190 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 191 let ParserMatchClass = t_addrmode_is2_asm_operand; 192 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 193} 194 195// t_addrmode_is1 := reg + imm5 196// 197def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 198def t_addrmode_is1 : Operand<i32>, 199 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 200 let EncoderMethod = "getAddrModeISOpValue"; 201 let DecoderMethod = "DecodeThumbAddrModeIS"; 202 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 203 let ParserMatchClass = t_addrmode_is1_asm_operand; 204 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 205} 206 207// t_addrmode_sp := sp + imm8 * 4 208// 209// FIXME: This really shouldn't have an explicit SP operand at all. It should 210// be implicit, just like in the instruction encoding itself. 211def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 212def t_addrmode_sp : Operand<i32>, 213 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 214 let EncoderMethod = "getAddrModeThumbSPOpValue"; 215 let DecoderMethod = "DecodeThumbAddrModeSP"; 216 let PrintMethod = "printThumbAddrModeSPOperand"; 217 let ParserMatchClass = t_addrmode_sp_asm_operand; 218 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 219} 220 221// t_addrmode_pc := <label> => pc + imm8 * 4 222// 223def t_addrmode_pc : Operand<i32> { 224 let EncoderMethod = "getAddrModePCOpValue"; 225 let DecoderMethod = "DecodeThumbAddrModePC"; 226 let PrintMethod = "printThumbLdrLabelOperand"; 227} 228 229//===----------------------------------------------------------------------===// 230// Miscellaneous Instructions. 231// 232 233// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 234// from removing one half of the matched pairs. That breaks PEI, which assumes 235// these will always be in pairs, and asserts if it finds otherwise. Better way? 236let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 237def tADJCALLSTACKUP : 238 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 239 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 240 Requires<[IsThumb, IsThumb1Only]>; 241 242def tADJCALLSTACKDOWN : 243 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 244 [(ARMcallseq_start imm:$amt)]>, 245 Requires<[IsThumb, IsThumb1Only]>; 246} 247 248class T1SystemEncoding<bits<8> opc> 249 : T1Encoding<0b101111> { 250 let Inst{9-8} = 0b11; 251 let Inst{7-0} = opc; 252} 253 254def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>, 255 T1SystemEncoding<0x00>, // A8.6.110 256 Requires<[IsThumb2]>; 257 258def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>, 259 T1SystemEncoding<0x10>, // A8.6.410 260 Requires<[IsThumb2]>; 261 262def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>, 263 T1SystemEncoding<0x20>, // A8.6.408 264 Requires<[IsThumb2]>; 265 266def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>, 267 T1SystemEncoding<0x30>, // A8.6.409 268 Requires<[IsThumb2]>; 269 270def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>, 271 T1SystemEncoding<0x40>, // A8.6.157 272 Requires<[IsThumb2]>; 273 274// The imm operand $val can be used by a debugger to store more information 275// about the breakpoint. 276def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 277 []>, 278 T1Encoding<0b101111> { 279 let Inst{9-8} = 0b10; 280 // A8.6.22 281 bits<8> val; 282 let Inst{7-0} = val; 283} 284 285def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 286 []>, T1Encoding<0b101101> { 287 bits<1> end; 288 // A8.6.156 289 let Inst{9-5} = 0b10010; 290 let Inst{4} = 1; 291 let Inst{3} = end; 292 let Inst{2-0} = 0b000; 293} 294 295// Change Processor State is a system instruction -- for disassembly only. 296def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 297 NoItinerary, "cps$imod $iflags", []>, 298 T1Misc<0b0110011> { 299 // A8.6.38 & B6.1.1 300 bit imod; 301 bits<3> iflags; 302 303 let Inst{4} = imod; 304 let Inst{3} = 0; 305 let Inst{2-0} = iflags; 306 let DecoderMethod = "DecodeThumbCPS"; 307} 308 309// For both thumb1 and thumb2. 310let isNotDuplicable = 1, isCodeGenOnly = 1 in 311def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 312 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 313 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 314 // A8.6.6 315 bits<3> dst; 316 let Inst{6-3} = 0b1111; // Rm = pc 317 let Inst{2-0} = dst; 318} 319 320// ADD <Rd>, sp, #<imm8> 321// FIXME: This should not be marked as having side effects, and it should be 322// rematerializable. Clearing the side effect bit causes miscompilations, 323// probably because the instruction can be moved around. 324def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 325 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 326 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> { 327 // A6.2 & A8.6.8 328 bits<3> dst; 329 bits<8> imm; 330 let Inst{10-8} = dst; 331 let Inst{7-0} = imm; 332 let DecoderMethod = "DecodeThumbAddSpecialReg"; 333} 334 335// ADD sp, sp, #<imm7> 336def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 337 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 338 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> { 339 // A6.2.5 & A8.6.8 340 bits<7> imm; 341 let Inst{6-0} = imm; 342 let DecoderMethod = "DecodeThumbAddSPImm"; 343} 344 345// SUB sp, sp, #<imm7> 346// FIXME: The encoding and the ASM string don't match up. 347def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 348 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 349 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> { 350 // A6.2.5 & A8.6.214 351 bits<7> imm; 352 let Inst{6-0} = imm; 353 let DecoderMethod = "DecodeThumbAddSPImm"; 354} 355 356def : tInstAlias<"add${p} sp, $imm", 357 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 358def : tInstAlias<"add${p} sp, sp, $imm", 359 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 360 361// Can optionally specify SP as a three operand instruction. 362def : tInstAlias<"add${p} sp, sp, $imm", 363 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 364def : tInstAlias<"sub${p} sp, sp, $imm", 365 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 366 367// ADD <Rm>, sp 368def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 369 "add", "\t$Rdn, $sp, $Rn", []>, 370 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 371 // A8.6.9 Encoding T1 372 bits<4> Rdn; 373 let Inst{7} = Rdn{3}; 374 let Inst{6-3} = 0b1101; 375 let Inst{2-0} = Rdn{2-0}; 376 let DecoderMethod = "DecodeThumbAddSPReg"; 377} 378 379// ADD sp, <Rm> 380def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 381 "add", "\t$Rdn, $Rm", []>, 382 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 383 // A8.6.9 Encoding T2 384 bits<4> Rm; 385 let Inst{7} = 1; 386 let Inst{6-3} = Rm; 387 let Inst{2-0} = 0b101; 388 let DecoderMethod = "DecodeThumbAddSPReg"; 389} 390 391//===----------------------------------------------------------------------===// 392// Control Flow Instructions. 393// 394 395// Indirect branches 396let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 397 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 398 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 399 // A6.2.3 & A8.6.25 400 bits<4> Rm; 401 let Inst{6-3} = Rm; 402 let Inst{2-0} = 0b000; 403 let Unpredictable{2-0} = 0b111; 404 } 405} 406 407let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 408 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 409 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>; 410 411 // Alternative return instruction used by vararg functions. 412 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 413 2, IIC_Br, [], 414 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 415} 416 417// All calls clobber the non-callee saved registers. SP is marked as a use to 418// prevent stack-pointer assignments that appear immediately before calls from 419// potentially appearing dead. 420let isCall = 1, 421 Defs = [LR], Uses = [SP] in { 422 // Also used for Thumb2 423 def tBL : TIx2<0b11110, 0b11, 1, 424 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br, 425 "bl${p}\t$func", 426 [(ARMtcall tglobaladdr:$func)]>, 427 Requires<[IsThumb]>, Sched<[WriteBrL]> { 428 bits<24> func; 429 let Inst{26} = func{23}; 430 let Inst{25-16} = func{20-11}; 431 let Inst{13} = func{22}; 432 let Inst{11} = func{21}; 433 let Inst{10-0} = func{10-0}; 434 } 435 436 // ARMv5T and above, also used for Thumb2 437 def tBLXi : TIx2<0b11110, 0b11, 0, 438 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br, 439 "blx${p}\t$func", 440 [(ARMcall tglobaladdr:$func)]>, 441 Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> { 442 bits<24> func; 443 let Inst{26} = func{23}; 444 let Inst{25-16} = func{20-11}; 445 let Inst{13} = func{22}; 446 let Inst{11} = func{21}; 447 let Inst{10-1} = func{10-1}; 448 let Inst{0} = 0; // func{0} is assumed zero 449 } 450 451 // Also used for Thumb2 452 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 453 "blx${p}\t$func", 454 [(ARMtcall GPR:$func)]>, 455 Requires<[IsThumb, HasV5T]>, 456 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24; 457 bits<4> func; 458 let Inst{6-3} = func; 459 let Inst{2-0} = 0b000; 460 } 461 462 // ARMv4T 463 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 464 4, IIC_Br, 465 [(ARMcall_nolink tGPR:$func)]>, 466 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>; 467} 468 469let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 470 let isPredicable = 1 in 471 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 472 "b", "\t$target", [(br bb:$target)]>, 473 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> { 474 bits<11> target; 475 let Inst{10-0} = target; 476 } 477 478 // Far jump 479 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 480 // the clobber of LR. 481 let Defs = [LR] in 482 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), 483 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>, 484 Sched<[WriteBrTbl]>; 485 486 def tBR_JTr : tPseudoInst<(outs), 487 (ins tGPR:$target, i32imm:$jt, i32imm:$id), 488 0, IIC_Br, 489 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>, 490 Sched<[WriteBrTbl]> { 491 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 492 } 493} 494 495// FIXME: should be able to write a pattern for ARMBrcond, but can't use 496// a two-value operand where a dag node expects two operands. :( 497let isBranch = 1, isTerminator = 1 in 498 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 499 "b${p}\t$target", 500 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 501 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> { 502 bits<4> p; 503 bits<8> target; 504 let Inst{11-8} = p; 505 let Inst{7-0} = target; 506} 507 508// Tail calls 509let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 510 // IOS versions. 511 let Uses = [SP] in { 512 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 513 4, IIC_Br, [], 514 (tBX GPR:$dst, (ops 14, zero_reg))>, 515 Requires<[IsThumb]>, Sched<[WriteBr]>; 516 } 517 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls 518 // on IOS), so it's in ARMInstrThumb2.td. 519 // Non-IOS version: 520 let Uses = [SP] in { 521 def tTAILJMPdND : tPseudoExpand<(outs), 522 (ins t_brtarget:$dst, pred:$p), 523 4, IIC_Br, [], 524 (tB t_brtarget:$dst, pred:$p)>, 525 Requires<[IsThumb, IsNotIOS]>, Sched<[WriteBr]>; 526 } 527} 528 529 530// A8.6.218 Supervisor Call (Software Interrupt) 531// A8.6.16 B: Encoding T1 532// If Inst{11-8} == 0b1111 then SEE SVC 533let isCall = 1, Uses = [SP] in 534def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 535 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> { 536 bits<8> imm; 537 let Inst{15-12} = 0b1101; 538 let Inst{11-8} = 0b1111; 539 let Inst{7-0} = imm; 540} 541 542// The assembler uses 0xDEFE for a trap instruction. 543let isBarrier = 1, isTerminator = 1 in 544def tTRAP : TI<(outs), (ins), IIC_Br, 545 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> { 546 let Inst = 0xdefe; 547} 548 549//===----------------------------------------------------------------------===// 550// Load Store Instructions. 551// 552 553// Loads: reg/reg and reg/imm5 554let canFoldAsLoad = 1, isReMaterializable = 1 in 555multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 556 Operand AddrMode_r, Operand AddrMode_i, 557 AddrMode am, InstrItinClass itin_r, 558 InstrItinClass itin_i, string asm, 559 PatFrag opnode> { 560 def r : // reg/reg 561 T1pILdStEncode<reg_opc, 562 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 563 am, itin_r, asm, "\t$Rt, $addr", 564 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 565 def i : // reg/imm5 566 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 567 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 568 am, itin_i, asm, "\t$Rt, $addr", 569 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 570} 571// Stores: reg/reg and reg/imm5 572multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 573 Operand AddrMode_r, Operand AddrMode_i, 574 AddrMode am, InstrItinClass itin_r, 575 InstrItinClass itin_i, string asm, 576 PatFrag opnode> { 577 def r : // reg/reg 578 T1pILdStEncode<reg_opc, 579 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 580 am, itin_r, asm, "\t$Rt, $addr", 581 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 582 def i : // reg/imm5 583 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 584 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 585 am, itin_i, asm, "\t$Rt, $addr", 586 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 587} 588 589// A8.6.57 & A8.6.60 590defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4, 591 t_addrmode_is4, AddrModeT1_4, 592 IIC_iLoad_r, IIC_iLoad_i, "ldr", 593 UnOpFrag<(load node:$Src)>>; 594 595// A8.6.64 & A8.6.61 596defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1, 597 t_addrmode_is1, AddrModeT1_1, 598 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 599 UnOpFrag<(zextloadi8 node:$Src)>>; 600 601// A8.6.76 & A8.6.73 602defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2, 603 t_addrmode_is2, AddrModeT1_2, 604 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 605 UnOpFrag<(zextloadi16 node:$Src)>>; 606 607let AddedComplexity = 10 in 608def tLDRSB : // A8.6.80 609 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 610 AddrModeT1_1, IIC_iLoad_bh_r, 611 "ldrsb", "\t$Rt, $addr", 612 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 613 614let AddedComplexity = 10 in 615def tLDRSH : // A8.6.84 616 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 617 AddrModeT1_2, IIC_iLoad_bh_r, 618 "ldrsh", "\t$Rt, $addr", 619 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 620 621let canFoldAsLoad = 1 in 622def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 623 "ldr", "\t$Rt, $addr", 624 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 625 T1LdStSP<{1,?,?}> { 626 bits<3> Rt; 627 bits<8> addr; 628 let Inst{10-8} = Rt; 629 let Inst{7-0} = addr; 630} 631 632// Load tconstpool 633// FIXME: Use ldr.n to work around a darwin assembler bug. 634let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in 635def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 636 "ldr", ".n\t$Rt, $addr", 637 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 638 T1Encoding<{0,1,0,0,1,?}> { 639 // A6.2 & A8.6.59 640 bits<3> Rt; 641 bits<8> addr; 642 let Inst{10-8} = Rt; 643 let Inst{7-0} = addr; 644} 645 646// FIXME: Remove this entry when the above ldr.n workaround is fixed. 647// For assembly/disassembly use only. 648def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 649 "ldr", "\t$Rt, $addr", []>, 650 T1Encoding<{0,1,0,0,1,?}> { 651 // A6.2 & A8.6.59 652 bits<3> Rt; 653 bits<8> addr; 654 let Inst{10-8} = Rt; 655 let Inst{7-0} = addr; 656} 657 658// A8.6.194 & A8.6.192 659defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, 660 t_addrmode_is4, AddrModeT1_4, 661 IIC_iStore_r, IIC_iStore_i, "str", 662 BinOpFrag<(store node:$LHS, node:$RHS)>>; 663 664// A8.6.197 & A8.6.195 665defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1, 666 t_addrmode_is1, AddrModeT1_1, 667 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 668 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 669 670// A8.6.207 & A8.6.205 671defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2, 672 t_addrmode_is2, AddrModeT1_2, 673 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 674 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 675 676 677def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 678 "str", "\t$Rt, $addr", 679 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 680 T1LdStSP<{0,?,?}> { 681 bits<3> Rt; 682 bits<8> addr; 683 let Inst{10-8} = Rt; 684 let Inst{7-0} = addr; 685} 686 687//===----------------------------------------------------------------------===// 688// Load / store multiple Instructions. 689// 690 691// These require base address to be written back or one of the loaded regs. 692let neverHasSideEffects = 1 in { 693 694let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 695def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 696 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 697 bits<3> Rn; 698 bits<8> regs; 699 let Inst{10-8} = Rn; 700 let Inst{7-0} = regs; 701} 702 703// Writeback version is just a pseudo, as there's no encoding difference. 704// Writeback happens iff the base register is not in the destination register 705// list. 706def tLDMIA_UPD : 707 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 708 "$Rn = $wb", IIC_iLoad_mu>, 709 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 710 let Size = 2; 711 let OutOperandList = (outs GPR:$wb); 712 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 713 let Pattern = []; 714 let isCodeGenOnly = 1; 715 let isPseudo = 1; 716 list<Predicate> Predicates = [IsThumb]; 717} 718 719// There is no non-writeback version of STM for Thumb. 720let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 721def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 722 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 723 AddrModeNone, 2, IIC_iStore_mu, 724 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 725 T1Encoding<{1,1,0,0,0,?}> { 726 bits<3> Rn; 727 bits<8> regs; 728 let Inst{10-8} = Rn; 729 let Inst{7-0} = regs; 730} 731 732} // neverHasSideEffects 733 734def : InstAlias<"ldm${p} $Rn!, $regs", 735 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, 736 Requires<[IsThumb, IsThumb1Only]>; 737 738let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 739def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 740 IIC_iPop, 741 "pop${p}\t$regs", []>, 742 T1Misc<{1,1,0,?,?,?,?}> { 743 bits<16> regs; 744 let Inst{8} = regs{15}; 745 let Inst{7-0} = regs{7-0}; 746} 747 748let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 749def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 750 IIC_iStore_m, 751 "push${p}\t$regs", []>, 752 T1Misc<{0,1,0,?,?,?,?}> { 753 bits<16> regs; 754 let Inst{8} = regs{14}; 755 let Inst{7-0} = regs{7-0}; 756} 757 758//===----------------------------------------------------------------------===// 759// Arithmetic Instructions. 760// 761 762// Helper classes for encoding T1pI patterns: 763class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 764 string opc, string asm, list<dag> pattern> 765 : T1pI<oops, iops, itin, opc, asm, pattern>, 766 T1DataProcessing<opA> { 767 bits<3> Rm; 768 bits<3> Rn; 769 let Inst{5-3} = Rm; 770 let Inst{2-0} = Rn; 771} 772class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 773 string opc, string asm, list<dag> pattern> 774 : T1pI<oops, iops, itin, opc, asm, pattern>, 775 T1Misc<opA> { 776 bits<3> Rm; 777 bits<3> Rd; 778 let Inst{5-3} = Rm; 779 let Inst{2-0} = Rd; 780} 781 782// Helper classes for encoding T1sI patterns: 783class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 784 string opc, string asm, list<dag> pattern> 785 : T1sI<oops, iops, itin, opc, asm, pattern>, 786 T1DataProcessing<opA> { 787 bits<3> Rd; 788 bits<3> Rn; 789 let Inst{5-3} = Rn; 790 let Inst{2-0} = Rd; 791} 792class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 793 string opc, string asm, list<dag> pattern> 794 : T1sI<oops, iops, itin, opc, asm, pattern>, 795 T1General<opA> { 796 bits<3> Rm; 797 bits<3> Rn; 798 bits<3> Rd; 799 let Inst{8-6} = Rm; 800 let Inst{5-3} = Rn; 801 let Inst{2-0} = Rd; 802} 803class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 804 string opc, string asm, list<dag> pattern> 805 : T1sI<oops, iops, itin, opc, asm, pattern>, 806 T1General<opA> { 807 bits<3> Rd; 808 bits<3> Rm; 809 let Inst{5-3} = Rm; 810 let Inst{2-0} = Rd; 811} 812 813// Helper classes for encoding T1sIt patterns: 814class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 815 string opc, string asm, list<dag> pattern> 816 : T1sIt<oops, iops, itin, opc, asm, pattern>, 817 T1DataProcessing<opA> { 818 bits<3> Rdn; 819 bits<3> Rm; 820 let Inst{5-3} = Rm; 821 let Inst{2-0} = Rdn; 822} 823class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 824 string opc, string asm, list<dag> pattern> 825 : T1sIt<oops, iops, itin, opc, asm, pattern>, 826 T1General<opA> { 827 bits<3> Rdn; 828 bits<8> imm8; 829 let Inst{10-8} = Rdn; 830 let Inst{7-0} = imm8; 831} 832 833// Add with carry register 834let isCommutable = 1, Uses = [CPSR] in 835def tADC : // A8.6.2 836 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 837 "adc", "\t$Rdn, $Rm", 838 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 839 840// Add immediate 841def tADDi3 : // A8.6.4 T1 842 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 843 IIC_iALUi, 844 "add", "\t$Rd, $Rm, $imm3", 845 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>, 846 Sched<[WriteALU]> { 847 bits<3> imm3; 848 let Inst{8-6} = imm3; 849} 850 851def tADDi8 : // A8.6.4 T2 852 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 853 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 854 "add", "\t$Rdn, $imm8", 855 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>, 856 Sched<[WriteALU]>; 857 858// Add register 859let isCommutable = 1 in 860def tADDrr : // A8.6.6 T1 861 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 862 IIC_iALUr, 863 "add", "\t$Rd, $Rn, $Rm", 864 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 865 866let neverHasSideEffects = 1 in 867def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 868 "add", "\t$Rdn, $Rm", []>, 869 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 870 // A8.6.6 T2 871 bits<4> Rdn; 872 bits<4> Rm; 873 let Inst{7} = Rdn{3}; 874 let Inst{6-3} = Rm; 875 let Inst{2-0} = Rdn{2-0}; 876} 877 878// AND register 879let isCommutable = 1 in 880def tAND : // A8.6.12 881 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 882 IIC_iBITr, 883 "and", "\t$Rdn, $Rm", 884 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 885 886// ASR immediate 887def tASRri : // A8.6.14 888 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 889 IIC_iMOVsi, 890 "asr", "\t$Rd, $Rm, $imm5", 891 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 892 Sched<[WriteALU]> { 893 bits<5> imm5; 894 let Inst{10-6} = imm5; 895} 896 897// ASR register 898def tASRrr : // A8.6.15 899 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 900 IIC_iMOVsr, 901 "asr", "\t$Rdn, $Rm", 902 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 903 904// BIC register 905def tBIC : // A8.6.20 906 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 907 IIC_iBITr, 908 "bic", "\t$Rdn, $Rm", 909 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>, 910 Sched<[WriteALU]>; 911 912// CMN register 913let isCompare = 1, Defs = [CPSR] in { 914//FIXME: Disable CMN, as CCodes are backwards from compare expectations 915// Compare-to-zero still works out, just not the relationals 916//def tCMN : // A8.6.33 917// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 918// IIC_iCMPr, 919// "cmn", "\t$lhs, $rhs", 920// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 921 922def tCMNz : // A8.6.33 923 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 924 IIC_iCMPr, 925 "cmn", "\t$Rn, $Rm", 926 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>; 927 928} // isCompare = 1, Defs = [CPSR] 929 930// CMP immediate 931let isCompare = 1, Defs = [CPSR] in { 932def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 933 "cmp", "\t$Rn, $imm8", 934 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 935 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> { 936 // A8.6.35 937 bits<3> Rn; 938 bits<8> imm8; 939 let Inst{10-8} = Rn; 940 let Inst{7-0} = imm8; 941} 942 943// CMP register 944def tCMPr : // A8.6.36 T1 945 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 946 IIC_iCMPr, 947 "cmp", "\t$Rn, $Rm", 948 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>; 949 950def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 951 "cmp", "\t$Rn, $Rm", []>, 952 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> { 953 // A8.6.36 T2 954 bits<4> Rm; 955 bits<4> Rn; 956 let Inst{7} = Rn{3}; 957 let Inst{6-3} = Rm; 958 let Inst{2-0} = Rn{2-0}; 959} 960} // isCompare = 1, Defs = [CPSR] 961 962 963// XOR register 964let isCommutable = 1 in 965def tEOR : // A8.6.45 966 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 967 IIC_iBITr, 968 "eor", "\t$Rdn, $Rm", 969 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 970 971// LSL immediate 972def tLSLri : // A8.6.88 973 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 974 IIC_iMOVsi, 975 "lsl", "\t$Rd, $Rm, $imm5", 976 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>, 977 Sched<[WriteALU]> { 978 bits<5> imm5; 979 let Inst{10-6} = imm5; 980} 981 982// LSL register 983def tLSLrr : // A8.6.89 984 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 985 IIC_iMOVsr, 986 "lsl", "\t$Rdn, $Rm", 987 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 988 989// LSR immediate 990def tLSRri : // A8.6.90 991 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 992 IIC_iMOVsi, 993 "lsr", "\t$Rd, $Rm, $imm5", 994 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 995 Sched<[WriteALU]> { 996 bits<5> imm5; 997 let Inst{10-6} = imm5; 998} 999 1000// LSR register 1001def tLSRrr : // A8.6.91 1002 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1003 IIC_iMOVsr, 1004 "lsr", "\t$Rdn, $Rm", 1005 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1006 1007// Move register 1008let isMoveImm = 1 in 1009def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1010 "mov", "\t$Rd, $imm8", 1011 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1012 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> { 1013 // A8.6.96 1014 bits<3> Rd; 1015 bits<8> imm8; 1016 let Inst{10-8} = Rd; 1017 let Inst{7-0} = imm8; 1018} 1019// Because we have an explicit tMOVSr below, we need an alias to handle 1020// the immediate "movs" form here. Blech. 1021def : tInstAlias <"movs $Rdn, $imm", 1022 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1023 1024// A7-73: MOV(2) - mov setting flag. 1025 1026let neverHasSideEffects = 1 in { 1027def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1028 2, IIC_iMOVr, 1029 "mov", "\t$Rd, $Rm", "", []>, 1030 T1Special<{1,0,?,?}>, Sched<[WriteALU]> { 1031 // A8.6.97 1032 bits<4> Rd; 1033 bits<4> Rm; 1034 let Inst{7} = Rd{3}; 1035 let Inst{6-3} = Rm; 1036 let Inst{2-0} = Rd{2-0}; 1037} 1038let Defs = [CPSR] in 1039def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1040 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> { 1041 // A8.6.97 1042 bits<3> Rd; 1043 bits<3> Rm; 1044 let Inst{15-6} = 0b0000000000; 1045 let Inst{5-3} = Rm; 1046 let Inst{2-0} = Rd; 1047} 1048} // neverHasSideEffects 1049 1050// Multiply register 1051let isCommutable = 1 in 1052def tMUL : // A8.6.105 T1 1053 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1054 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1055 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1056 T1DataProcessing<0b1101> { 1057 bits<3> Rd; 1058 bits<3> Rn; 1059 let Inst{5-3} = Rn; 1060 let Inst{2-0} = Rd; 1061 let AsmMatchConverter = "cvtThumbMultiply"; 1062} 1063 1064def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1065 pred:$p)>; 1066 1067// Move inverse register 1068def tMVN : // A8.6.107 1069 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1070 "mvn", "\t$Rd, $Rn", 1071 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>; 1072 1073// Bitwise or register 1074let isCommutable = 1 in 1075def tORR : // A8.6.114 1076 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1077 IIC_iBITr, 1078 "orr", "\t$Rdn, $Rm", 1079 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1080 1081// Swaps 1082def tREV : // A8.6.134 1083 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1084 IIC_iUNAr, 1085 "rev", "\t$Rd, $Rm", 1086 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1087 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1088 1089def tREV16 : // A8.6.135 1090 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1091 IIC_iUNAr, 1092 "rev16", "\t$Rd, $Rm", 1093 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1094 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1095 1096def tREVSH : // A8.6.136 1097 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1098 IIC_iUNAr, 1099 "revsh", "\t$Rd, $Rm", 1100 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1101 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1102 1103// Rotate right register 1104def tROR : // A8.6.139 1105 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1106 IIC_iMOVsr, 1107 "ror", "\t$Rdn, $Rm", 1108 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>, 1109 Sched<[WriteALU]>; 1110 1111// Negate register 1112def tRSB : // A8.6.141 1113 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1114 IIC_iALUi, 1115 "rsb", "\t$Rd, $Rn, #0", 1116 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>; 1117 1118// Subtract with carry register 1119let Uses = [CPSR] in 1120def tSBC : // A8.6.151 1121 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1122 IIC_iALUr, 1123 "sbc", "\t$Rdn, $Rm", 1124 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>, 1125 Sched<[WriteALU]>; 1126 1127// Subtract immediate 1128def tSUBi3 : // A8.6.210 T1 1129 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1130 IIC_iALUi, 1131 "sub", "\t$Rd, $Rm, $imm3", 1132 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>, 1133 Sched<[WriteALU]> { 1134 bits<3> imm3; 1135 let Inst{8-6} = imm3; 1136} 1137 1138def tSUBi8 : // A8.6.210 T2 1139 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1140 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1141 "sub", "\t$Rdn, $imm8", 1142 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>, 1143 Sched<[WriteALU]>; 1144 1145// Subtract register 1146def tSUBrr : // A8.6.212 1147 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1148 IIC_iALUr, 1149 "sub", "\t$Rd, $Rn, $Rm", 1150 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>, 1151 Sched<[WriteALU]>; 1152 1153// Sign-extend byte 1154def tSXTB : // A8.6.222 1155 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1156 IIC_iUNAr, 1157 "sxtb", "\t$Rd, $Rm", 1158 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1159 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1160 Sched<[WriteALU]>; 1161 1162// Sign-extend short 1163def tSXTH : // A8.6.224 1164 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1165 IIC_iUNAr, 1166 "sxth", "\t$Rd, $Rm", 1167 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1168 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1169 Sched<[WriteALU]>; 1170 1171// Test 1172let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1173def tTST : // A8.6.230 1174 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1175 "tst", "\t$Rn, $Rm", 1176 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>, 1177 Sched<[WriteALU]>; 1178 1179// Zero-extend byte 1180def tUXTB : // A8.6.262 1181 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1182 IIC_iUNAr, 1183 "uxtb", "\t$Rd, $Rm", 1184 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1185 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1186 Sched<[WriteALU]>; 1187 1188// Zero-extend short 1189def tUXTH : // A8.6.264 1190 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1191 IIC_iUNAr, 1192 "uxth", "\t$Rd, $Rm", 1193 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1194 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1195 1196// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1197// Expanded after instruction selection into a branch sequence. 1198let usesCustomInserter = 1 in // Expanded after instruction selection. 1199 def tMOVCCr_pseudo : 1200 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 1201 NoItinerary, 1202 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 1203 1204// tLEApcrel - Load a pc-relative address into a register without offending the 1205// assembler. 1206 1207def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1208 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1209 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> { 1210 bits<3> Rd; 1211 bits<8> addr; 1212 let Inst{10-8} = Rd; 1213 let Inst{7-0} = addr; 1214 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1215} 1216 1217let neverHasSideEffects = 1, isReMaterializable = 1 in 1218def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1219 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1220 1221let hasSideEffects = 1 in 1222def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1223 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1224 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1225 1226//===----------------------------------------------------------------------===// 1227// TLS Instructions 1228// 1229 1230// __aeabi_read_tp preserves the registers r1-r3. 1231// This is a pseudo inst so that we can get the encoding right, 1232// complete with fixup for the aeabi_read_tp function. 1233let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1234def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1235 [(set R0, ARMthread_pointer)]>, 1236 Sched<[WriteBr]>; 1237 1238//===----------------------------------------------------------------------===// 1239// SJLJ Exception handling intrinsics 1240// 1241 1242// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1243// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1244// from some other function to get here, and we're using the stack frame for the 1245// containing function to save/restore registers, we can't keep anything live in 1246// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1247// tromped upon when we get here from a longjmp(). We force everything out of 1248// registers except for our own input by listing the relevant registers in 1249// Defs. By doing so, we also cause the prologue/epilogue code to actively 1250// preserve all of the callee-saved resgisters, which is exactly what we want. 1251// $val is a scratch register for our use. 1252let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1253 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1254 usesCustomInserter = 1 in 1255def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1256 AddrModeNone, 0, NoItinerary, "","", 1257 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1258 1259// FIXME: Non-IOS version(s) 1260let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1261 Defs = [ R7, LR, SP ] in 1262def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1263 AddrModeNone, 0, IndexModeNone, 1264 Pseudo, NoItinerary, "", "", 1265 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1266 Requires<[IsThumb, IsIOS]>; 1267 1268//===----------------------------------------------------------------------===// 1269// Non-Instruction Patterns 1270// 1271 1272// Comparisons 1273def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1274 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1275def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1276 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1277 1278// Add with carry 1279def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1280 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1281def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1282 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1283def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1284 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1285 1286// Subtract with carry 1287def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1288 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1289def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1290 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1291def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1292 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1293 1294// ConstantPool, GlobalAddress 1295def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 1296def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1297 1298// JumpTable 1299def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1300 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 1301 1302// Direct calls 1303def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1304 Requires<[IsThumb]>; 1305 1306def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1307 Requires<[IsThumb, HasV5T]>; 1308 1309// Indirect calls to ARM routines 1310def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1311 Requires<[IsThumb, HasV5T]>; 1312 1313// zextload i1 -> zextload i8 1314def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), 1315 (tLDRBr t_addrmode_rrs1:$addr)>; 1316def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1317 (tLDRBi t_addrmode_is1:$addr)>; 1318 1319// extload -> zextload 1320def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1321def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1322def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1323def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1324def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>; 1325def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1326 1327// If it's impossible to use [r,r] address mode for sextload, select to 1328// ldr{b|h} + sxt{b|h} instead. 1329def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1330 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1331 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1332def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1333 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>, 1334 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1335def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1336 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1337 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1338def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1339 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>, 1340 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1341 1342def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1343 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>; 1344def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1345 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1346def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1347 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>; 1348def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1349 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1350 1351def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1352 (tLDRBi t_addrmode_is1:$src)>; 1353def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src), 1354 (tLDRBr t_addrmode_rrs1:$src)>; 1355def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1356 (tLDRHi t_addrmode_is2:$src)>; 1357def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src), 1358 (tLDRHr t_addrmode_rrs2:$src)>; 1359def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1360 (tLDRi t_addrmode_is4:$src)>; 1361def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src), 1362 (tLDRr t_addrmode_rrs4:$src)>; 1363def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1364 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1365def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val), 1366 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>; 1367def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1368 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1369def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val), 1370 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>; 1371def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1372 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1373def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val), 1374 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>; 1375 1376// Large immediate handling. 1377 1378// Two piece imms. 1379def : T1Pat<(i32 thumb_immshifted:$src), 1380 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1381 (thumb_immshifted_shamt imm:$src))>; 1382 1383def : T1Pat<(i32 imm0_255_comp:$src), 1384 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1385 1386// Pseudo instruction that combines ldr from constpool and add pc. This should 1387// be expanded into two instructions late to allow if-conversion and 1388// scheduling. 1389let isReMaterializable = 1 in 1390def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1391 NoItinerary, 1392 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1393 imm:$cp))]>, 1394 Requires<[IsThumb, IsThumb1Only]>; 1395 1396// Pseudo-instruction for merged POP and return. 1397// FIXME: remove when we have a way to marking a MI with these properties. 1398let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1399 hasExtraDefRegAllocReq = 1 in 1400def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1401 2, IIC_iPop_Br, [], 1402 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; 1403 1404// Indirect branch using "mov pc, $Rm" 1405let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1406 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1407 2, IIC_Br, [(brind GPR:$Rm)], 1408 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 1409} 1410 1411 1412// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1413// encoding is available on ARMv6K, but we don't differentiate that finely. 1414def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>; 1415 1416 1417// For round-trip assembly/disassembly, we have to handle a CPS instruction 1418// without any iflags. That's not, strictly speaking, valid syntax, but it's 1419// a useful extension and assembles to defined behaviour (the insn does 1420// nothing). 1421def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1422def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1423 1424// "neg" is and alias for "rsb rd, rn, #0" 1425def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1426 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1427 1428 1429// Implied destination operand forms for shifts. 1430def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1431 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1432def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1433 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1434def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1435 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1436