ARMInstrThumb.td revision fa5bd27fbe5188ca708ac0dda4f32d90505da9f5 
1//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Thumb specific DAG Nodes.
16//
17
18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
20                       SDNPVariadic]>;
21
22def imm_neg_XFORM : SDNodeXForm<imm, [{
23  return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24}]>;
25def imm_comp_XFORM : SDNodeXForm<imm, [{
26  return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
27}]>;
28
29/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30def imm0_7 : PatLeaf<(i32 imm), [{
31  return (uint32_t)N->getZExtValue() < 8;
32}]>;
33def imm0_7_neg : PatLeaf<(i32 imm), [{
34  return (uint32_t)-N->getZExtValue() < 8;
35}], imm_neg_XFORM>;
36
37def imm0_255 : PatLeaf<(i32 imm), [{
38  return (uint32_t)N->getZExtValue() < 256;
39}]>;
40def imm0_255_comp : PatLeaf<(i32 imm), [{
41  return ~((uint32_t)N->getZExtValue()) < 256;
42}]>;
43
44def imm8_255 : PatLeaf<(i32 imm), [{
45  return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
46}]>;
47def imm8_255_neg : PatLeaf<(i32 imm), [{
48  unsigned Val = -N->getZExtValue();
49  return Val >= 8 && Val < 256;
50}], imm_neg_XFORM>;
51
52// Break imm's up into two pieces: an immediate + a left shift. This uses
53// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
54// to get the val/shift pieces.
55def thumb_immshifted : PatLeaf<(imm), [{
56  return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
57}]>;
58
59def thumb_immshifted_val : SDNodeXForm<imm, [{
60  unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61  return CurDAG->getTargetConstant(V, MVT::i32);
62}]>;
63
64def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65  unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66  return CurDAG->getTargetConstant(V, MVT::i32);
67}]>;
68
69// ADR instruction labels.
70def t_adrlabel : Operand<i32> {
71  let EncoderMethod = "getThumbAdrLabelOpValue";
72}
73
74// Scaled 4 immediate.
75def t_imm_s4 : Operand<i32> {
76  let PrintMethod = "printThumbS4ImmOperand";
77}
78
79// Define Thumb specific addressing modes.
80
81def t_brtarget : Operand<OtherVT> {
82  let EncoderMethod = "getThumbBRTargetOpValue";
83}
84
85def t_bcctarget : Operand<i32> {
86  let EncoderMethod = "getThumbBCCTargetOpValue";
87}
88
89def t_cbtarget : Operand<i32> {
90  let EncoderMethod = "getThumbCBTargetOpValue";
91}
92
93def t_bltarget : Operand<i32> {
94  let EncoderMethod = "getThumbBLTargetOpValue";
95}
96
97def t_blxtarget : Operand<i32> {
98  let EncoderMethod = "getThumbBLXTargetOpValue";
99}
100
101def MemModeRegThumbAsmOperand : AsmOperandClass {
102  let Name = "MemModeRegThumb";
103  let SuperClasses = [];
104}
105
106def MemModeImmThumbAsmOperand : AsmOperandClass {
107  let Name = "MemModeImmThumb";
108  let SuperClasses = [];
109}
110
111// t_addrmode_rr := reg + reg
112//
113def t_addrmode_rr : Operand<i32>,
114                    ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
115  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
116  let PrintMethod = "printThumbAddrModeRROperand";
117  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
118}
119
120// t_addrmode_rrs := reg + reg
121//
122def t_addrmode_rrs1 : Operand<i32>,
123                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
124  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
125  let PrintMethod = "printThumbAddrModeRROperand";
126  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
127  let ParserMatchClass = MemModeRegThumbAsmOperand;
128}
129def t_addrmode_rrs2 : Operand<i32>,
130                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
131  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
132  let PrintMethod = "printThumbAddrModeRROperand";
133  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
134  let ParserMatchClass = MemModeRegThumbAsmOperand;
135}
136def t_addrmode_rrs4 : Operand<i32>,
137                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
138  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
139  let PrintMethod = "printThumbAddrModeRROperand";
140  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
141  let ParserMatchClass = MemModeRegThumbAsmOperand;
142}
143
144// t_addrmode_is4 := reg + imm5 * 4
145//
146def t_addrmode_is4 : Operand<i32>,
147                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
148  let EncoderMethod = "getAddrModeISOpValue";
149  let PrintMethod = "printThumbAddrModeImm5S4Operand";
150  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
151  let ParserMatchClass = MemModeImmThumbAsmOperand;
152}
153
154// t_addrmode_is2 := reg + imm5 * 2
155//
156def t_addrmode_is2 : Operand<i32>,
157                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
158  let EncoderMethod = "getAddrModeISOpValue";
159  let PrintMethod = "printThumbAddrModeImm5S2Operand";
160  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
161  let ParserMatchClass = MemModeImmThumbAsmOperand;
162}
163
164// t_addrmode_is1 := reg + imm5
165//
166def t_addrmode_is1 : Operand<i32>,
167                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
168  let EncoderMethod = "getAddrModeISOpValue";
169  let PrintMethod = "printThumbAddrModeImm5S1Operand";
170  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
171  let ParserMatchClass = MemModeImmThumbAsmOperand;
172}
173
174// t_addrmode_sp := sp + imm8 * 4
175//
176def t_addrmode_sp : Operand<i32>,
177                    ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
178  let EncoderMethod = "getAddrModeThumbSPOpValue";
179  let PrintMethod = "printThumbAddrModeSPOperand";
180  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
181  let ParserMatchClass = MemModeImmThumbAsmOperand;
182}
183
184// t_addrmode_pc := <label> => pc + imm8 * 4
185//
186def t_addrmode_pc : Operand<i32> {
187  let EncoderMethod = "getAddrModePCOpValue";
188  let ParserMatchClass = MemModeImmThumbAsmOperand;
189}
190
191//===----------------------------------------------------------------------===//
192//  Miscellaneous Instructions.
193//
194
195// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
196// from removing one half of the matched pairs. That breaks PEI, which assumes
197// these will always be in pairs, and asserts if it finds otherwise. Better way?
198let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
199def tADJCALLSTACKUP :
200  PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
201             [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
202            Requires<[IsThumb, IsThumb1Only]>;
203
204def tADJCALLSTACKDOWN :
205  PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
206             [(ARMcallseq_start imm:$amt)]>,
207            Requires<[IsThumb, IsThumb1Only]>;
208}
209
210// T1Disassembly - A simple class to make encoding some disassembly patterns
211// easier and less verbose.
212class T1Disassembly<bits<2> op1, bits<8> op2>
213  : T1Encoding<0b101111> {
214  let Inst{9-8} = op1;
215  let Inst{7-0} = op2;
216}
217
218def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
219                [/* For disassembly only; pattern left blank */]>,
220           T1Disassembly<0b11, 0x00>; // A8.6.110
221
222def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
223                  [/* For disassembly only; pattern left blank */]>,
224           T1Disassembly<0b11, 0x10>; // A8.6.410
225
226def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
227                [/* For disassembly only; pattern left blank */]>,
228           T1Disassembly<0b11, 0x20>; // A8.6.408
229
230def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
231                [/* For disassembly only; pattern left blank */]>,
232           T1Disassembly<0b11, 0x30>; // A8.6.409
233
234def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
235                [/* For disassembly only; pattern left blank */]>,
236           T1Disassembly<0b11, 0x40>; // A8.6.157
237
238// The i32imm operand $val can be used by a debugger to store more information
239// about the breakpoint.
240def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
241                [/* For disassembly only; pattern left blank */]>,
242           T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
243  // A8.6.22
244  bits<8> val;
245  let Inst{7-0} = val;
246}
247
248def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
249                    [/* For disassembly only; pattern left blank */]>,
250                T1Encoding<0b101101> {
251  // A8.6.156
252  let Inst{9-5} = 0b10010;
253  let Inst{4}   = 1;
254  let Inst{3}   = 1;            // Big-Endian
255  let Inst{2-0} = 0b000;
256}
257
258def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
259                    [/* For disassembly only; pattern left blank */]>,
260                T1Encoding<0b101101> {
261  // A8.6.156
262  let Inst{9-5} = 0b10010;
263  let Inst{4}   = 1;
264  let Inst{3}   = 0;            // Little-Endian
265  let Inst{2-0} = 0b000;
266}
267
268// Change Processor State is a system instruction -- for disassembly only.
269// The singleton $opt operand contains the following information:
270// 
271//   opt{4-0} = mode ==> don't care
272//   opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
273//   opt{8-6} = AIF from Inst{2-0}
274//   opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
275//
276// The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
277// CPS which has more options.
278def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
279              [/* For disassembly only; pattern left blank */]>,
280           T1Misc<0b0110011> {
281  // A8.6.38 & B6.1.1
282  let Inst{3} = 0;
283  // FIXME: Finish encoding.
284}
285
286// For both thumb1 and thumb2.
287let isNotDuplicable = 1, isCodeGenOnly = 1 in
288def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
289                  [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
290              T1Special<{0,0,?,?}> {
291  // A8.6.6
292  bits<3> dst;
293  let Inst{6-3} = 0b1111; // Rm = pc
294  let Inst{2-0} = dst;
295}
296
297// PC relative add (ADR).
298def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
299                   "add\t$dst, pc, $rhs", []>,
300               T1Encoding<{1,0,1,0,0,?}> {
301  // A6.2 & A8.6.10
302  bits<3> dst;
303  bits<8> rhs;
304  let Inst{10-8} = dst;
305  let Inst{7-0}  = rhs;
306}
307
308// ADD <Rd>, sp, #<imm8>
309// This is rematerializable, which is particularly useful for taking the
310// address of locals.
311let isReMaterializable = 1 in
312def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
313                   "add\t$dst, $sp, $rhs", []>,
314               T1Encoding<{1,0,1,0,1,?}> {
315  // A6.2 & A8.6.8
316  bits<3> dst;
317  bits<8> rhs;
318  let Inst{10-8} = dst;
319  let Inst{7-0}  = rhs;
320}
321
322// ADD sp, sp, #<imm7>
323def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
324                  "add\t$dst, $rhs", []>,
325              T1Misc<{0,0,0,0,0,?,?}> {
326  // A6.2.5 & A8.6.8
327  bits<7> rhs;
328  let Inst{6-0} = rhs;
329}
330
331// SUB sp, sp, #<imm7>
332// FIXME: The encoding and the ASM string don't match up.
333def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
334                  "sub\t$dst, $rhs", []>,
335              T1Misc<{0,0,0,0,1,?,?}> {
336  // A6.2.5 & A8.6.214
337  bits<7> rhs;
338  let Inst{6-0} = rhs;
339}
340
341// ADD <Rm>, sp
342def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
343                  "add\t$dst, $rhs", []>,
344              T1Special<{0,0,?,?}> {
345  // A8.6.9 Encoding T1
346  bits<4> dst;
347  let Inst{7}   = dst{3};
348  let Inst{6-3} = 0b1101;
349  let Inst{2-0} = dst{2-0};
350}
351
352// ADD sp, <Rm>
353def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
354                  "add\t$dst, $rhs", []>,
355              T1Special<{0,0,?,?}> {
356  // A8.6.9 Encoding T2
357  bits<4> dst;
358  let Inst{7} = 1;
359  let Inst{6-3} = dst;
360  let Inst{2-0} = 0b101;
361}
362
363//===----------------------------------------------------------------------===//
364//  Control Flow Instructions.
365//
366
367let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
368  def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
369                   [(ARMretflag)]>,
370                T1Special<{1,1,0,?}> {
371    // A6.2.3 & A8.6.25
372    let Inst{6-3} = 0b1110; // Rm = lr
373    let Inst{2-0} = 0b000;
374  }
375
376  // Alternative return instruction used by vararg functions.
377  def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
378                          IIC_Br, "bx\t$Rm",
379                          []>,
380                       T1Special<{1,1,0,?}> {
381    // A6.2.3 & A8.6.25
382    bits<4> Rm;
383    let Inst{6-3} = Rm;
384    let Inst{2-0} = 0b000;
385  }
386}
387
388// Indirect branches
389let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
390  def tBRIND : TI<(outs), (ins GPR:$Rm),
391                  IIC_Br,
392                  "mov\tpc, $Rm",
393                  [(brind GPR:$Rm)]>,
394               T1Special<{1,0,?,?}> {
395    // A8.6.97
396    bits<4> Rm;
397    let Inst{7}   = 1;          // <Rd> = Inst{7:2-0} = pc
398    let Inst{6-3} = Rm;
399    let Inst{2-0} = 0b111;
400  }
401}
402
403// FIXME: remove when we have a way to marking a MI with these properties.
404let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
405    hasExtraDefRegAllocReq = 1 in
406def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
407                   IIC_iPop_Br,
408                   "pop${p}\t$regs", []>,
409               T1Misc<{1,1,0,?,?,?,?}> {
410  // A8.6.121
411  bits<16> regs;
412  let Inst{8}   = regs{15};     // registers = P:'0000000':register_list
413  let Inst{7-0} = regs{7-0};
414}
415
416// All calls clobber the non-callee saved registers. SP is marked as a use to
417// prevent stack-pointer assignments that appear immediately before calls from
418// potentially appearing dead.
419let isCall = 1,
420  // On non-Darwin platforms R9 is callee-saved.
421  Defs = [R0,  R1,  R2,  R3,  R12, LR,
422          D0,  D1,  D2,  D3,  D4,  D5,  D6,  D7,
423          D16, D17, D18, D19, D20, D21, D22, D23,
424          D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
425  Uses = [SP] in {
426  // Also used for Thumb2
427  def tBL  : TIx2<0b11110, 0b11, 1,
428                  (outs), (ins t_bltarget:$func, variable_ops), IIC_Br,
429                  "bl\t$func",
430                  [(ARMtcall tglobaladdr:$func)]>,
431             Requires<[IsThumb, IsNotDarwin]> {
432    bits<21> func;
433    let Inst{25-16} = func{20-11};
434    let Inst{13} = 1;
435    let Inst{11} = 1;
436    let Inst{10-0} = func{10-0};
437  }
438
439  // ARMv5T and above, also used for Thumb2
440  def tBLXi : TIx2<0b11110, 0b11, 0,
441                   (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br,
442                   "blx\t$func",
443                   [(ARMcall tglobaladdr:$func)]>,
444              Requires<[IsThumb, HasV5T, IsNotDarwin]> {
445    bits<21> func;
446    let Inst{25-16} = func{20-11};
447    let Inst{13} = 1;
448    let Inst{11} = 1;
449    let Inst{10-1} = func{10-1};
450    let Inst{0} = 0; // func{0} is assumed zero
451  }
452
453  // Also used for Thumb2
454  def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
455                  "blx\t$func",
456                  [(ARMtcall GPR:$func)]>,
457              Requires<[IsThumb, HasV5T, IsNotDarwin]>,
458              T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
459
460  // ARMv4T
461  // FIXME: Should be a pseudo.
462  let isCodeGenOnly = 1 in
463  def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
464                  (outs), (ins tGPR:$func, variable_ops), IIC_Br,
465                  "mov\tlr, pc\n\tbx\t$func",
466                  [(ARMcall_nolink tGPR:$func)]>,
467            Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
468}
469
470let isCall = 1,
471  // On Darwin R9 is call-clobbered.
472  // R7 is marked as a use to prevent frame-pointer assignments from being
473  // moved above / below calls.
474  Defs = [R0,  R1,  R2,  R3,  R9,  R12, LR,
475          D0,  D1,  D2,  D3,  D4,  D5,  D6,  D7,
476          D16, D17, D18, D19, D20, D21, D22, D23,
477          D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
478  Uses = [R7, SP] in {
479  // Also used for Thumb2
480  def tBLr9 : TIx2<0b11110, 0b11, 1,
481                   (outs), (ins pred:$p, t_bltarget:$func, variable_ops),
482                   IIC_Br, "bl${p}\t$func",
483                   [(ARMtcall tglobaladdr:$func)]>,
484              Requires<[IsThumb, IsDarwin]> {
485    bits<21> func;
486    let Inst{25-16} = func{20-11};
487    let Inst{13} = 1;
488    let Inst{11} = 1;
489    let Inst{10-0} = func{10-0};
490  }
491
492  // ARMv5T and above, also used for Thumb2
493  def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
494                      (outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
495                      IIC_Br, "blx${p}\t$func",
496                      [(ARMcall tglobaladdr:$func)]>,
497                 Requires<[IsThumb, HasV5T, IsDarwin]> {
498    bits<21> func;
499    let Inst{25-16} = func{20-11};
500    let Inst{13} = 1;
501    let Inst{11} = 1;
502    let Inst{10-1} = func{10-1};
503    let Inst{0} = 0; // func{0} is assumed zero
504  }
505
506  // Also used for Thumb2
507  def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
508                    "blx${p}\t$func",
509                    [(ARMtcall GPR:$func)]>,
510                 Requires<[IsThumb, HasV5T, IsDarwin]>,
511                 T1Special<{1,1,1,?}> {
512    // A6.2.3 & A8.6.24
513    bits<4> func;
514    let Inst{6-3} = func;
515    let Inst{2-0} = 0b000;
516  }
517
518  // ARMv4T
519  let isCodeGenOnly = 1 in
520  // FIXME: Should be a pseudo.
521  def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
522                   (outs), (ins tGPR:$func, variable_ops), IIC_Br,
523                   "mov\tlr, pc\n\tbx\t$func",
524                   [(ARMcall_nolink tGPR:$func)]>,
525              Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
526}
527
528let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
529  let isPredicable = 1 in
530  def tB   : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
531                 "b\t$target", [(br bb:$target)]>,
532             T1Encoding<{1,1,1,0,0,?}> {
533    bits<11> target;
534    let Inst{10-0} = target;
535  }
536
537  // Far jump
538  // Just a pseudo for a tBL instruction. Needed to let regalloc know about
539  // the clobber of LR.
540  let Defs = [LR] in
541  def tBfar : tPseudoInst<(outs), (ins t_bltarget:$target),
542                          Size4Bytes, IIC_Br, []>;
543
544  def tBR_JTr : tPseudoInst<(outs),
545                      (ins tGPR:$target, i32imm:$jt, i32imm:$id),
546                      SizeSpecial, IIC_Br,
547                      [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
548    list<Predicate> Predicates = [IsThumb, IsThumb1Only];
549  }
550}
551
552// FIXME: should be able to write a pattern for ARMBrcond, but can't use
553// a two-value operand where a dag node expects two operands. :(
554let isBranch = 1, isTerminator = 1 in
555  def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
556                 "b${p}\t$target",
557                 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
558             T1Encoding<{1,1,0,1,?,?}> {
559  bits<4> p;
560  bits<8> target;
561  let Inst{11-8} = p;
562  let Inst{7-0} = target;
563}
564
565// Compare and branch on zero / non-zero
566let isBranch = 1, isTerminator = 1 in {
567  def tCBZ  : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
568                  "cbz\t$Rn, $target", []>,
569              T1Misc<{0,0,?,1,?,?,?}> {
570    // A8.6.27
571    bits<6> target;
572    bits<3> Rn;
573    let Inst{9}   = target{5};
574    let Inst{7-3} = target{4-0};
575    let Inst{2-0} = Rn;
576  }
577
578  def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
579                  "cbnz\t$cmp, $target", []>,
580              T1Misc<{1,0,?,1,?,?,?}> {
581    // A8.6.27
582    bits<6> target;
583    bits<3> Rn;
584    let Inst{9}   = target{5};
585    let Inst{7-3} = target{4-0};
586    let Inst{2-0} = Rn;
587  }
588}
589
590// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
591// A8.6.16 B: Encoding T1
592// If Inst{11-8} == 0b1111 then SEE SVC
593let isCall = 1, Uses = [SP] in
594def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
595                "svc", "\t$imm", []>, Encoding16 {
596  bits<8> imm;
597  let Inst{15-12} = 0b1101;
598  let Inst{11-8}  = 0b1111;
599  let Inst{7-0}   = imm;
600}
601
602// The assembler uses 0xDEFE for a trap instruction.
603let isBarrier = 1, isTerminator = 1 in
604def tTRAP : TI<(outs), (ins), IIC_Br, 
605               "trap", [(trap)]>, Encoding16 {
606  let Inst = 0xdefe;
607}
608
609//===----------------------------------------------------------------------===//
610//  Load Store Instructions.
611//
612
613// Loads: reg/reg and reg/imm5
614let canFoldAsLoad = 1, isReMaterializable = 1 in
615multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
616                              Operand AddrMode_r, Operand AddrMode_i,
617                              AddrMode am, InstrItinClass itin_r,
618                              InstrItinClass itin_i, string asm,
619                              PatFrag opnode> {
620  def r : // reg/reg
621    T1pILdStEncode<reg_opc,
622                   (outs tGPR:$Rt), (ins AddrMode_r:$addr),
623                   am, itin_r, asm, "\t$Rt, $addr",
624                   [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
625  def i : // reg/imm5
626    T1pILdStEncodeImm<imm_opc, 1 /* Load */,
627                      (outs tGPR:$Rt), (ins AddrMode_i:$addr),
628                      am, itin_i, asm, "\t$Rt, $addr",
629                      [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
630}
631// Stores: reg/reg and reg/imm5
632multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
633                              Operand AddrMode_r, Operand AddrMode_i,
634                              AddrMode am, InstrItinClass itin_r,
635                              InstrItinClass itin_i, string asm,
636                              PatFrag opnode> {
637  def r : // reg/reg
638    T1pILdStEncode<reg_opc,
639                   (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
640                   am, itin_r, asm, "\t$Rt, $addr",
641                   [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
642  def i : // reg/imm5
643    T1pILdStEncodeImm<imm_opc, 0 /* Store */,
644                      (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
645                      am, itin_i, asm, "\t$Rt, $addr",
646                      [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
647}
648
649// A8.6.57 & A8.6.60
650defm tLDR  : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
651                                t_addrmode_is4, AddrModeT1_4,
652                                IIC_iLoad_r, IIC_iLoad_i, "ldr",
653                                UnOpFrag<(load node:$Src)>>;
654
655// A8.6.64 & A8.6.61
656defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
657                                t_addrmode_is1, AddrModeT1_1,
658                                IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
659                                UnOpFrag<(zextloadi8 node:$Src)>>;
660
661// A8.6.76 & A8.6.73
662defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
663                                t_addrmode_is2, AddrModeT1_2,
664                                IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
665                                UnOpFrag<(zextloadi16 node:$Src)>>;
666
667let AddedComplexity = 10 in
668def tLDRSB :                    // A8.6.80
669  T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
670                 AddrModeT1_1, IIC_iLoad_bh_r,
671                 "ldrsb", "\t$dst, $addr",
672                 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
673
674let AddedComplexity = 10 in
675def tLDRSH :                    // A8.6.84
676  T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
677                 AddrModeT1_2, IIC_iLoad_bh_r,
678                 "ldrsh", "\t$dst, $addr",
679                 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
680
681let canFoldAsLoad = 1 in
682def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
683                    "ldr", "\t$Rt, $addr",
684                    [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
685              T1LdStSP<{1,?,?}> {
686  bits<3> Rt;
687  bits<8> addr;
688  let Inst{10-8} = Rt;
689  let Inst{7-0} = addr;
690}
691
692// Special instruction for restore. It cannot clobber condition register
693// when it's expanded by eliminateCallFramePseudoInstr().
694let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
695// FIXME: Pseudo for tLDRspi
696def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
697                     "ldr", "\t$dst, $addr", []>,
698               T1LdStSP<{1,?,?}> {
699  bits<3> Rt;
700  bits<8> addr;
701  let Inst{10-8} = Rt;
702  let Inst{7-0} = addr;
703}
704
705// Load tconstpool
706// FIXME: Use ldr.n to work around a Darwin assembler bug.
707let canFoldAsLoad = 1, isReMaterializable = 1 in
708def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
709                  "ldr", ".n\t$Rt, $addr",
710                  [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
711              T1Encoding<{0,1,0,0,1,?}> {
712  // A6.2 & A8.6.59
713  bits<3> Rt;
714  bits<8> addr;
715  let Inst{10-8} = Rt;
716  let Inst{7-0}  = addr;
717}
718
719// A8.6.194 & A8.6.192
720defm tSTR  : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
721                                t_addrmode_is4, AddrModeT1_4,
722                                IIC_iStore_r, IIC_iStore_i, "str",
723                                BinOpFrag<(store node:$LHS, node:$RHS)>>;
724
725// A8.6.197 & A8.6.195
726defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
727                                t_addrmode_is1, AddrModeT1_1,
728                                IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
729                                BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
730
731// A8.6.207 & A8.6.205
732defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
733                                t_addrmode_is2, AddrModeT1_2,
734                                IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
735                                BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
736
737
738def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
739                    "str", "\t$Rt, $addr",
740                    [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
741              T1LdStSP<{0,?,?}> {
742  bits<3> Rt;
743  bits<8> addr;
744  let Inst{10-8} = Rt;
745  let Inst{7-0} = addr;
746}
747
748let mayStore = 1, neverHasSideEffects = 1 in
749// Special instruction for spill. It cannot clobber condition register when it's
750// expanded by eliminateCallFramePseudoInstr().
751// FIXME: Pseudo for tSTRspi
752def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
753                  "str", "\t$src, $addr", []>,
754             T1LdStSP<{0,?,?}> {
755  bits<3> Rt;
756  bits<8> addr;
757  let Inst{10-8} = Rt;
758  let Inst{7-0} = addr;
759}
760
761//===----------------------------------------------------------------------===//
762//  Load / store multiple Instructions.
763//
764
765multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
766                           InstrItinClass itin_upd, bits<6> T1Enc,
767                           bit L_bit> {
768  def IA :
769    T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
770        itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
771       T1Encoding<T1Enc> {
772    bits<3> Rn;
773    bits<8> regs;
774    let Inst{10-8} = Rn;
775    let Inst{7-0}  = regs;
776  }
777  def IA_UPD :
778    T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
779         itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
780        T1Encoding<T1Enc> {
781    bits<3> Rn;
782    bits<8> regs;
783    let Inst{10-8} = Rn;
784    let Inst{7-0}  = regs;
785  }
786}
787
788// These require base address to be written back or one of the loaded regs.
789let neverHasSideEffects = 1 in {
790
791let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
792defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
793                            {1,1,0,0,1,?}, 1>;
794
795let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
796defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
797                            {1,1,0,0,0,?}, 0>;
798 
799} // neverHasSideEffects
800
801let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
802def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
803               IIC_iPop,
804               "pop${p}\t$regs", []>,
805           T1Misc<{1,1,0,?,?,?,?}> {
806  bits<16> regs;
807  let Inst{8}   = regs{15};
808  let Inst{7-0} = regs{7-0};
809}
810
811let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
812def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
813                IIC_iStore_m,
814                "push${p}\t$regs", []>,
815            T1Misc<{0,1,0,?,?,?,?}> {
816  bits<16> regs;
817  let Inst{8}   = regs{14};
818  let Inst{7-0} = regs{7-0};
819}
820
821//===----------------------------------------------------------------------===//
822//  Arithmetic Instructions.
823//
824
825// Helper classes for encoding T1pI patterns:
826class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
827                   string opc, string asm, list<dag> pattern>
828    : T1pI<oops, iops, itin, opc, asm, pattern>,
829      T1DataProcessing<opA> {
830  bits<3> Rm;
831  bits<3> Rn;
832  let Inst{5-3} = Rm;
833  let Inst{2-0} = Rn;
834}
835class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
836                     string opc, string asm, list<dag> pattern>
837    : T1pI<oops, iops, itin, opc, asm, pattern>,
838      T1Misc<opA> {
839  bits<3> Rm;
840  bits<3> Rd;
841  let Inst{5-3} = Rm;
842  let Inst{2-0} = Rd;
843}
844
845// Helper classes for encoding T1sI patterns:
846class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
847                   string opc, string asm, list<dag> pattern>
848    : T1sI<oops, iops, itin, opc, asm, pattern>,
849      T1DataProcessing<opA> {
850  bits<3> Rd;
851  bits<3> Rn;
852  let Inst{5-3} = Rn;
853  let Inst{2-0} = Rd;
854}
855class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
856                    string opc, string asm, list<dag> pattern>
857    : T1sI<oops, iops, itin, opc, asm, pattern>,
858      T1General<opA> {
859  bits<3> Rm;
860  bits<3> Rn;
861  bits<3> Rd;
862  let Inst{8-6} = Rm;
863  let Inst{5-3} = Rn;
864  let Inst{2-0} = Rd;
865}
866class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
867                       string opc, string asm, list<dag> pattern>
868    : T1sI<oops, iops, itin, opc, asm, pattern>,
869      T1General<opA> {
870  bits<3> Rd;
871  bits<3> Rm;
872  let Inst{5-3} = Rm;
873  let Inst{2-0} = Rd;
874}
875
876// Helper classes for encoding T1sIt patterns:
877class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
878                    string opc, string asm, list<dag> pattern>
879    : T1sIt<oops, iops, itin, opc, asm, pattern>,
880      T1DataProcessing<opA> {
881  bits<3> Rdn;
882  bits<3> Rm;
883  let Inst{5-3} = Rm;
884  let Inst{2-0} = Rdn;
885}
886class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
887                        string opc, string asm, list<dag> pattern>
888    : T1sIt<oops, iops, itin, opc, asm, pattern>,
889      T1General<opA> {
890  bits<3> Rdn;
891  bits<8> imm8;
892  let Inst{10-8} = Rdn;
893  let Inst{7-0}  = imm8;
894}
895
896// Add with carry register
897let isCommutable = 1, Uses = [CPSR] in
898def tADC :                      // A8.6.2
899  T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
900                "adc", "\t$Rdn, $Rm",
901                [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
902
903// Add immediate
904def tADDi3 :                    // A8.6.4 T1
905  T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi,
906                   "add", "\t$Rd, $Rm, $imm3",
907                   [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
908  bits<3> imm3;
909  let Inst{8-6} = imm3;
910}
911
912def tADDi8 :                    // A8.6.4 T2
913  T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
914                    IIC_iALUi,
915                    "add", "\t$Rdn, $imm8",
916                    [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
917
918// Add register
919let isCommutable = 1 in
920def tADDrr :                    // A8.6.6 T1
921  T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
922                IIC_iALUr,
923                "add", "\t$Rd, $Rn, $Rm",
924                [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
925
926let neverHasSideEffects = 1 in
927def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
928                     "add", "\t$Rdn, $Rm", []>,
929               T1Special<{0,0,?,?}> {
930  // A8.6.6 T2
931  bits<4> Rdn;
932  bits<4> Rm;
933  let Inst{7}   = Rdn{3};
934  let Inst{6-3} = Rm;
935  let Inst{2-0} = Rdn{2-0};
936}
937
938// AND register
939let isCommutable = 1 in
940def tAND :                      // A8.6.12
941  T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
942                IIC_iBITr,
943                "and", "\t$Rdn, $Rm",
944                [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
945
946// ASR immediate
947def tASRri :                    // A8.6.14
948  T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
949                   IIC_iMOVsi,
950                   "asr", "\t$Rd, $Rm, $imm5",
951                   [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
952  bits<5> imm5;
953  let Inst{10-6} = imm5;
954}
955
956// ASR register
957def tASRrr :                    // A8.6.15
958  T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
959                IIC_iMOVsr,
960                "asr", "\t$Rdn, $Rm",
961                [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
962
963// BIC register
964def tBIC :                      // A8.6.20
965  T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
966                IIC_iBITr,
967                "bic", "\t$Rdn, $Rm",
968                [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
969
970// CMN register
971let isCompare = 1, Defs = [CPSR] in {
972//FIXME: Disable CMN, as CCodes are backwards from compare expectations
973//       Compare-to-zero still works out, just not the relationals
974//def tCMN :                     // A8.6.33
975//  T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
976//               IIC_iCMPr,
977//               "cmn", "\t$lhs, $rhs",
978//               [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
979
980def tCMNz :                     // A8.6.33
981  T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
982               IIC_iCMPr,
983               "cmn", "\t$Rn, $Rm",
984               [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
985
986} // isCompare = 1, Defs = [CPSR]
987
988// CMP immediate
989let isCompare = 1, Defs = [CPSR] in {
990def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
991                  "cmp", "\t$Rn, $imm8",
992                  [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
993             T1General<{1,0,1,?,?}> {
994  // A8.6.35
995  bits<3> Rn;
996  bits<8> imm8;
997  let Inst{10-8} = Rn;
998  let Inst{7-0}  = imm8;
999}
1000
1001// CMP register
1002def tCMPr :                     // A8.6.36 T1
1003  T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1004               IIC_iCMPr,
1005               "cmp", "\t$Rn, $Rm",
1006               [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
1007
1008def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
1009                   "cmp", "\t$Rn, $Rm", []>,
1010              T1Special<{0,1,?,?}> {
1011  // A8.6.36 T2
1012  bits<4> Rm;
1013  bits<4> Rn;
1014  let Inst{7}   = Rn{3};
1015  let Inst{6-3} = Rm;
1016  let Inst{2-0} = Rn{2-0};
1017}
1018} // isCompare = 1, Defs = [CPSR]
1019
1020
1021// XOR register
1022let isCommutable = 1 in
1023def tEOR :                      // A8.6.45
1024  T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1025                IIC_iBITr,
1026                "eor", "\t$Rdn, $Rm",
1027                [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
1028
1029// LSL immediate
1030def tLSLri :                    // A8.6.88
1031  T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1032                   IIC_iMOVsi,
1033                   "lsl", "\t$Rd, $Rm, $imm5",
1034                   [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
1035  bits<5> imm5;
1036  let Inst{10-6} = imm5;
1037}
1038
1039// LSL register
1040def tLSLrr :                    // A8.6.89
1041  T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1042                IIC_iMOVsr,
1043                "lsl", "\t$Rdn, $Rm",
1044                [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1045
1046// LSR immediate
1047def tLSRri :                    // A8.6.90
1048  T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1049                   IIC_iMOVsi,
1050                   "lsr", "\t$Rd, $Rm, $imm5",
1051                   [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
1052  bits<5> imm5;
1053  let Inst{10-6} = imm5;
1054}
1055
1056// LSR register
1057def tLSRrr :                    // A8.6.91
1058  T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1059                IIC_iMOVsr,
1060                "lsr", "\t$Rdn, $Rm",
1061                [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1062
1063// Move register
1064let isMoveImm = 1 in
1065def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi,
1066                  "mov", "\t$Rd, $imm8",
1067                  [(set tGPR:$Rd, imm0_255:$imm8)]>,
1068             T1General<{1,0,0,?,?}> {
1069  // A8.6.96
1070  bits<3> Rd;
1071  bits<8> imm8;
1072  let Inst{10-8} = Rd;
1073  let Inst{7-0}  = imm8;
1074}
1075
1076// TODO: A7-73: MOV(2) - mov setting flag.
1077
1078let neverHasSideEffects = 1 in {
1079// FIXME: Make this predicable.
1080def tMOVr       : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1081                      "mov\t$Rd, $Rm", []>,
1082                  T1Special<0b1000> {
1083  // A8.6.97
1084  bits<4> Rd;
1085  bits<4> Rm;
1086  // Bits {7-6} are encoded by the T1Special value.
1087  let Inst{5-3} = Rm{2-0};
1088  let Inst{2-0} = Rd{2-0};
1089}
1090let Defs = [CPSR] in
1091def tMOVSr      : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1092                      "movs\t$Rd, $Rm", []>, Encoding16 {
1093  // A8.6.97
1094  bits<3> Rd;
1095  bits<3> Rm;
1096  let Inst{15-6} = 0b0000000000;
1097  let Inst{5-3}  = Rm;
1098  let Inst{2-0}  = Rd;
1099}
1100
1101// FIXME: Make these predicable.
1102def tMOVgpr2tgpr : T1I<(outs tGPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1103                       "mov\t$Rd, $Rm", []>,
1104                   T1Special<{1,0,0,?}> {
1105  // A8.6.97
1106  bits<4> Rd;
1107  bits<4> Rm;
1108  // Bit {7} is encoded by the T1Special value.
1109  let Inst{6-3} = Rm;
1110  let Inst{2-0} = Rd{2-0};
1111}
1112def tMOVtgpr2gpr : T1I<(outs GPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1113                       "mov\t$Rd, $Rm", []>,
1114                   T1Special<{1,0,?,0}> {
1115  // A8.6.97
1116  bits<4> Rd;
1117  bits<4> Rm;
1118  // Bit {6} is encoded by the T1Special value.
1119  let Inst{7}   = Rd{3};
1120  let Inst{5-3} = Rm{2-0};
1121  let Inst{2-0} = Rd{2-0};
1122}
1123def tMOVgpr2gpr  : T1I<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1124                       "mov\t$Rd, $Rm", []>,
1125                   T1Special<{1,0,?,?}> {
1126  // A8.6.97
1127  bits<4> Rd;
1128  bits<4> Rm;
1129  let Inst{7}   = Rd{3};
1130  let Inst{6-3} = Rm;
1131  let Inst{2-0} = Rd{2-0};
1132}
1133} // neverHasSideEffects
1134
1135// Multiply register
1136let isCommutable = 1 in
1137def tMUL :                      // A8.6.105 T1
1138  T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1139                IIC_iMUL32,
1140                "mul", "\t$Rdn, $Rm, $Rdn",
1141                [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1142
1143// Move inverse register
1144def tMVN :                      // A8.6.107
1145  T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1146               "mvn", "\t$Rd, $Rn",
1147               [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1148
1149// Bitwise or register
1150let isCommutable = 1 in
1151def tORR :                      // A8.6.114
1152  T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1153                IIC_iBITr,
1154                "orr", "\t$Rdn, $Rm",
1155                [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1156
1157// Swaps
1158def tREV :                      // A8.6.134
1159  T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1160                 IIC_iUNAr,
1161                 "rev", "\t$Rd, $Rm",
1162                 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1163                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1164
1165def tREV16 :                    // A8.6.135
1166  T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1167                 IIC_iUNAr,
1168                 "rev16", "\t$Rd, $Rm",
1169             [(set tGPR:$Rd,
1170                   (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
1171                       (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
1172                           (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
1173                               (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
1174                Requires<[IsThumb, IsThumb1Only, HasV6]>;
1175
1176def tREVSH :                    // A8.6.136
1177  T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1178                 IIC_iUNAr,
1179                 "revsh", "\t$Rd, $Rm",
1180                 [(set tGPR:$Rd,
1181                       (sext_inreg
1182                         (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
1183                             (shl tGPR:$Rm, (i32 8))), i16))]>,
1184                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1185
1186// Rotate right register
1187def tROR :                      // A8.6.139
1188  T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1189                IIC_iMOVsr,
1190                "ror", "\t$Rdn, $Rm",
1191                [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1192
1193// Negate register
1194def tRSB :                      // A8.6.141
1195  T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1196               IIC_iALUi,
1197               "rsb", "\t$Rd, $Rn, #0",
1198               [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1199
1200// Subtract with carry register
1201let Uses = [CPSR] in
1202def tSBC :                      // A8.6.151
1203  T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1204                IIC_iALUr,
1205                "sbc", "\t$Rdn, $Rm",
1206                [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1207
1208// Subtract immediate
1209def tSUBi3 :                    // A8.6.210 T1
1210  T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1211                   IIC_iALUi,
1212                   "sub", "\t$Rd, $Rm, $imm3",
1213                   [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1214  bits<3> imm3;
1215  let Inst{8-6} = imm3;
1216}
1217
1218def tSUBi8 :                    // A8.6.210 T2
1219  T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1220                    IIC_iALUi,
1221                    "sub", "\t$Rdn, $imm8",
1222                    [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1223
1224// Subtract register
1225def tSUBrr :                    // A8.6.212
1226  T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1227                IIC_iALUr,
1228                "sub", "\t$Rd, $Rn, $Rm",
1229                [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1230
1231// TODO: A7-96: STMIA - store multiple.
1232
1233// Sign-extend byte
1234def tSXTB :                     // A8.6.222
1235  T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1236                 IIC_iUNAr,
1237                 "sxtb", "\t$Rd, $Rm",
1238                 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1239                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1240
1241// Sign-extend short
1242def tSXTH :                     // A8.6.224
1243  T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1244                 IIC_iUNAr,
1245                 "sxth", "\t$Rd, $Rm",
1246                 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1247                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1248
1249// Test
1250let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1251def tTST :                      // A8.6.230
1252  T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1253               "tst", "\t$Rn, $Rm",
1254               [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1255
1256// Zero-extend byte
1257def tUXTB :                     // A8.6.262
1258  T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1259                 IIC_iUNAr,
1260                 "uxtb", "\t$Rd, $Rm",
1261                 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1262                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1263
1264// Zero-extend short
1265def tUXTH :                     // A8.6.264
1266  T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1267                 IIC_iUNAr,
1268                 "uxth", "\t$Rd, $Rm",
1269                 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1270                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1271
1272// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1273// Expanded after instruction selection into a branch sequence.
1274let usesCustomInserter = 1 in  // Expanded after instruction selection.
1275  def tMOVCCr_pseudo :
1276  PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1277              NoItinerary,
1278             [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1279
1280
1281// 16-bit movcc in IT blocks for Thumb2.
1282let neverHasSideEffects = 1 in {
1283def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr,
1284                    "mov", "\t$Rdn, $Rm", []>,
1285              T1Special<{1,0,?,?}> {
1286  bits<4> Rdn;
1287  bits<4> Rm;
1288  let Inst{7}   = Rdn{3};
1289  let Inst{6-3} = Rm;
1290  let Inst{2-0} = Rdn{2-0};
1291}
1292
1293let isMoveImm = 1 in
1294def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
1295                    "mov", "\t$Rdn, $Rm", []>,
1296              T1General<{1,0,0,?,?}> {
1297  bits<3> Rdn;
1298  bits<8> Rm;
1299  let Inst{10-8} = Rdn;
1300  let Inst{7-0}  = Rm;
1301}
1302
1303} // neverHasSideEffects
1304
1305// tLEApcrel - Load a pc-relative address into a register without offending the
1306// assembler.
1307
1308def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1309               IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1310               T1Encoding<{1,0,1,0,0,?}> {
1311  bits<3> Rd;
1312  bits<8> addr;
1313  let Inst{10-8} = Rd;
1314  let Inst{7-0} = addr;
1315}
1316
1317let neverHasSideEffects = 1, isReMaterializable = 1 in
1318def tLEApcrel   : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1319                              Size2Bytes, IIC_iALUi, []>;
1320
1321def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1322                              (ins i32imm:$label, nohash_imm:$id, pred:$p),
1323                              Size2Bytes, IIC_iALUi, []>;
1324
1325//===----------------------------------------------------------------------===//
1326// Move between coprocessor and ARM core register -- for disassembly only
1327//
1328
1329class tMovRCopro<string opc, bit direction>
1330  : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
1331                       GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1332          !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
1333          [/* For disassembly only; pattern left blank */]> {
1334  let Inst{27-24} = 0b1110;
1335  let Inst{20} = direction;
1336  let Inst{4} = 1;
1337
1338  bits<4> Rt;
1339  bits<4> cop;
1340  bits<3> opc1;
1341  bits<3> opc2;
1342  bits<4> CRm;
1343  bits<4> CRn;
1344
1345  let Inst{15-12} = Rt;
1346  let Inst{11-8}  = cop;
1347  let Inst{23-21} = opc1;
1348  let Inst{7-5}   = opc2;
1349  let Inst{3-0}   = CRm;
1350  let Inst{19-16} = CRn;
1351}
1352
1353def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */>;
1354def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */>;
1355
1356class tMovRRCopro<string opc, bit direction>
1357  : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
1358          !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
1359          [/* For disassembly only; pattern left blank */]> {
1360  let Inst{27-24} = 0b1100;
1361  let Inst{23-21} = 0b010;
1362  let Inst{20} = direction;
1363
1364  bits<4> Rt;
1365  bits<4> Rt2;
1366  bits<4> cop;
1367  bits<4> opc1;
1368  bits<4> CRm;
1369
1370  let Inst{15-12} = Rt;
1371  let Inst{19-16} = Rt2;
1372  let Inst{11-8}  = cop;
1373  let Inst{7-4}   = opc1;
1374  let Inst{3-0}   = CRm;
1375}
1376
1377def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
1378def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
1379
1380//===----------------------------------------------------------------------===//
1381// TLS Instructions
1382//
1383
1384// __aeabi_read_tp preserves the registers r1-r3.
1385let isCall = 1, Defs = [R0, LR], Uses = [SP] in
1386def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
1387                   "bl\t__aeabi_read_tp",
1388                   [(set R0, ARMthread_pointer)]> {
1389  // Encoding is 0xf7fffffe.
1390  let Inst = 0xf7fffffe;
1391}
1392
1393//===----------------------------------------------------------------------===//
1394// SJLJ Exception handling intrinsics
1395// 
1396
1397// eh_sjlj_setjmp() is an instruction sequence to store the return address and
1398// save #0 in R0 for the non-longjmp case.  Since by its nature we may be coming
1399// from some other function to get here, and we're using the stack frame for the
1400// containing function to save/restore registers, we can't keep anything live in
1401// regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1402// tromped upon when we get here from a longjmp(). We force everthing out of
1403// registers except for our own input by listing the relevant registers in
1404// Defs. By doing so, we also cause the prologue/epilogue code to actively
1405// preserve all of the callee-saved resgisters, which is exactly what we want.
1406// $val is a scratch register for our use.
1407let Defs = [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7, R12 ],
1408    hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1409def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1410                                  AddrModeNone, SizeSpecial, NoItinerary, "","",
1411                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1412
1413// FIXME: Non-Darwin version(s)
1414let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1415    Defs = [ R7, LR, SP ] in
1416def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1417                              AddrModeNone, SizeSpecial, IndexModeNone,
1418                              Pseudo, NoItinerary, "", "",
1419                              [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1420                             Requires<[IsThumb, IsDarwin]>;
1421
1422//===----------------------------------------------------------------------===//
1423// Non-Instruction Patterns
1424//
1425
1426// Comparisons
1427def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1428            (tCMPi8  tGPR:$Rn, imm0_255:$imm8)>;
1429def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1430            (tCMPr   tGPR:$Rn, tGPR:$Rm)>;
1431
1432// Add with carry
1433def : T1Pat<(addc   tGPR:$lhs, imm0_7:$rhs),
1434            (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1435def : T1Pat<(addc   tGPR:$lhs, imm8_255:$rhs),
1436            (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1437def : T1Pat<(addc   tGPR:$lhs, tGPR:$rhs),
1438            (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1439
1440// Subtract with carry
1441def : T1Pat<(addc   tGPR:$lhs, imm0_7_neg:$rhs),
1442            (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1443def : T1Pat<(addc   tGPR:$lhs, imm8_255_neg:$rhs),
1444            (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1445def : T1Pat<(subc   tGPR:$lhs, tGPR:$rhs),
1446            (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1447
1448// ConstantPool, GlobalAddress
1449def : T1Pat<(ARMWrapper  tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1450def : T1Pat<(ARMWrapper  tconstpool  :$dst), (tLEApcrel tconstpool  :$dst)>;
1451
1452// JumpTable
1453def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1454            (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1455
1456// Direct calls
1457def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1458      Requires<[IsThumb, IsNotDarwin]>;
1459def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1460      Requires<[IsThumb, IsDarwin]>;
1461
1462def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1463      Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1464def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1465      Requires<[IsThumb, HasV5T, IsDarwin]>;
1466
1467// Indirect calls to ARM routines
1468def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1469      Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1470def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1471      Requires<[IsThumb, HasV5T, IsDarwin]>;
1472
1473// zextload i1 -> zextload i8
1474def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1475            (tLDRBr t_addrmode_rrs1:$addr)>;
1476def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1477            (tLDRBi t_addrmode_is1:$addr)>;
1478
1479// extload -> zextload
1480def : T1Pat<(extloadi1  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1481def : T1Pat<(extloadi1  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
1482def : T1Pat<(extloadi8  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1483def : T1Pat<(extloadi8  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
1484def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1485def : T1Pat<(extloadi16 t_addrmode_is2:$addr),  (tLDRHi t_addrmode_is2:$addr)>;
1486
1487// If it's impossible to use [r,r] address mode for sextload, select to
1488// ldr{b|h} + sxt{b|h} instead.
1489def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1490            (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1491      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1492def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1493            (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1494      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1495def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1496            (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1497      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1498def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1499            (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1500      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1501
1502def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1503            (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1504def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1505            (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1506def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1507            (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1508def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1509            (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1510
1511// Large immediate handling.
1512
1513// Two piece imms.
1514def : T1Pat<(i32 thumb_immshifted:$src),
1515            (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1516                    (thumb_immshifted_shamt imm:$src))>;
1517
1518def : T1Pat<(i32 imm0_255_comp:$src),
1519            (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1520
1521// Pseudo instruction that combines ldr from constpool and add pc. This should
1522// be expanded into two instructions late to allow if-conversion and
1523// scheduling.
1524let isReMaterializable = 1 in
1525def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1526                             NoItinerary,
1527               [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1528                                           imm:$cp))]>,
1529               Requires<[IsThumb, IsThumb1Only]>;
1530