ARMInstrThumb2.td revision 2f54a2fd8542aa6280d1c5da18ac314d16550676
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb2 instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// IT block predicate field 15def it_pred : Operand<i32> { 16 let PrintMethod = "printPredicateOperand"; 17} 18 19// IT block condition mask 20def it_mask : Operand<i32> { 21 let PrintMethod = "printThumbITMask"; 22} 23 24// Table branch address 25def tb_addrmode : Operand<i32> { 26 let PrintMethod = "printTBAddrMode"; 27} 28 29// Shifted operands. No register controlled shifts for Thumb2. 30// Note: We do not support rrx shifted operands yet. 31def t2_so_reg : Operand<i32>, // reg imm 32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 33 [shl,srl,sra,rotr]> { 34 let PrintMethod = "printT2SOOperand"; 35 let MIOperandInfo = (ops GPR, i32imm); 36} 37 38// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 39def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 41}]>; 42 43// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 44def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 46}]>; 47 48// t2_so_imm - Match a 32-bit immediate operand, which is an 49// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 50// immediate splatted into multiple bytes of the word. t2_so_imm values are 51// represented in the imm field in the same 12-bit form that they are encoded 52// into t2_so_imm instructions: the 8-bit immediate is the least significant bits 53// [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. 54def t2_so_imm : Operand<i32>, 55 PatLeaf<(imm), [{ 56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1; 57}]>; 58 59// t2_so_imm_not - Match an immediate that is a complement 60// of a t2_so_imm. 61def t2_so_imm_not : Operand<i32>, 62 PatLeaf<(imm), [{ 63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 64}], t2_so_imm_not_XFORM>; 65 66// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 67def t2_so_imm_neg : Operand<i32>, 68 PatLeaf<(imm), [{ 69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1; 70}], t2_so_imm_neg_XFORM>; 71 72// Break t2_so_imm's up into two pieces. This handles immediates with up to 16 73// bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12] 74// to get the first/second pieces. 75def t2_so_imm2part : Operand<i32>, 76 PatLeaf<(imm), [{ 77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue()); 78 }]> { 79} 80 81def t2_so_imm2part_1 : SDNodeXForm<imm, [{ 82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue()); 83 return CurDAG->getTargetConstant(V, MVT::i32); 84}]>; 85 86def t2_so_imm2part_2 : SDNodeXForm<imm, [{ 87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue()); 88 return CurDAG->getTargetConstant(V, MVT::i32); 89}]>; 90 91/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31]. 92def imm1_31 : PatLeaf<(i32 imm), [{ 93 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32; 94}]>; 95 96/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 97def imm0_4095 : Operand<i32>, 98 PatLeaf<(i32 imm), [{ 99 return (uint32_t)N->getZExtValue() < 4096; 100}]>; 101 102def imm0_4095_neg : PatLeaf<(i32 imm), [{ 103 return (uint32_t)(-N->getZExtValue()) < 4096; 104}], imm_neg_XFORM>; 105 106def imm0_255_neg : PatLeaf<(i32 imm), [{ 107 return (uint32_t)(-N->getZExtValue()) < 255; 108}], imm_neg_XFORM>; 109 110// Define Thumb2 specific addressing modes. 111 112// t2addrmode_imm12 := reg + imm12 113def t2addrmode_imm12 : Operand<i32>, 114 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 115 let PrintMethod = "printT2AddrModeImm12Operand"; 116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 117} 118 119// t2addrmode_imm8 := reg - imm8 120def t2addrmode_imm8 : Operand<i32>, 121 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 122 let PrintMethod = "printT2AddrModeImm8Operand"; 123 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 124} 125 126def t2am_imm8_offset : Operand<i32>, 127 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{ 128 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 129} 130 131// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 132def t2addrmode_imm8s4 : Operand<i32>, 133 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> { 134 let PrintMethod = "printT2AddrModeImm8s4Operand"; 135 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 136} 137 138// t2addrmode_so_reg := reg + (reg << imm2) 139def t2addrmode_so_reg : Operand<i32>, 140 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 141 let PrintMethod = "printT2AddrModeSoRegOperand"; 142 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 143} 144 145 146//===----------------------------------------------------------------------===// 147// Multiclass helpers... 148// 149 150/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 151/// unary operation that produces a value. These are predicable and can be 152/// changed to modify CPSR. 153multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{ 154 // shifted imm 155 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi, 156 opc, "\t$dst, $src", 157 [(set GPR:$dst, (opnode t2_so_imm:$src))]> { 158 let isAsCheapAsAMove = Cheap; 159 let isReMaterializable = ReMat; 160 } 161 // register 162 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 163 opc, ".w\t$dst, $src", 164 [(set GPR:$dst, (opnode GPR:$src))]>; 165 // shifted register 166 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi, 167 opc, ".w\t$dst, $src", 168 [(set GPR:$dst, (opnode t2_so_reg:$src))]>; 169} 170 171/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 172// binary operation that produces a value. These are predicable and can be 173/// changed to modify CPSR. 174multiclass T2I_bin_irs<string opc, PatFrag opnode, 175 bit Commutable = 0, string wide =""> { 176 // shifted imm 177 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 178 opc, "\t$dst, $lhs, $rhs", 179 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 180 // register 181 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 182 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), 183 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 184 let isCommutable = Commutable; 185 } 186 // shifted register 187 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 188 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), 189 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 190} 191 192/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 193// the ".w" prefix to indicate that they are wide. 194multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> : 195 T2I_bin_irs<opc, opnode, Commutable, ".w">; 196 197/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 198/// reversed. It doesn't define the 'rr' form since it's handled by its 199/// T2I_bin_irs counterpart. 200multiclass T2I_rbin_is<string opc, PatFrag opnode> { 201 // shifted imm 202 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, 203 opc, ".w\t$dst, $rhs, $lhs", 204 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 205 // shifted register 206 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi, 207 opc, "\t$dst, $rhs, $lhs", 208 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 209} 210 211/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 212/// instruction modifies the CPSR register. 213let Defs = [CPSR] in { 214multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> { 215 // shifted imm 216 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 217 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 218 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 219 // register 220 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 221 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 222 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 223 let isCommutable = Commutable; 224 } 225 // shifted register 226 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 227 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 228 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 229} 230} 231 232/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 233/// patterns for a binary operation that produces a value. 234multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> { 235 // shifted imm 236 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 237 opc, ".w\t$dst, $lhs, $rhs", 238 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 239 // 12-bit imm 240 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi, 241 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs", 242 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; 243 // register 244 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 245 opc, ".w\t$dst, $lhs, $rhs", 246 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 247 let isCommutable = Commutable; 248 } 249 // shifted register 250 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 251 opc, ".w\t$dst, $lhs, $rhs", 252 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 253} 254 255/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 256/// binary operation that produces a value and use and define the carry bit. 257/// It's not predicable. 258let Uses = [CPSR] in { 259multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> { 260 // shifted imm 261 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 262 opc, "\t$dst, $lhs, $rhs", 263 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 264 Requires<[IsThumb2, CarryDefIsUnused]>; 265 // register 266 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 267 opc, ".w\t$dst, $lhs, $rhs", 268 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 269 Requires<[IsThumb2, CarryDefIsUnused]> { 270 let isCommutable = Commutable; 271 } 272 // shifted register 273 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 274 opc, ".w\t$dst, $lhs, $rhs", 275 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 276 Requires<[IsThumb2, CarryDefIsUnused]>; 277 // Carry setting variants 278 // shifted imm 279 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 280 !strconcat(opc, "s\t$dst, $lhs, $rhs"), 281 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 282 Requires<[IsThumb2, CarryDefIsUsed]> { 283 let Defs = [CPSR]; 284 } 285 // register 286 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 287 !strconcat(opc, "s.w\t$dst, $lhs, $rhs"), 288 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 289 Requires<[IsThumb2, CarryDefIsUsed]> { 290 let Defs = [CPSR]; 291 let isCommutable = Commutable; 292 } 293 // shifted register 294 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 295 !strconcat(opc, "s.w\t$dst, $lhs, $rhs"), 296 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 297 Requires<[IsThumb2, CarryDefIsUsed]> { 298 let Defs = [CPSR]; 299 } 300} 301} 302 303/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit. 304let Defs = [CPSR] in { 305multiclass T2I_rbin_s_is<string opc, PatFrag opnode> { 306 // shifted imm 307 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), 308 IIC_iALUi, 309 !strconcat(opc, "${s}.w\t$dst, $rhs, $lhs"), 310 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 311 // shifted register 312 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), 313 IIC_iALUsi, 314 !strconcat(opc, "${s}\t$dst, $rhs, $lhs"), 315 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 316} 317} 318 319/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 320// rotate operation that produces a value. 321multiclass T2I_sh_ir<string opc, PatFrag opnode> { 322 // 5-bit imm 323 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 324 opc, ".w\t$dst, $lhs, $rhs", 325 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>; 326 // register 327 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr, 328 opc, ".w\t$dst, $lhs, $rhs", 329 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; 330} 331 332/// T2I_cmp_is - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 333/// patterns. Similar to T2I_bin_irs except the instruction does not produce 334/// a explicit result, only implicitly set CPSR. 335let Defs = [CPSR] in { 336multiclass T2I_cmp_is<string opc, PatFrag opnode> { 337 // shifted imm 338 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi, 339 opc, ".w\t$lhs, $rhs", 340 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>; 341 // register 342 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 343 opc, ".w\t$lhs, $rhs", 344 [(opnode GPR:$lhs, GPR:$rhs)]>; 345 // shifted register 346 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi, 347 opc, ".w\t$lhs, $rhs", 348 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>; 349} 350} 351 352/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 353multiclass T2I_ld<string opc, PatFrag opnode> { 354 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi, 355 opc, ".w\t$dst, $addr", 356 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>; 357 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, 358 opc, "\t$dst, $addr", 359 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>; 360 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr, 361 opc, ".w\t$dst, $addr", 362 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>; 363 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 364 opc, ".w\t$dst, $addr", 365 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> { 366 let isReMaterializable = 1; 367 } 368} 369 370/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 371multiclass T2I_st<string opc, PatFrag opnode> { 372 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei, 373 opc, ".w\t$src, $addr", 374 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>; 375 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei, 376 opc, "\t$src, $addr", 377 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>; 378 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer, 379 opc, ".w\t$src, $addr", 380 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>; 381} 382 383/// T2I_picld - Defines the PIC load pattern. 384class T2I_picld<string opc, PatFrag opnode> : 385 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoadi, 386 !strconcat("\n${addr:label}:\n\t", opc), "\t$dst, $addr", 387 [(set GPR:$dst, (opnode addrmodepc:$addr))]>; 388 389/// T2I_picst - Defines the PIC store pattern. 390class T2I_picst<string opc, PatFrag opnode> : 391 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStorer, 392 !strconcat("\n${addr:label}:\n\t", opc), "\t$src, $addr", 393 [(opnode GPR:$src, addrmodepc:$addr)]>; 394 395 396/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a 397/// register and one whose operand is a register rotated by 8/16/24. 398multiclass T2I_unary_rrot<string opc, PatFrag opnode> { 399 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 400 opc, ".w\t$dst, $src", 401 [(set GPR:$dst, (opnode GPR:$src))]>; 402 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi, 403 opc, ".w\t$dst, $src, ror $rot", 404 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>; 405} 406 407/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a 408/// register and one whose operand is a register rotated by 8/16/24. 409multiclass T2I_bin_rrot<string opc, PatFrag opnode> { 410 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr, 411 opc, "\t$dst, $LHS, $RHS", 412 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>; 413 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 414 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", 415 [(set GPR:$dst, (opnode GPR:$LHS, 416 (rotr GPR:$RHS, rot_imm:$rot)))]>; 417} 418 419//===----------------------------------------------------------------------===// 420// Instructions 421//===----------------------------------------------------------------------===// 422 423//===----------------------------------------------------------------------===// 424// Miscellaneous Instructions. 425// 426 427// LEApcrel - Load a pc-relative address into a register without offending the 428// assembler. 429def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi, 430 "adr$p.w\t$dst, #$label", []>; 431 432def t2LEApcrelJT : T2XI<(outs GPR:$dst), 433 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi, 434 "adr$p.w\t$dst, #${label}_${id}", []>; 435 436// ADD r, sp, {so_imm|i12} 437def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 438 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []>; 439def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 440 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []>; 441 442// ADD r, sp, so_reg 443def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 444 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []>; 445 446// SUB r, sp, {so_imm|i12} 447def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 448 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []>; 449def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 450 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []>; 451 452// SUB r, sp, so_reg 453def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 454 IIC_iALUsi, 455 "sub", "\t$dst, $sp, $rhs", []>; 456 457 458// Pseudo instruction that will expand into a t2SUBrSPi + a copy. 459let usesCustomInserter = 1 in { // Expanded after instruction selection. 460def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 461 NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>; 462def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 463 NoItinerary, "@ subw\t$dst, $sp, $imm", []>; 464def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 465 NoItinerary, "@ sub\t$dst, $sp, $rhs", []>; 466} // usesCustomInserter 467 468 469//===----------------------------------------------------------------------===// 470// Load / store Instructions. 471// 472 473// Load 474let canFoldAsLoad = 1 in 475defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>; 476 477// Loads with zero extension 478defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>; 479defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>; 480 481// Loads with sign extension 482defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>; 483defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>; 484 485let mayLoad = 1, hasExtraDefRegAllocReq = 1 in { 486// Load doubleword 487def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2), 488 (ins t2addrmode_imm8s4:$addr), 489 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>; 490def t2LDRDpci : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2), 491 (ins i32imm:$addr), IIC_iLoadi, 492 "ldrd", "\t$dst1, $addr", []>; 493} 494 495// zextload i1 -> zextload i8 496def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 497 (t2LDRBi12 t2addrmode_imm12:$addr)>; 498def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr), 499 (t2LDRBi8 t2addrmode_imm8:$addr)>; 500def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 501 (t2LDRBs t2addrmode_so_reg:$addr)>; 502def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 503 (t2LDRBpci tconstpool:$addr)>; 504 505// extload -> zextload 506// FIXME: Reduce the number of patterns by legalizing extload to zextload 507// earlier? 508def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 509 (t2LDRBi12 t2addrmode_imm12:$addr)>; 510def : T2Pat<(extloadi1 t2addrmode_imm8:$addr), 511 (t2LDRBi8 t2addrmode_imm8:$addr)>; 512def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 513 (t2LDRBs t2addrmode_so_reg:$addr)>; 514def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 515 (t2LDRBpci tconstpool:$addr)>; 516 517def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 518 (t2LDRBi12 t2addrmode_imm12:$addr)>; 519def : T2Pat<(extloadi8 t2addrmode_imm8:$addr), 520 (t2LDRBi8 t2addrmode_imm8:$addr)>; 521def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 522 (t2LDRBs t2addrmode_so_reg:$addr)>; 523def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 524 (t2LDRBpci tconstpool:$addr)>; 525 526def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 527 (t2LDRHi12 t2addrmode_imm12:$addr)>; 528def : T2Pat<(extloadi16 t2addrmode_imm8:$addr), 529 (t2LDRHi8 t2addrmode_imm8:$addr)>; 530def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 531 (t2LDRHs t2addrmode_so_reg:$addr)>; 532def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 533 (t2LDRHpci tconstpool:$addr)>; 534 535// Indexed loads 536let mayLoad = 1 in { 537def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 538 (ins t2addrmode_imm8:$addr), 539 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 540 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", 541 []>; 542 543def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 544 (ins GPR:$base, t2am_imm8_offset:$offset), 545 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 546 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", 547 []>; 548 549def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 550 (ins t2addrmode_imm8:$addr), 551 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 552 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", 553 []>; 554def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 555 (ins GPR:$base, t2am_imm8_offset:$offset), 556 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 557 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", 558 []>; 559 560def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 561 (ins t2addrmode_imm8:$addr), 562 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 563 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", 564 []>; 565def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 566 (ins GPR:$base, t2am_imm8_offset:$offset), 567 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 568 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", 569 []>; 570 571def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 572 (ins t2addrmode_imm8:$addr), 573 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 574 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", 575 []>; 576def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 577 (ins GPR:$base, t2am_imm8_offset:$offset), 578 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 579 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", 580 []>; 581 582def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 583 (ins t2addrmode_imm8:$addr), 584 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 585 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", 586 []>; 587def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 588 (ins GPR:$base, t2am_imm8_offset:$offset), 589 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 590 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", 591 []>; 592} 593 594// Store 595defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; 596defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 597defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 598 599// Store doubleword 600let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in 601def t2STRDi8 : T2Ii8s4<(outs), 602 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr), 603 IIC_iStorer, "strd", "\t$src1, $addr", []>; 604 605// Indexed stores 606def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb), 607 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 608 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 609 "str", "\t$src, [$base, $offset]!", "$base = $base_wb", 610 [(set GPR:$base_wb, 611 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 612 613def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb), 614 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 615 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 616 "str", "\t$src, [$base], $offset", "$base = $base_wb", 617 [(set GPR:$base_wb, 618 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 619 620def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb), 621 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 622 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 623 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb", 624 [(set GPR:$base_wb, 625 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 626 627def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb), 628 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 629 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 630 "strh", "\t$src, [$base], $offset", "$base = $base_wb", 631 [(set GPR:$base_wb, 632 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 633 634def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb), 635 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 636 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 637 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb", 638 [(set GPR:$base_wb, 639 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 640 641def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb), 642 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 643 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 644 "strb", "\t$src, [$base], $offset", "$base = $base_wb", 645 [(set GPR:$base_wb, 646 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 647 648 649// FIXME: ldrd / strd pre / post variants 650 651//===----------------------------------------------------------------------===// 652// Load / store multiple Instructions. 653// 654 655let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 656def t2LDM : T2XI<(outs), 657 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 658 IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []>; 659 660let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 661def t2STM : T2XI<(outs), 662 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 663 IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []>; 664 665//===----------------------------------------------------------------------===// 666// Move Instructions. 667// 668 669let neverHasSideEffects = 1 in 670def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 671 "mov", ".w\t$dst, $src", []>; 672 673// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16. 674let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in 675def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi, 676 "mov", ".w\t$dst, $src", 677 [(set GPR:$dst, t2_so_imm:$src)]>; 678 679let isReMaterializable = 1, isAsCheapAsAMove = 1 in 680def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi, 681 "movw", "\t$dst, $src", 682 [(set GPR:$dst, imm0_65535:$src)]>; 683 684let Constraints = "$src = $dst" in 685def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi, 686 "movt", "\t$dst, $imm", 687 [(set GPR:$dst, 688 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]>; 689 690def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>; 691 692//===----------------------------------------------------------------------===// 693// Extend Instructions. 694// 695 696// Sign extenders 697 698defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 699defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 700 701defm t2SXTAB : T2I_bin_rrot<"sxtab", 702 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 703defm t2SXTAH : T2I_bin_rrot<"sxtah", 704 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 705 706// TODO: SXT(A){B|H}16 707 708// Zero extenders 709 710let AddedComplexity = 16 in { 711defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 712defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 713defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 714 715def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 716 (t2UXTB16r_rot GPR:$Src, 24)>; 717def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 718 (t2UXTB16r_rot GPR:$Src, 8)>; 719 720defm t2UXTAB : T2I_bin_rrot<"uxtab", 721 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 722defm t2UXTAH : T2I_bin_rrot<"uxtah", 723 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 724} 725 726//===----------------------------------------------------------------------===// 727// Arithmetic Instructions. 728// 729 730defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 731defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 732 733// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 734defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; 735defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 736 737defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>; 738defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>; 739 740// RSB 741defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 742defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 743 744// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 745let AddedComplexity = 1 in 746def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), 747 (t2SUBri GPR:$src, imm0_255_neg:$imm)>; 748def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 749 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 750def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 751 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 752 753 754//===----------------------------------------------------------------------===// 755// Shift and rotate Instructions. 756// 757 758defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>; 759defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>; 760defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; 761defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; 762 763let Uses = [CPSR] in { 764def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 765 "rrx", "\t$dst, $src", 766 [(set GPR:$dst, (ARMrrx GPR:$src))]>; 767} 768 769let Defs = [CPSR] in { 770def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 771 "lsrs.w\t$dst, $src, #1", 772 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; 773def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 774 "asrs.w\t$dst, $src, #1", 775 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; 776} 777 778//===----------------------------------------------------------------------===// 779// Bitwise Instructions. 780// 781 782defm t2AND : T2I_bin_w_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 783defm t2ORR : T2I_bin_w_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 784defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 785 786defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 787 788let Constraints = "$src = $dst" in 789def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), 790 IIC_iUNAsi, "bfc", "\t$dst, $imm", 791 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>; 792 793def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 794 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []>; 795 796def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 797 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []>; 798 799// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1) 800 801defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>; 802 803// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 804let AddedComplexity = 1 in 805defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>; 806 807 808def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm), 809 (t2BICri GPR:$src, t2_so_imm_not:$imm)>; 810 811// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 812def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm), 813 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>, 814 Requires<[IsThumb2]>; 815 816def : T2Pat<(t2_so_imm_not:$src), 817 (t2MVNi t2_so_imm_not:$src)>; 818 819//===----------------------------------------------------------------------===// 820// Multiply Instructions. 821// 822let isCommutable = 1 in 823def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 824 "mul", "\t$dst, $a, $b", 825 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; 826 827def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 828 "mla", "\t$dst, $a, $b, $c", 829 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; 830 831def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 832 "mls", "\t$dst, $a, $b, $c", 833 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>; 834 835// Extra precision multiplies with low / high results 836let neverHasSideEffects = 1 in { 837let isCommutable = 1 in { 838def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64, 839 "smull", "\t$ldst, $hdst, $a, $b", []>; 840 841def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64, 842 "umull", "\t$ldst, $hdst, $a, $b", []>; 843} 844 845// Multiply + accumulate 846def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 847 "smlal", "\t$ldst, $hdst, $a, $b", []>; 848 849def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 850 "umlal", "\t$ldst, $hdst, $a, $b", []>; 851 852def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 853 "umaal", "\t$ldst, $hdst, $a, $b", []>; 854} // neverHasSideEffects 855 856// Most significant word multiply 857def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 858 "smmul", "\t$dst, $a, $b", 859 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>; 860 861def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 862 "smmla", "\t$dst, $a, $b, $c", 863 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>; 864 865 866def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 867 "smmls", "\t$dst, $a, $b, $c", 868 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>; 869 870multiclass T2I_smul<string opc, PatFrag opnode> { 871 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 872 !strconcat(opc, "bb"), "\t$dst, $a, $b", 873 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 874 (sext_inreg GPR:$b, i16)))]>; 875 876 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 877 !strconcat(opc, "bt"), "\t$dst, $a, $b", 878 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 879 (sra GPR:$b, (i32 16))))]>; 880 881 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 882 !strconcat(opc, "tb"), "\t$dst, $a, $b", 883 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 884 (sext_inreg GPR:$b, i16)))]>; 885 886 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 887 !strconcat(opc, "tt"), "\t$dst, $a, $b", 888 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 889 (sra GPR:$b, (i32 16))))]>; 890 891 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16, 892 !strconcat(opc, "wb"), "\t$dst, $a, $b", 893 [(set GPR:$dst, (sra (opnode GPR:$a, 894 (sext_inreg GPR:$b, i16)), (i32 16)))]>; 895 896 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16, 897 !strconcat(opc, "wt"), "\t$dst, $a, $b", 898 [(set GPR:$dst, (sra (opnode GPR:$a, 899 (sra GPR:$b, (i32 16))), (i32 16)))]>; 900} 901 902 903multiclass T2I_smla<string opc, PatFrag opnode> { 904 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 905 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc", 906 [(set GPR:$dst, (add GPR:$acc, 907 (opnode (sext_inreg GPR:$a, i16), 908 (sext_inreg GPR:$b, i16))))]>; 909 910 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 911 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc", 912 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 913 (sra GPR:$b, (i32 16)))))]>; 914 915 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 916 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc", 917 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 918 (sext_inreg GPR:$b, i16))))]>; 919 920 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 921 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc", 922 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 923 (sra GPR:$b, (i32 16)))))]>; 924 925 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 926 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc", 927 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 928 (sext_inreg GPR:$b, i16)), (i32 16))))]>; 929 930 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 931 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc", 932 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 933 (sra GPR:$b, (i32 16))), (i32 16))))]>; 934} 935 936defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 937defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 938 939// TODO: Halfword multiple accumulate long: SMLAL<x><y> 940// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 941 942 943//===----------------------------------------------------------------------===// 944// Misc. Arithmetic Instructions. 945// 946 947def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 948 "clz", "\t$dst, $src", 949 [(set GPR:$dst, (ctlz GPR:$src))]>; 950 951def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 952 "rev", ".w\t$dst, $src", 953 [(set GPR:$dst, (bswap GPR:$src))]>; 954 955def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 956 "rev16", ".w\t$dst, $src", 957 [(set GPR:$dst, 958 (or (and (srl GPR:$src, (i32 8)), 0xFF), 959 (or (and (shl GPR:$src, (i32 8)), 0xFF00), 960 (or (and (srl GPR:$src, (i32 8)), 0xFF0000), 961 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>; 962 963def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 964 "revsh", ".w\t$dst, $src", 965 [(set GPR:$dst, 966 (sext_inreg 967 (or (srl (and GPR:$src, 0xFF00), (i32 8)), 968 (shl GPR:$src, (i32 8))), i16))]>; 969 970def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 971 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt", 972 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 973 (and (shl GPR:$src2, (i32 imm:$shamt)), 974 0xFFFF0000)))]>; 975 976// Alternate cases for PKHBT where identities eliminate some nodes. 977def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 978 (t2PKHBT GPR:$src1, GPR:$src2, 0)>; 979def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 980 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; 981 982def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 983 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt", 984 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 985 (and (sra GPR:$src2, imm16_31:$shamt), 986 0xFFFF)))]>; 987 988// Alternate cases for PKHTB where identities eliminate some nodes. Note that 989// a shift amount of 0 is *not legal* here, it is PKHBT instead. 990def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), 991 (t2PKHTB GPR:$src1, GPR:$src2, 16)>; 992def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), 993 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 994 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; 995 996//===----------------------------------------------------------------------===// 997// Comparison Instructions... 998// 999 1000defm t2CMP : T2I_cmp_is<"cmp", 1001 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 1002defm t2CMPz : T2I_cmp_is<"cmp", 1003 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; 1004 1005defm t2CMN : T2I_cmp_is<"cmn", 1006 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 1007defm t2CMNz : T2I_cmp_is<"cmn", 1008 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 1009 1010def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 1011 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 1012 1013def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm), 1014 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 1015 1016defm t2TST : T2I_cmp_is<"tst", 1017 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>; 1018defm t2TEQ : T2I_cmp_is<"teq", 1019 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>; 1020 1021// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero. 1022// Short range conditional branch. Looks awesome for loops. Need to figure 1023// out how to use this one. 1024 1025 1026// Conditional moves 1027// FIXME: should be able to write a pattern for ARMcmov, but can't use 1028// a two-value operand where a dag node expects two operands. :( 1029def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr, 1030 "mov", ".w\t$dst, $true", 1031 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 1032 RegConstraint<"$false = $dst">; 1033 1034def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true), 1035 IIC_iCMOVi, "mov", ".w\t$dst, $true", 1036[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 1037 RegConstraint<"$false = $dst">; 1038 1039def t2MOVCClsl : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1040 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>, 1041 RegConstraint<"$false = $dst">; 1042def t2MOVCClsr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1043 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>, 1044 RegConstraint<"$false = $dst">; 1045def t2MOVCCasr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1046 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>, 1047 RegConstraint<"$false = $dst">; 1048def t2MOVCCror : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1049 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>, 1050 RegConstraint<"$false = $dst">; 1051 1052//===----------------------------------------------------------------------===// 1053// TLS Instructions 1054// 1055 1056// __aeabi_read_tp preserves the registers r1-r3. 1057let isCall = 1, 1058 Defs = [R0, R12, LR, CPSR] in { 1059 def t2TPsoft : T2XI<(outs), (ins), IIC_Br, 1060 "bl\t__aeabi_read_tp", 1061 [(set R0, ARMthread_pointer)]>; 1062} 1063 1064//===----------------------------------------------------------------------===// 1065// SJLJ Exception handling intrinsics 1066// eh_sjlj_setjmp() is an instruction sequence to store the return 1067// address and save #0 in R0 for the non-longjmp case. 1068// Since by its nature we may be coming from some other function to get 1069// here, and we're using the stack frame for the containing function to 1070// save/restore registers, we can't keep anything live in regs across 1071// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 1072// when we get here from a longjmp(). We force everthing out of registers 1073// except for our own input by listing the relevant registers in Defs. By 1074// doing so, we also cause the prologue/epilogue code to actively preserve 1075// all of the callee-saved resgisters, which is exactly what we want. 1076let Defs = 1077 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0, 1078 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 1079 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, 1080 D31 ] in { 1081 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src), 1082 AddrModeNone, SizeSpecial, NoItinerary, 1083 "str.w\tsp, [$src, #+8] @ eh_setjmp begin\n" 1084 "\tadr\tr12, 0f\n" 1085 "\torr\tr12, #1\n" 1086 "\tstr.w\tr12, [$src, #+4]\n" 1087 "\tmovs\tr0, #0\n" 1088 "\tb\t1f\n" 1089 "0:\tmovs\tr0, #1 @ eh_setjmp end\n" 1090 "1:", "", 1091 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>; 1092} 1093 1094 1095 1096//===----------------------------------------------------------------------===// 1097// Control-Flow Instructions 1098// 1099 1100// FIXME: remove when we have a way to marking a MI with these properties. 1101// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 1102// operand list. 1103// FIXME: Should pc be an implicit operand like PICADD, etc? 1104let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1105 hasExtraDefRegAllocReq = 1 in 1106 def t2LDM_RET : T2XI<(outs), 1107 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 1108 IIC_Br, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", 1109 []>; 1110 1111let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 1112let isPredicable = 1 in 1113def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br, 1114 "b.w\t$target", 1115 [(br bb:$target)]>; 1116 1117let isNotDuplicable = 1, isIndirectBranch = 1 in { 1118def t2BR_JT : 1119 T2JTI<(outs), 1120 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id), 1121 IIC_Br, "mov\tpc, $target\n$jt", 1122 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>; 1123 1124// FIXME: Add a non-pc based case that can be predicated. 1125def t2TBB : 1126 T2JTI<(outs), 1127 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 1128 IIC_Br, "tbb\t$index\n$jt", []>; 1129 1130def t2TBH : 1131 T2JTI<(outs), 1132 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 1133 IIC_Br, "tbh\t$index\n$jt", []>; 1134} // isNotDuplicable, isIndirectBranch 1135 1136} // isBranch, isTerminator, isBarrier 1137 1138// FIXME: should be able to write a pattern for ARMBrcond, but can't use 1139// a two-value operand where a dag node expects two operands. :( 1140let isBranch = 1, isTerminator = 1 in 1141def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 1142 "b", ".w\t$target", 1143 [/*(ARMbrcond bb:$target, imm:$cc)*/]>; 1144 1145 1146// IT block 1147def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 1148 AddrModeNone, Size2Bytes, IIC_iALUx, 1149 "it$mask\t$cc", "", []>; 1150 1151//===----------------------------------------------------------------------===// 1152// Non-Instruction Patterns 1153// 1154 1155// Two piece so_imms. 1156def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS), 1157 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 1158 (t2_so_imm2part_2 imm:$RHS))>; 1159def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS), 1160 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 1161 (t2_so_imm2part_2 imm:$RHS))>; 1162def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS), 1163 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 1164 (t2_so_imm2part_2 imm:$RHS))>; 1165def : T2Pat<(sub GPR:$LHS, t2_so_imm2part:$RHS), 1166 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 1167 (t2_so_imm2part_2 imm:$RHS))>; 1168 1169// ConstantPool, GlobalAddress, and JumpTable 1170def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>; 1171def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 1172def : T2Pat<(ARMWrapper tblockaddress:$dst), (t2LEApcrel tblockaddress:$dst)>; 1173def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1174 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 1175 1176// 32-bit immediate using movw + movt. 1177// This is a single pseudo instruction to make it re-materializable. Remove 1178// when we can do generalized remat. 1179let isReMaterializable = 1 in 1180def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi, 1181 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}", 1182 [(set GPR:$dst, (i32 imm:$src))]>; 1183