ARMInstrThumb2.td revision 861986401e05e437cb33bfd8320d510b956fe41e
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb2 instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// IT block predicate field 15def it_pred : Operand<i32> { 16 let PrintMethod = "printPredicateOperand"; 17} 18 19// IT block condition mask 20def it_mask : Operand<i32> { 21 let PrintMethod = "printThumbITMask"; 22} 23 24// Table branch address 25def tb_addrmode : Operand<i32> { 26 let PrintMethod = "printTBAddrMode"; 27} 28 29// Shifted operands. No register controlled shifts for Thumb2. 30// Note: We do not support rrx shifted operands yet. 31def t2_so_reg : Operand<i32>, // reg imm 32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 33 [shl,srl,sra,rotr]> { 34 let PrintMethod = "printT2SOOperand"; 35 let MIOperandInfo = (ops GPR, i32imm); 36} 37 38// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 39def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 41}]>; 42 43// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 44def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 46}]>; 47 48// t2_so_imm - Match a 32-bit immediate operand, which is an 49// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 50// immediate splatted into multiple bytes of the word. t2_so_imm values are 51// represented in the imm field in the same 12-bit form that they are encoded 52// into t2_so_imm instructions: the 8-bit immediate is the least significant bits 53// [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. 54def t2_so_imm : Operand<i32>, 55 PatLeaf<(imm), [{ 56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1; 57}]>; 58 59// t2_so_imm_not - Match an immediate that is a complement 60// of a t2_so_imm. 61def t2_so_imm_not : Operand<i32>, 62 PatLeaf<(imm), [{ 63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 64}], t2_so_imm_not_XFORM>; 65 66// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 67def t2_so_imm_neg : Operand<i32>, 68 PatLeaf<(imm), [{ 69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1; 70}], t2_so_imm_neg_XFORM>; 71 72/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31]. 73def imm1_31 : PatLeaf<(i32 imm), [{ 74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32; 75}]>; 76 77/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 78def imm0_4095 : Operand<i32>, 79 PatLeaf<(i32 imm), [{ 80 return (uint32_t)N->getZExtValue() < 4096; 81}]>; 82 83def imm0_4095_neg : PatLeaf<(i32 imm), [{ 84 return (uint32_t)(-N->getZExtValue()) < 4096; 85}], imm_neg_XFORM>; 86 87def imm0_255_neg : PatLeaf<(i32 imm), [{ 88 return (uint32_t)(-N->getZExtValue()) < 255; 89}], imm_neg_XFORM>; 90 91/// imm0_65535 predicate - True if the 32-bit immediate is in the range 92/// [0.65535]. 93def imm0_65535 : PatLeaf<(i32 imm), [{ 94 return (uint32_t)N->getZExtValue() < 65536; 95}]>; 96 97/// Split a 32-bit immediate into two 16 bit parts. 98def t2_lo16 : SDNodeXForm<imm, [{ 99 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff, 100 MVT::i32); 101}]>; 102 103def t2_hi16 : SDNodeXForm<imm, [{ 104 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 105}]>; 106 107def t2_lo16AllZero : PatLeaf<(i32 imm), [{ 108 // Returns true if all low 16-bits are 0. 109 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 110 }], t2_hi16>; 111 112 113// Define Thumb2 specific addressing modes. 114 115// t2addrmode_imm12 := reg + imm12 116def t2addrmode_imm12 : Operand<i32>, 117 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 118 let PrintMethod = "printT2AddrModeImm12Operand"; 119 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 120} 121 122// t2addrmode_imm8 := reg - imm8 123def t2addrmode_imm8 : Operand<i32>, 124 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 125 let PrintMethod = "printT2AddrModeImm8Operand"; 126 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 127} 128 129def t2am_imm8_offset : Operand<i32>, 130 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{ 131 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 132} 133 134// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 135def t2addrmode_imm8s4 : Operand<i32>, 136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> { 137 let PrintMethod = "printT2AddrModeImm8s4Operand"; 138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 139} 140 141// t2addrmode_so_reg := reg + (reg << imm2) 142def t2addrmode_so_reg : Operand<i32>, 143 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 144 let PrintMethod = "printT2AddrModeSoRegOperand"; 145 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 146} 147 148 149//===----------------------------------------------------------------------===// 150// Multiclass helpers... 151// 152 153/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 154/// unary operation that produces a value. These are predicable and can be 155/// changed to modify CPSR. 156multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{ 157 // shifted imm 158 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iALU, 159 opc, " $dst, $src", 160 [(set GPR:$dst, (opnode t2_so_imm:$src))]> { 161 let isAsCheapAsAMove = Cheap; 162 let isReMaterializable = ReMat; 163 } 164 // register 165 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, 166 opc, ".w $dst, $src", 167 [(set GPR:$dst, (opnode GPR:$src))]>; 168 // shifted register 169 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iALU, 170 opc, ".w $dst, $src", 171 [(set GPR:$dst, (opnode t2_so_reg:$src))]>; 172} 173 174/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 175// binary operation that produces a value. These are predicable and can be 176/// changed to modify CPSR. 177multiclass T2I_bin_irs<string opc, PatFrag opnode, 178 bit Commutable = 0, string wide =""> { 179 // shifted imm 180 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, 181 opc, " $dst, $lhs, $rhs", 182 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 183 // register 184 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, 185 opc, !strconcat(wide, " $dst, $lhs, $rhs"), 186 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 187 let isCommutable = Commutable; 188 } 189 // shifted register 190 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, 191 opc, !strconcat(wide, " $dst, $lhs, $rhs"), 192 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 193} 194 195/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 196// the ".w" prefix to indicate that they are wide. 197multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> : 198 T2I_bin_irs<opc, opnode, Commutable, ".w">; 199 200/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 201/// reversed. It doesn't define the 'rr' form since it's handled by its 202/// T2I_bin_irs counterpart. 203multiclass T2I_rbin_is<string opc, PatFrag opnode> { 204 // shifted imm 205 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALU, 206 opc, ".w $dst, $rhs, $lhs", 207 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 208 // shifted register 209 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALU, 210 opc, " $dst, $rhs, $lhs", 211 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 212} 213 214/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 215/// instruction modifies the CPSR register. 216let Defs = [CPSR] in { 217multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> { 218 // shifted imm 219 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, 220 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 221 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 222 // register 223 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, 224 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 225 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 226 let isCommutable = Commutable; 227 } 228 // shifted register 229 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, 230 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 231 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 232} 233} 234 235/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 236/// patterns for a binary operation that produces a value. 237multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> { 238 // shifted imm 239 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, 240 opc, ".w $dst, $lhs, $rhs", 241 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 242 // 12-bit imm 243 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALU, 244 !strconcat(opc, "w"), " $dst, $lhs, $rhs", 245 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; 246 // register 247 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, 248 opc, ".w $dst, $lhs, $rhs", 249 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 250 let isCommutable = Commutable; 251 } 252 // shifted register 253 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, 254 opc, ".w $dst, $lhs, $rhs", 255 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 256} 257 258/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 259/// binary operation that produces a value and use and define the carry bit. 260/// It's not predicable. 261let Uses = [CPSR] in { 262multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> { 263 // shifted imm 264 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, 265 opc, " $dst, $lhs, $rhs", 266 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 267 Requires<[IsThumb2, CarryDefIsUnused]>; 268 // register 269 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, 270 opc, ".w $dst, $lhs, $rhs", 271 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 272 Requires<[IsThumb2, CarryDefIsUnused]> { 273 let isCommutable = Commutable; 274 } 275 // shifted register 276 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, 277 opc, ".w $dst, $lhs, $rhs", 278 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 279 Requires<[IsThumb2, CarryDefIsUnused]>; 280 // Carry setting variants 281 // shifted imm 282 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, 283 !strconcat(opc, "s $dst, $lhs, $rhs"), 284 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 285 Requires<[IsThumb2, CarryDefIsUsed]> { 286 let Defs = [CPSR]; 287 } 288 // register 289 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, 290 !strconcat(opc, "s.w $dst, $lhs, $rhs"), 291 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 292 Requires<[IsThumb2, CarryDefIsUsed]> { 293 let Defs = [CPSR]; 294 let isCommutable = Commutable; 295 } 296 // shifted register 297 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, 298 !strconcat(opc, "s.w $dst, $lhs, $rhs"), 299 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 300 Requires<[IsThumb2, CarryDefIsUsed]> { 301 let Defs = [CPSR]; 302 } 303} 304} 305 306/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit. 307let Defs = [CPSR] in { 308multiclass T2I_rbin_s_is<string opc, PatFrag opnode> { 309 // shifted imm 310 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), IIC_iALU, 311 !strconcat(opc, "${s}.w $dst, $rhs, $lhs"), 312 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 313 // shifted register 314 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), IIC_iALU, 315 !strconcat(opc, "${s} $dst, $rhs, $lhs"), 316 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 317} 318} 319 320/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 321// rotate operation that produces a value. 322multiclass T2I_sh_ir<string opc, PatFrag opnode> { 323 // 5-bit imm 324 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU, 325 opc, ".w $dst, $lhs, $rhs", 326 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>; 327 // register 328 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, 329 opc, ".w $dst, $lhs, $rhs", 330 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; 331} 332 333/// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 334/// patterns. Similar to T2I_bin_irs except the instruction does not produce 335/// a explicit result, only implicitly set CPSR. 336let Defs = [CPSR] in { 337multiclass T2I_cmp_is<string opc, PatFrag opnode> { 338 // shifted imm 339 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, 340 opc, ".w $lhs, $rhs", 341 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>; 342 // register 343 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, 344 opc, ".w $lhs, $rhs", 345 [(opnode GPR:$lhs, GPR:$rhs)]>; 346 // shifted register 347 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, 348 opc, ".w $lhs, $rhs", 349 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>; 350} 351} 352 353/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 354multiclass T2I_ld<string opc, PatFrag opnode> { 355 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoad, 356 opc, ".w $dst, $addr", 357 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>; 358 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoad, 359 opc, " $dst, $addr", 360 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>; 361 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoad, 362 opc, ".w $dst, $addr", 363 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>; 364 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoad, 365 opc, ".w $dst, $addr", 366 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>; 367} 368 369/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 370multiclass T2I_st<string opc, PatFrag opnode> { 371 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStore, 372 opc, ".w $src, $addr", 373 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>; 374 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStore, 375 opc, " $src, $addr", 376 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>; 377 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStore, 378 opc, ".w $src, $addr", 379 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>; 380} 381 382/// T2I_picld - Defines the PIC load pattern. 383class T2I_picld<string opc, PatFrag opnode> : 384 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoad, 385 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr", 386 [(set GPR:$dst, (opnode addrmodepc:$addr))]>; 387 388/// T2I_picst - Defines the PIC store pattern. 389class T2I_picst<string opc, PatFrag opnode> : 390 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStore, 391 !strconcat("${addr:label}:\n\t", opc), " $src, $addr", 392 [(opnode GPR:$src, addrmodepc:$addr)]>; 393 394 395/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a 396/// register and one whose operand is a register rotated by 8/16/24. 397multiclass T2I_unary_rrot<string opc, PatFrag opnode> { 398 def r : T2I<(outs GPR:$dst), (ins GPR:$Src), IIC_iALU, 399 opc, ".w $dst, $Src", 400 [(set GPR:$dst, (opnode GPR:$Src))]>; 401 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), IIC_iALU, 402 opc, ".w $dst, $Src, ror $rot", 403 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>; 404} 405 406/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a 407/// register and one whose operand is a register rotated by 8/16/24. 408multiclass T2I_bin_rrot<string opc, PatFrag opnode> { 409 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALU, 410 opc, " $dst, $LHS, $RHS", 411 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>; 412 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 413 IIC_iALU, opc, " $dst, $LHS, $RHS, ror $rot", 414 [(set GPR:$dst, (opnode GPR:$LHS, 415 (rotr GPR:$RHS, rot_imm:$rot)))]>; 416} 417 418//===----------------------------------------------------------------------===// 419// Instructions 420//===----------------------------------------------------------------------===// 421 422//===----------------------------------------------------------------------===// 423// Miscellaneous Instructions. 424// 425 426// LEApcrel - Load a pc-relative address into a register without offending the 427// assembler. 428def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALU, 429 "adr$p.w $dst, #$label", []>; 430 431def t2LEApcrelJT : T2XI<(outs GPR:$dst), 432 (ins i32imm:$label, i32imm:$id, pred:$p), IIC_iALU, 433 "adr$p.w $dst, #${label}_${id:no_hash}", []>; 434 435 436// ADD r, sp, {so_imm|i12} 437def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), IIC_iALU, 438 "add", ".w $dst, $sp, $imm", []>; 439def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), IIC_iALU, 440 "addw", " $dst, $sp, $imm", []>; 441 442// ADD r, sp, so_reg 443def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), IIC_iALU, 444 "add", ".w $dst, $sp, $rhs", []>; 445 446// SUB r, sp, {so_imm|i12} 447def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), IIC_iALU, 448 "sub", ".w $dst, $sp, $imm", []>; 449def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), IIC_iALU, 450 "subw", " $dst, $sp, $imm", []>; 451 452// SUB r, sp, so_reg 453def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), IIC_iALU, 454 "sub", " $dst, $sp, $rhs", []>; 455 456 457// Pseudo instruction that will expand into a t2SUBrSPi + a copy. 458let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 459def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 460 NoItinerary, "@ sub.w $dst, $sp, $imm", []>; 461def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 462 NoItinerary, "@ subw $dst, $sp, $imm", []>; 463def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 464 NoItinerary, "@ sub $dst, $sp, $rhs", []>; 465} // usesCustomDAGSchedInserter 466 467 468//===----------------------------------------------------------------------===// 469// Load / store Instructions. 470// 471 472// Load 473let canFoldAsLoad = 1 in 474defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>; 475 476// Loads with zero extension 477defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>; 478defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>; 479 480// Loads with sign extension 481defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>; 482defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>; 483 484let mayLoad = 1 in { 485// Load doubleword 486def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr), 487 IIC_iLoad, "ldrd", " $dst, $addr", []>; 488def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoad, 489 "ldrd", " $dst, $addr", []>; 490} 491 492// zextload i1 -> zextload i8 493def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 494 (t2LDRBi12 t2addrmode_imm12:$addr)>; 495def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr), 496 (t2LDRBi8 t2addrmode_imm8:$addr)>; 497def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 498 (t2LDRBs t2addrmode_so_reg:$addr)>; 499def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 500 (t2LDRBpci tconstpool:$addr)>; 501 502// extload -> zextload 503// FIXME: Reduce the number of patterns by legalizing extload to zextload 504// earlier? 505def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 506 (t2LDRBi12 t2addrmode_imm12:$addr)>; 507def : T2Pat<(extloadi1 t2addrmode_imm8:$addr), 508 (t2LDRBi8 t2addrmode_imm8:$addr)>; 509def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 510 (t2LDRBs t2addrmode_so_reg:$addr)>; 511def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 512 (t2LDRBpci tconstpool:$addr)>; 513 514def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 515 (t2LDRBi12 t2addrmode_imm12:$addr)>; 516def : T2Pat<(extloadi8 t2addrmode_imm8:$addr), 517 (t2LDRBi8 t2addrmode_imm8:$addr)>; 518def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 519 (t2LDRBs t2addrmode_so_reg:$addr)>; 520def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 521 (t2LDRBpci tconstpool:$addr)>; 522 523def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 524 (t2LDRHi12 t2addrmode_imm12:$addr)>; 525def : T2Pat<(extloadi16 t2addrmode_imm8:$addr), 526 (t2LDRHi8 t2addrmode_imm8:$addr)>; 527def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 528 (t2LDRHs t2addrmode_so_reg:$addr)>; 529def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 530 (t2LDRHpci tconstpool:$addr)>; 531 532// Indexed loads 533let mayLoad = 1 in { 534def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 535 (ins t2addrmode_imm8:$addr), 536 AddrModeT2_i8, IndexModePre, IIC_iLoad, 537 "ldr", " $dst, $addr!", "$addr.base = $base_wb", 538 []>; 539 540def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 541 (ins GPR:$base, t2am_imm8_offset:$offset), 542 AddrModeT2_i8, IndexModePost, IIC_iLoad, 543 "ldr", " $dst, [$base], $offset", "$base = $base_wb", 544 []>; 545 546def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 547 (ins t2addrmode_imm8:$addr), 548 AddrModeT2_i8, IndexModePre, IIC_iLoad, 549 "ldrb", " $dst, $addr!", "$addr.base = $base_wb", 550 []>; 551def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 552 (ins GPR:$base, t2am_imm8_offset:$offset), 553 AddrModeT2_i8, IndexModePost, IIC_iLoad, 554 "ldrb", " $dst, [$base], $offset", "$base = $base_wb", 555 []>; 556 557def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 558 (ins t2addrmode_imm8:$addr), 559 AddrModeT2_i8, IndexModePre, IIC_iLoad, 560 "ldrh", " $dst, $addr!", "$addr.base = $base_wb", 561 []>; 562def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 563 (ins GPR:$base, t2am_imm8_offset:$offset), 564 AddrModeT2_i8, IndexModePost, IIC_iLoad, 565 "ldrh", " $dst, [$base], $offset", "$base = $base_wb", 566 []>; 567 568def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 569 (ins t2addrmode_imm8:$addr), 570 AddrModeT2_i8, IndexModePre, IIC_iLoad, 571 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb", 572 []>; 573def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 574 (ins GPR:$base, t2am_imm8_offset:$offset), 575 AddrModeT2_i8, IndexModePost, IIC_iLoad, 576 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb", 577 []>; 578 579def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 580 (ins t2addrmode_imm8:$addr), 581 AddrModeT2_i8, IndexModePre, IIC_iLoad, 582 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb", 583 []>; 584def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 585 (ins GPR:$base, t2am_imm8_offset:$offset), 586 AddrModeT2_i8, IndexModePost, IIC_iLoad, 587 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb", 588 []>; 589} 590 591// Store 592defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; 593defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 594defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 595 596// Store doubleword 597let mayLoad = 1 in 598def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr), IIC_iStore, 599 "strd", " $src, $addr", []>; 600 601// Indexed stores 602def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb), 603 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 604 AddrModeT2_i8, IndexModePre, IIC_iStore, 605 "str", " $src, [$base, $offset]!", "$base = $base_wb", 606 [(set GPR:$base_wb, 607 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 608 609def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb), 610 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 611 AddrModeT2_i8, IndexModePost, IIC_iStore, 612 "str", " $src, [$base], $offset", "$base = $base_wb", 613 [(set GPR:$base_wb, 614 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 615 616def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb), 617 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 618 AddrModeT2_i8, IndexModePre, IIC_iStore, 619 "strh", " $src, [$base, $offset]!", "$base = $base_wb", 620 [(set GPR:$base_wb, 621 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 622 623def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb), 624 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 625 AddrModeT2_i8, IndexModePost, IIC_iStore, 626 "strh", " $src, [$base], $offset", "$base = $base_wb", 627 [(set GPR:$base_wb, 628 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 629 630def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb), 631 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 632 AddrModeT2_i8, IndexModePre, IIC_iStore, 633 "strb", " $src, [$base, $offset]!", "$base = $base_wb", 634 [(set GPR:$base_wb, 635 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 636 637def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb), 638 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 639 AddrModeT2_i8, IndexModePost, IIC_iStore, 640 "strb", " $src, [$base], $offset", "$base = $base_wb", 641 [(set GPR:$base_wb, 642 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 643 644 645// FIXME: ldrd / strd pre / post variants 646 647//===----------------------------------------------------------------------===// 648// Load / store multiple Instructions. 649// 650 651let mayLoad = 1 in 652def t2LDM : T2XI<(outs), 653 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 654 IIC_iLoad, "ldm${addr:submode}${p} $addr, $dst1", []>; 655 656let mayStore = 1 in 657def t2STM : T2XI<(outs), 658 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), 659 IIC_iStore, "stm${addr:submode}${p} $addr, $src1", []>; 660 661//===----------------------------------------------------------------------===// 662// Move Instructions. 663// 664 665let neverHasSideEffects = 1 in 666def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, 667 "mov", ".w $dst, $src", []>; 668 669let isReMaterializable = 1, isAsCheapAsAMove = 1 in 670def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iALU, 671 "mov", ".w $dst, $src", 672 [(set GPR:$dst, t2_so_imm:$src)]>; 673 674let isReMaterializable = 1, isAsCheapAsAMove = 1 in 675def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iALU, 676 "movw", " $dst, $src", 677 [(set GPR:$dst, imm0_65535:$src)]>; 678 679// FIXME: Also available in ARM mode. 680let Constraints = "$src = $dst" in 681def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iALU, 682 "movt", " $dst, $imm", 683 [(set GPR:$dst, 684 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>; 685 686//===----------------------------------------------------------------------===// 687// Extend Instructions. 688// 689 690// Sign extenders 691 692defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 693defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 694 695defm t2SXTAB : T2I_bin_rrot<"sxtab", 696 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 697defm t2SXTAH : T2I_bin_rrot<"sxtah", 698 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 699 700// TODO: SXT(A){B|H}16 701 702// Zero extenders 703 704let AddedComplexity = 16 in { 705defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 706defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 707defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 708 709def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 710 (t2UXTB16r_rot GPR:$Src, 24)>; 711def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 712 (t2UXTB16r_rot GPR:$Src, 8)>; 713 714defm t2UXTAB : T2I_bin_rrot<"uxtab", 715 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 716defm t2UXTAH : T2I_bin_rrot<"uxtah", 717 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 718} 719 720//===----------------------------------------------------------------------===// 721// Arithmetic Instructions. 722// 723 724defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 725defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 726 727// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 728defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; 729defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 730 731defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>; 732defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>; 733 734// RSB 735defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 736defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 737 738// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 739let AddedComplexity = 1 in 740def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), 741 (t2SUBri GPR:$src, imm0_255_neg:$imm)>; 742def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 743 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 744def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 745 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 746 747 748//===----------------------------------------------------------------------===// 749// Shift and rotate Instructions. 750// 751 752defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>; 753defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>; 754defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; 755defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; 756 757def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, 758 "rrx", ".w $dst, $src", 759 [(set GPR:$dst, (ARMrrx GPR:$src))]>; 760 761let Defs = [CPSR] in { 762def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, 763 "lsrs.w $dst, $src, #1", 764 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; 765def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, 766 "asrs.w $dst, $src, #1", 767 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; 768} 769 770//===----------------------------------------------------------------------===// 771// Bitwise Instructions. 772// 773 774defm t2AND : T2I_bin_w_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 775defm t2ORR : T2I_bin_w_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 776defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 777 778defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 779 780let Constraints = "$src = $dst" in 781def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), IIC_iALU, 782 "bfc", " $dst, $imm", 783 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>; 784 785// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1) 786 787/* 788defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>; 789*/ 790// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 791def t2ORNri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, 792 "orn", " $dst, $lhs, $rhs", 793 [(set GPR:$dst, (or GPR:$lhs, (not t2_so_imm:$rhs)))]>, 794 Requires<[IsThumb2, IsNotDarwin]>; 795 796def t2ORNrr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, 797 "orn", " $dst, $lhs, $rhs", 798 [(set GPR:$dst, (or GPR:$lhs, (not GPR:$rhs)))]>; 799def t2ORNrs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, 800 "orn", " $dst, $lhs, $rhs", 801 [(set GPR:$dst, (or GPR:$lhs, (not t2_so_reg:$rhs)))]>; 802 803// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 804let AddedComplexity = 1 in 805defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>; 806 807 808def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm), 809 (t2BICri GPR:$src, t2_so_imm_not:$imm)>; 810 811// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 812def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm), 813 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>, 814 Requires<[IsThumb2, IsNotDarwin]>; 815 816def : T2Pat<(t2_so_imm_not:$src), 817 (t2MVNi t2_so_imm_not:$src)>; 818 819//===----------------------------------------------------------------------===// 820// Multiply Instructions. 821// 822let isCommutable = 1 in 823def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU, 824 "mul", " $dst, $a, $b", 825 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; 826 827def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iALU, 828 "mla", " $dst, $a, $b, $c", 829 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; 830 831def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iALU, 832 "mls", " $dst, $a, $b, $c", 833 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>; 834 835// Extra precision multiplies with low / high results 836let neverHasSideEffects = 1 in { 837let isCommutable = 1 in { 838def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iALU, 839 "smull", " $ldst, $hdst, $a, $b", []>; 840 841def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iALU, 842 "umull", " $ldst, $hdst, $a, $b", []>; 843} 844 845// Multiply + accumulate 846def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iALU, 847 "smlal", " $ldst, $hdst, $a, $b", []>; 848 849def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iALU, 850 "umlal", " $ldst, $hdst, $a, $b", []>; 851 852def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iALU, 853 "umaal", " $ldst, $hdst, $a, $b", []>; 854} // neverHasSideEffects 855 856// Most significant word multiply 857def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU, 858 "smmul", " $dst, $a, $b", 859 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>; 860 861def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iALU, 862 "smmla", " $dst, $a, $b, $c", 863 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>; 864 865 866def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iALU, 867 "smmls", " $dst, $a, $b, $c", 868 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>; 869 870multiclass T2I_smul<string opc, PatFrag opnode> { 871 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU, 872 !strconcat(opc, "bb"), " $dst, $a, $b", 873 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 874 (sext_inreg GPR:$b, i16)))]>; 875 876 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU, 877 !strconcat(opc, "bt"), " $dst, $a, $b", 878 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 879 (sra GPR:$b, (i32 16))))]>; 880 881 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU, 882 !strconcat(opc, "tb"), " $dst, $a, $b", 883 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 884 (sext_inreg GPR:$b, i16)))]>; 885 886 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU, 887 !strconcat(opc, "tt"), " $dst, $a, $b", 888 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 889 (sra GPR:$b, (i32 16))))]>; 890 891 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU, 892 !strconcat(opc, "wb"), " $dst, $a, $b", 893 [(set GPR:$dst, (sra (opnode GPR:$a, 894 (sext_inreg GPR:$b, i16)), (i32 16)))]>; 895 896 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU, 897 !strconcat(opc, "wt"), " $dst, $a, $b", 898 [(set GPR:$dst, (sra (opnode GPR:$a, 899 (sra GPR:$b, (i32 16))), (i32 16)))]>; 900} 901 902 903multiclass T2I_smla<string opc, PatFrag opnode> { 904 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU, 905 !strconcat(opc, "bb"), " $dst, $a, $b, $acc", 906 [(set GPR:$dst, (add GPR:$acc, 907 (opnode (sext_inreg GPR:$a, i16), 908 (sext_inreg GPR:$b, i16))))]>; 909 910 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU, 911 !strconcat(opc, "bt"), " $dst, $a, $b, $acc", 912 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 913 (sra GPR:$b, (i32 16)))))]>; 914 915 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU, 916 !strconcat(opc, "tb"), " $dst, $a, $b, $acc", 917 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 918 (sext_inreg GPR:$b, i16))))]>; 919 920 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU, 921 !strconcat(opc, "tt"), " $dst, $a, $b, $acc", 922 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 923 (sra GPR:$b, (i32 16)))))]>; 924 925 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU, 926 !strconcat(opc, "wb"), " $dst, $a, $b, $acc", 927 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 928 (sext_inreg GPR:$b, i16)), (i32 16))))]>; 929 930 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU, 931 !strconcat(opc, "wt"), " $dst, $a, $b, $acc", 932 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 933 (sra GPR:$b, (i32 16))), (i32 16))))]>; 934} 935 936defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 937defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 938 939// TODO: Halfword multiple accumulate long: SMLAL<x><y> 940// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 941 942 943//===----------------------------------------------------------------------===// 944// Misc. Arithmetic Instructions. 945// 946 947def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, 948 "clz", " $dst, $src", 949 [(set GPR:$dst, (ctlz GPR:$src))]>; 950 951def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, 952 "rev", ".w $dst, $src", 953 [(set GPR:$dst, (bswap GPR:$src))]>; 954 955def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, 956 "rev16", ".w $dst, $src", 957 [(set GPR:$dst, 958 (or (and (srl GPR:$src, (i32 8)), 0xFF), 959 (or (and (shl GPR:$src, (i32 8)), 0xFF00), 960 (or (and (srl GPR:$src, (i32 8)), 0xFF0000), 961 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>; 962 963def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, 964 "revsh", ".w $dst, $src", 965 [(set GPR:$dst, 966 (sext_inreg 967 (or (srl (and GPR:$src, 0xFFFF), (i32 8)), 968 (shl GPR:$src, (i32 8))), i16))]>; 969 970def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 971 IIC_iALU, "pkhbt", " $dst, $src1, $src2, LSL $shamt", 972 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 973 (and (shl GPR:$src2, (i32 imm:$shamt)), 974 0xFFFF0000)))]>; 975 976// Alternate cases for PKHBT where identities eliminate some nodes. 977def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 978 (t2PKHBT GPR:$src1, GPR:$src2, 0)>; 979def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 980 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; 981 982def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 983 IIC_iALU, "pkhtb", " $dst, $src1, $src2, ASR $shamt", 984 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 985 (and (sra GPR:$src2, imm16_31:$shamt), 986 0xFFFF)))]>; 987 988// Alternate cases for PKHTB where identities eliminate some nodes. Note that 989// a shift amount of 0 is *not legal* here, it is PKHBT instead. 990def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), 991 (t2PKHTB GPR:$src1, GPR:$src2, 16)>; 992def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), 993 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 994 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; 995 996//===----------------------------------------------------------------------===// 997// Comparison Instructions... 998// 999 1000defm t2CMP : T2I_cmp_is<"cmp", 1001 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 1002defm t2CMPz : T2I_cmp_is<"cmp", 1003 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; 1004 1005defm t2CMN : T2I_cmp_is<"cmn", 1006 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 1007defm t2CMNz : T2I_cmp_is<"cmn", 1008 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 1009 1010def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 1011 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 1012 1013def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm), 1014 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 1015 1016defm t2TST : T2I_cmp_is<"tst", 1017 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>; 1018defm t2TEQ : T2I_cmp_is<"teq", 1019 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>; 1020 1021// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero. 1022// Short range conditional branch. Looks awesome for loops. Need to figure 1023// out how to use this one. 1024 1025 1026// Conditional moves 1027// FIXME: should be able to write a pattern for ARMcmov, but can't use 1028// a two-value operand where a dag node expects two operands. :( 1029def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iALU, 1030 "mov", ".w $dst, $true", 1031 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 1032 RegConstraint<"$false = $dst">; 1033 1034def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true), IIC_iALU, 1035 "mov", ".w $dst, $true", 1036[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 1037 RegConstraint<"$false = $dst">; 1038 1039def t2MOVCClsl : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1040 IIC_iALU, "lsl", ".w $dst, $true, $rhs", []>, 1041 RegConstraint<"$false = $dst">; 1042def t2MOVCClsr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1043 IIC_iALU, "lsr", ".w $dst, $true, $rhs", []>, 1044 RegConstraint<"$false = $dst">; 1045def t2MOVCCasr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1046 IIC_iALU, "asr", ".w $dst, $true, $rhs", []>, 1047 RegConstraint<"$false = $dst">; 1048def t2MOVCCror : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1049 IIC_iALU, "ror", ".w $dst, $true, $rhs", []>, 1050 RegConstraint<"$false = $dst">; 1051 1052//===----------------------------------------------------------------------===// 1053// TLS Instructions 1054// 1055 1056// __aeabi_read_tp preserves the registers r1-r3. 1057let isCall = 1, 1058 Defs = [R0, R12, LR, CPSR] in { 1059 def t2TPsoft : T2XI<(outs), (ins), IIC_Br, 1060 "bl __aeabi_read_tp", 1061 [(set R0, ARMthread_pointer)]>; 1062} 1063 1064//===----------------------------------------------------------------------===// 1065// Control-Flow Instructions 1066// 1067 1068// FIXME: remove when we have a way to marking a MI with these properties. 1069// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 1070// operand list. 1071// FIXME: Should pc be an implicit operand like PICADD, etc? 1072let isReturn = 1, isTerminator = 1, mayLoad = 1 in 1073 def t2LDM_RET : T2XI<(outs), 1074 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 1075 IIC_iLoad, "ldm${addr:submode}${p} $addr, $dst1", 1076 []>; 1077 1078let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 1079let isPredicable = 1 in 1080def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br, 1081 "b.w $target", 1082 [(br bb:$target)]>; 1083 1084let isNotDuplicable = 1, isIndirectBranch = 1 in { 1085def t2BR_JT : 1086 T2JTI<(outs), 1087 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id), 1088 IIC_Br, "mov pc, $target\n$jt", 1089 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>; 1090 1091// FIXME: Add a non-pc based case that can be predicated. 1092def t2TBB : 1093 T2JTI<(outs), 1094 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 1095 IIC_Br, "tbb $index\n$jt", []>; 1096 1097def t2TBH : 1098 T2JTI<(outs), 1099 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 1100 IIC_Br, "tbh $index\n$jt", []>; 1101} // isNotDuplicable, isIndirectBranch 1102 1103} // isBranch, isTerminator, isBarrier 1104 1105// FIXME: should be able to write a pattern for ARMBrcond, but can't use 1106// a two-value operand where a dag node expects two operands. :( 1107let isBranch = 1, isTerminator = 1 in 1108def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 1109 "b", ".w $target", 1110 [/*(ARMbrcond bb:$target, imm:$cc)*/]>; 1111 1112 1113// IT block 1114def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 1115 AddrModeNone, Size2Bytes, IIC_iALU, 1116 "it$mask $cc", "", []>; 1117 1118//===----------------------------------------------------------------------===// 1119// Non-Instruction Patterns 1120// 1121 1122// ConstantPool, GlobalAddress, and JumpTable 1123def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>; 1124def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 1125def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1126 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 1127 1128// Large immediate handling. 1129 1130def : T2Pat<(i32 imm:$src), 1131 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>; 1132