ARMInstrThumb2.td revision ad5c8808923ed5b24b586cec544e45cee539e529
1//===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb2 instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// IT block predicate field 15def it_pred_asmoperand : AsmOperandClass { 16 let Name = "ITCondCode"; 17 let ParserMethod = "parseITCondCode"; 18} 19def it_pred : Operand<i32> { 20 let PrintMethod = "printMandatoryPredicateOperand"; 21 let ParserMatchClass = it_pred_asmoperand; 22} 23 24// IT block condition mask 25def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; } 26def it_mask : Operand<i32> { 27 let PrintMethod = "printThumbITMask"; 28 let ParserMatchClass = it_mask_asmoperand; 29} 30 31// t2_shift_imm: An integer that encodes a shift amount and the type of shift 32// (asr or lsl). The 6-bit immediate encodes as: 33// {5} 0 ==> lsl 34// 1 asr 35// {4-0} imm5 shift amount. 36// asr #32 not allowed 37def t2_shift_imm : Operand<i32> { 38 let PrintMethod = "printShiftImmOperand"; 39 let ParserMatchClass = ShifterImmAsmOperand; 40 let DecoderMethod = "DecodeT2ShifterImmOperand"; 41} 42 43// Shifted operands. No register controlled shifts for Thumb2. 44// Note: We do not support rrx shifted operands yet. 45def t2_so_reg : Operand<i32>, // reg imm 46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 47 [shl,srl,sra,rotr]> { 48 let EncoderMethod = "getT2SORegOpValue"; 49 let PrintMethod = "printT2SOOperand"; 50 let DecoderMethod = "DecodeSORegImmOperand"; 51 let ParserMatchClass = ShiftedImmAsmOperand; 52 let MIOperandInfo = (ops rGPR, i32imm); 53} 54 55// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 56def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 58}]>; 59 60// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 61def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 63}]>; 64 65// t2_so_imm - Match a 32-bit immediate operand, which is an 66// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 67// immediate splatted into multiple bytes of the word. 68def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; } 69def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{ 70 return ARM_AM::getT2SOImmVal(Imm) != -1; 71 }]> { 72 let ParserMatchClass = t2_so_imm_asmoperand; 73 let EncoderMethod = "getT2SOImmOpValue"; 74 let DecoderMethod = "DecodeT2SOImm"; 75} 76 77// t2_so_imm_not - Match an immediate that is a complement 78// of a t2_so_imm. 79// Note: this pattern doesn't require an encoder method and such, as it's 80// only used on aliases (Pat<> and InstAlias<>). The actual encoding 81// is handled by the destination instructions, which use t2_so_imm. 82def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; } 83def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{ 84 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 85}], t2_so_imm_not_XFORM> { 86 let ParserMatchClass = t2_so_imm_not_asmoperand; 87} 88 89// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 90def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; } 91def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 92 int64_t Value = -(int)N->getZExtValue(); 93 return Value && ARM_AM::getT2SOImmVal(Value) != -1; 94}], t2_so_imm_neg_XFORM> { 95 let ParserMatchClass = t2_so_imm_neg_asmoperand; 96} 97 98/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 99def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; } 100def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{ 101 return Imm >= 0 && Imm < 4096; 102}]> { 103 let ParserMatchClass = imm0_4095_asmoperand; 104} 105 106def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; } 107def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{ 108 return (uint32_t)(-N->getZExtValue()) < 4096; 109}], imm_neg_XFORM> { 110 let ParserMatchClass = imm0_4095_neg_asmoperand; 111} 112 113def imm0_255_neg : PatLeaf<(i32 imm), [{ 114 return (uint32_t)(-N->getZExtValue()) < 255; 115}], imm_neg_XFORM>; 116 117def imm0_255_not : PatLeaf<(i32 imm), [{ 118 return (uint32_t)(~N->getZExtValue()) < 255; 119}], imm_comp_XFORM>; 120 121def lo5AllOne : PatLeaf<(i32 imm), [{ 122 // Returns true if all low 5-bits are 1. 123 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL; 124}]>; 125 126// Define Thumb2 specific addressing modes. 127 128// t2addrmode_imm12 := reg + imm12 129def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";} 130def t2addrmode_imm12 : Operand<i32>, 131 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 132 let PrintMethod = "printAddrModeImm12Operand"; 133 let EncoderMethod = "getAddrModeImm12OpValue"; 134 let DecoderMethod = "DecodeT2AddrModeImm12"; 135 let ParserMatchClass = t2addrmode_imm12_asmoperand; 136 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 137} 138 139// t2ldrlabel := imm12 140def t2ldrlabel : Operand<i32> { 141 let EncoderMethod = "getAddrModeImm12OpValue"; 142 let PrintMethod = "printT2LdrLabelOperand"; 143} 144 145def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";} 146def t2ldr_pcrel_imm12 : Operand<i32> { 147 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand; 148 // used for assembler pseudo instruction and maps to t2ldrlabel, so 149 // doesn't need encoder or print methods of its own. 150} 151 152// ADR instruction labels. 153def t2adrlabel : Operand<i32> { 154 let EncoderMethod = "getT2AdrLabelOpValue"; 155} 156 157 158// t2addrmode_posimm8 := reg + imm8 159def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";} 160def t2addrmode_posimm8 : Operand<i32> { 161 let PrintMethod = "printT2AddrModeImm8Operand"; 162 let EncoderMethod = "getT2AddrModeImm8OpValue"; 163 let DecoderMethod = "DecodeT2AddrModeImm8"; 164 let ParserMatchClass = MemPosImm8OffsetAsmOperand; 165 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 166} 167 168// t2addrmode_negimm8 := reg - imm8 169def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";} 170def t2addrmode_negimm8 : Operand<i32>, 171 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 172 let PrintMethod = "printT2AddrModeImm8Operand"; 173 let EncoderMethod = "getT2AddrModeImm8OpValue"; 174 let DecoderMethod = "DecodeT2AddrModeImm8"; 175 let ParserMatchClass = MemNegImm8OffsetAsmOperand; 176 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 177} 178 179// t2addrmode_imm8 := reg +/- imm8 180def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; } 181def t2addrmode_imm8 : Operand<i32>, 182 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 183 let PrintMethod = "printT2AddrModeImm8Operand"; 184 let EncoderMethod = "getT2AddrModeImm8OpValue"; 185 let DecoderMethod = "DecodeT2AddrModeImm8"; 186 let ParserMatchClass = MemImm8OffsetAsmOperand; 187 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 188} 189 190def t2am_imm8_offset : Operand<i32>, 191 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", 192 [], [SDNPWantRoot]> { 193 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 194 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue"; 195 let DecoderMethod = "DecodeT2Imm8"; 196} 197 198// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 199def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";} 200def t2addrmode_imm8s4 : Operand<i32> { 201 let PrintMethod = "printT2AddrModeImm8s4Operand"; 202 let EncoderMethod = "getT2AddrModeImm8s4OpValue"; 203 let DecoderMethod = "DecodeT2AddrModeImm8s4"; 204 let ParserMatchClass = MemImm8s4OffsetAsmOperand; 205 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 206} 207 208def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; } 209def t2am_imm8s4_offset : Operand<i32> { 210 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand"; 211 let EncoderMethod = "getT2Imm8s4OpValue"; 212 let DecoderMethod = "DecodeT2Imm8S4"; 213} 214 215// t2addrmode_imm0_1020s4 := reg + (imm8 << 2) 216def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass { 217 let Name = "MemImm0_1020s4Offset"; 218} 219def t2addrmode_imm0_1020s4 : Operand<i32> { 220 let PrintMethod = "printT2AddrModeImm0_1020s4Operand"; 221 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue"; 222 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4"; 223 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand; 224 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm); 225} 226 227// t2addrmode_so_reg := reg + (reg << imm2) 228def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";} 229def t2addrmode_so_reg : Operand<i32>, 230 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 231 let PrintMethod = "printT2AddrModeSoRegOperand"; 232 let EncoderMethod = "getT2AddrModeSORegOpValue"; 233 let DecoderMethod = "DecodeT2AddrModeSOReg"; 234 let ParserMatchClass = t2addrmode_so_reg_asmoperand; 235 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm); 236} 237 238// Addresses for the TBB/TBH instructions. 239def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; } 240def addrmode_tbb : Operand<i32> { 241 let PrintMethod = "printAddrModeTBB"; 242 let ParserMatchClass = addrmode_tbb_asmoperand; 243 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm); 244} 245def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; } 246def addrmode_tbh : Operand<i32> { 247 let PrintMethod = "printAddrModeTBH"; 248 let ParserMatchClass = addrmode_tbh_asmoperand; 249 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm); 250} 251 252//===----------------------------------------------------------------------===// 253// Multiclass helpers... 254// 255 256 257class T2OneRegImm<dag oops, dag iops, InstrItinClass itin, 258 string opc, string asm, list<dag> pattern> 259 : T2I<oops, iops, itin, opc, asm, pattern> { 260 bits<4> Rd; 261 bits<12> imm; 262 263 let Inst{11-8} = Rd; 264 let Inst{26} = imm{11}; 265 let Inst{14-12} = imm{10-8}; 266 let Inst{7-0} = imm{7-0}; 267} 268 269 270class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin, 271 string opc, string asm, list<dag> pattern> 272 : T2sI<oops, iops, itin, opc, asm, pattern> { 273 bits<4> Rd; 274 bits<4> Rn; 275 bits<12> imm; 276 277 let Inst{11-8} = Rd; 278 let Inst{26} = imm{11}; 279 let Inst{14-12} = imm{10-8}; 280 let Inst{7-0} = imm{7-0}; 281} 282 283class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin, 284 string opc, string asm, list<dag> pattern> 285 : T2I<oops, iops, itin, opc, asm, pattern> { 286 bits<4> Rn; 287 bits<12> imm; 288 289 let Inst{19-16} = Rn; 290 let Inst{26} = imm{11}; 291 let Inst{14-12} = imm{10-8}; 292 let Inst{7-0} = imm{7-0}; 293} 294 295 296class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 297 string opc, string asm, list<dag> pattern> 298 : T2I<oops, iops, itin, opc, asm, pattern> { 299 bits<4> Rd; 300 bits<12> ShiftedRm; 301 302 let Inst{11-8} = Rd; 303 let Inst{3-0} = ShiftedRm{3-0}; 304 let Inst{5-4} = ShiftedRm{6-5}; 305 let Inst{14-12} = ShiftedRm{11-9}; 306 let Inst{7-6} = ShiftedRm{8-7}; 307} 308 309class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 310 string opc, string asm, list<dag> pattern> 311 : T2sI<oops, iops, itin, opc, asm, pattern> { 312 bits<4> Rd; 313 bits<12> ShiftedRm; 314 315 let Inst{11-8} = Rd; 316 let Inst{3-0} = ShiftedRm{3-0}; 317 let Inst{5-4} = ShiftedRm{6-5}; 318 let Inst{14-12} = ShiftedRm{11-9}; 319 let Inst{7-6} = ShiftedRm{8-7}; 320} 321 322class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin, 323 string opc, string asm, list<dag> pattern> 324 : T2I<oops, iops, itin, opc, asm, pattern> { 325 bits<4> Rn; 326 bits<12> ShiftedRm; 327 328 let Inst{19-16} = Rn; 329 let Inst{3-0} = ShiftedRm{3-0}; 330 let Inst{5-4} = ShiftedRm{6-5}; 331 let Inst{14-12} = ShiftedRm{11-9}; 332 let Inst{7-6} = ShiftedRm{8-7}; 333} 334 335class T2TwoReg<dag oops, dag iops, InstrItinClass itin, 336 string opc, string asm, list<dag> pattern> 337 : T2I<oops, iops, itin, opc, asm, pattern> { 338 bits<4> Rd; 339 bits<4> Rm; 340 341 let Inst{11-8} = Rd; 342 let Inst{3-0} = Rm; 343} 344 345class T2sTwoReg<dag oops, dag iops, InstrItinClass itin, 346 string opc, string asm, list<dag> pattern> 347 : T2sI<oops, iops, itin, opc, asm, pattern> { 348 bits<4> Rd; 349 bits<4> Rm; 350 351 let Inst{11-8} = Rd; 352 let Inst{3-0} = Rm; 353} 354 355class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin, 356 string opc, string asm, list<dag> pattern> 357 : T2I<oops, iops, itin, opc, asm, pattern> { 358 bits<4> Rn; 359 bits<4> Rm; 360 361 let Inst{19-16} = Rn; 362 let Inst{3-0} = Rm; 363} 364 365 366class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin, 367 string opc, string asm, list<dag> pattern> 368 : T2I<oops, iops, itin, opc, asm, pattern> { 369 bits<4> Rd; 370 bits<4> Rn; 371 bits<12> imm; 372 373 let Inst{11-8} = Rd; 374 let Inst{19-16} = Rn; 375 let Inst{26} = imm{11}; 376 let Inst{14-12} = imm{10-8}; 377 let Inst{7-0} = imm{7-0}; 378} 379 380class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin, 381 string opc, string asm, list<dag> pattern> 382 : T2sI<oops, iops, itin, opc, asm, pattern> { 383 bits<4> Rd; 384 bits<4> Rn; 385 bits<12> imm; 386 387 let Inst{11-8} = Rd; 388 let Inst{19-16} = Rn; 389 let Inst{26} = imm{11}; 390 let Inst{14-12} = imm{10-8}; 391 let Inst{7-0} = imm{7-0}; 392} 393 394class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 395 string opc, string asm, list<dag> pattern> 396 : T2I<oops, iops, itin, opc, asm, pattern> { 397 bits<4> Rd; 398 bits<4> Rm; 399 bits<5> imm; 400 401 let Inst{11-8} = Rd; 402 let Inst{3-0} = Rm; 403 let Inst{14-12} = imm{4-2}; 404 let Inst{7-6} = imm{1-0}; 405} 406 407class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 408 string opc, string asm, list<dag> pattern> 409 : T2sI<oops, iops, itin, opc, asm, pattern> { 410 bits<4> Rd; 411 bits<4> Rm; 412 bits<5> imm; 413 414 let Inst{11-8} = Rd; 415 let Inst{3-0} = Rm; 416 let Inst{14-12} = imm{4-2}; 417 let Inst{7-6} = imm{1-0}; 418} 419 420class T2ThreeReg<dag oops, dag iops, InstrItinClass itin, 421 string opc, string asm, list<dag> pattern> 422 : T2I<oops, iops, itin, opc, asm, pattern> { 423 bits<4> Rd; 424 bits<4> Rn; 425 bits<4> Rm; 426 427 let Inst{11-8} = Rd; 428 let Inst{19-16} = Rn; 429 let Inst{3-0} = Rm; 430} 431 432class T2sThreeReg<dag oops, dag iops, InstrItinClass itin, 433 string opc, string asm, list<dag> pattern> 434 : T2sI<oops, iops, itin, opc, asm, pattern> { 435 bits<4> Rd; 436 bits<4> Rn; 437 bits<4> Rm; 438 439 let Inst{11-8} = Rd; 440 let Inst{19-16} = Rn; 441 let Inst{3-0} = Rm; 442} 443 444class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 445 string opc, string asm, list<dag> pattern> 446 : T2I<oops, iops, itin, opc, asm, pattern> { 447 bits<4> Rd; 448 bits<4> Rn; 449 bits<12> ShiftedRm; 450 451 let Inst{11-8} = Rd; 452 let Inst{19-16} = Rn; 453 let Inst{3-0} = ShiftedRm{3-0}; 454 let Inst{5-4} = ShiftedRm{6-5}; 455 let Inst{14-12} = ShiftedRm{11-9}; 456 let Inst{7-6} = ShiftedRm{8-7}; 457} 458 459class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 460 string opc, string asm, list<dag> pattern> 461 : T2sI<oops, iops, itin, opc, asm, pattern> { 462 bits<4> Rd; 463 bits<4> Rn; 464 bits<12> ShiftedRm; 465 466 let Inst{11-8} = Rd; 467 let Inst{19-16} = Rn; 468 let Inst{3-0} = ShiftedRm{3-0}; 469 let Inst{5-4} = ShiftedRm{6-5}; 470 let Inst{14-12} = ShiftedRm{11-9}; 471 let Inst{7-6} = ShiftedRm{8-7}; 472} 473 474class T2FourReg<dag oops, dag iops, InstrItinClass itin, 475 string opc, string asm, list<dag> pattern> 476 : T2I<oops, iops, itin, opc, asm, pattern> { 477 bits<4> Rd; 478 bits<4> Rn; 479 bits<4> Rm; 480 bits<4> Ra; 481 482 let Inst{19-16} = Rn; 483 let Inst{15-12} = Ra; 484 let Inst{11-8} = Rd; 485 let Inst{3-0} = Rm; 486} 487 488class T2MulLong<bits<3> opc22_20, bits<4> opc7_4, 489 dag oops, dag iops, InstrItinClass itin, 490 string opc, string asm, list<dag> pattern> 491 : T2I<oops, iops, itin, opc, asm, pattern> { 492 bits<4> RdLo; 493 bits<4> RdHi; 494 bits<4> Rn; 495 bits<4> Rm; 496 497 let Inst{31-23} = 0b111110111; 498 let Inst{22-20} = opc22_20; 499 let Inst{19-16} = Rn; 500 let Inst{15-12} = RdLo; 501 let Inst{11-8} = RdHi; 502 let Inst{7-4} = opc7_4; 503 let Inst{3-0} = Rm; 504} 505 506 507/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 508/// binary operation that produces a value. These are predicable and can be 509/// changed to modify CPSR. 510multiclass T2I_bin_irs<bits<4> opcod, string opc, 511 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 512 PatFrag opnode, string baseOpc, bit Commutable = 0, 513 string wide = ""> { 514 // shifted imm 515 def ri : T2sTwoRegImm< 516 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii, 517 opc, "\t$Rd, $Rn, $imm", 518 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> { 519 let Inst{31-27} = 0b11110; 520 let Inst{25} = 0; 521 let Inst{24-21} = opcod; 522 let Inst{15} = 0; 523 } 524 // register 525 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir, 526 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"), 527 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> { 528 let isCommutable = Commutable; 529 let Inst{31-27} = 0b11101; 530 let Inst{26-25} = 0b01; 531 let Inst{24-21} = opcod; 532 let Inst{14-12} = 0b000; // imm3 533 let Inst{7-6} = 0b00; // imm2 534 let Inst{5-4} = 0b00; // type 535 } 536 // shifted register 537 def rs : T2sTwoRegShiftedReg< 538 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis, 539 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"), 540 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> { 541 let Inst{31-27} = 0b11101; 542 let Inst{26-25} = 0b01; 543 let Inst{24-21} = opcod; 544 } 545 // Assembly aliases for optional destination operand when it's the same 546 // as the source operand. 547 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"), 548 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, 549 t2_so_imm:$imm, pred:$p, 550 cc_out:$s)>; 551 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"), 552 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 553 rGPR:$Rm, pred:$p, 554 cc_out:$s)>; 555 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"), 556 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn, 557 t2_so_reg:$shift, pred:$p, 558 cc_out:$s)>; 559} 560 561/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 562// the ".w" suffix to indicate that they are wide. 563multiclass T2I_bin_w_irs<bits<4> opcod, string opc, 564 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 565 PatFrag opnode, string baseOpc, bit Commutable = 0> : 566 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> { 567 // Assembler aliases w/ the ".w" suffix. 568 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"), 569 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn, 570 t2_so_imm:$imm, pred:$p, 571 cc_out:$s)>; 572 // Assembler aliases w/o the ".w" suffix. 573 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 574 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn, 575 rGPR:$Rm, pred:$p, 576 cc_out:$s)>; 577 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"), 578 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn, 579 t2_so_reg:$shift, pred:$p, 580 cc_out:$s)>; 581 582 // and with the optional destination operand, too. 583 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"), 584 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, 585 t2_so_imm:$imm, pred:$p, 586 cc_out:$s)>; 587 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 588 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 589 rGPR:$Rm, pred:$p, 590 cc_out:$s)>; 591 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"), 592 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn, 593 t2_so_reg:$shift, pred:$p, 594 cc_out:$s)>; 595} 596 597/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 598/// reversed. The 'rr' form is only defined for the disassembler; for codegen 599/// it is equivalent to the T2I_bin_irs counterpart. 600multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> { 601 // shifted imm 602 def ri : T2sTwoRegImm< 603 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, 604 opc, ".w\t$Rd, $Rn, $imm", 605 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { 606 let Inst{31-27} = 0b11110; 607 let Inst{25} = 0; 608 let Inst{24-21} = opcod; 609 let Inst{15} = 0; 610 } 611 // register 612 def rr : T2sThreeReg< 613 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 614 opc, "\t$Rd, $Rn, $Rm", 615 [/* For disassembly only; pattern left blank */]> { 616 let Inst{31-27} = 0b11101; 617 let Inst{26-25} = 0b01; 618 let Inst{24-21} = opcod; 619 let Inst{14-12} = 0b000; // imm3 620 let Inst{7-6} = 0b00; // imm2 621 let Inst{5-4} = 0b00; // type 622 } 623 // shifted register 624 def rs : T2sTwoRegShiftedReg< 625 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 626 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm", 627 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { 628 let Inst{31-27} = 0b11101; 629 let Inst{26-25} = 0b01; 630 let Inst{24-21} = opcod; 631 } 632} 633 634/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 635/// instruction modifies the CPSR register. 636/// 637/// These opcodes will be converted to the real non-S opcodes by 638/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand. 639let hasPostISelHook = 1, Defs = [CPSR] in { 640multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 641 InstrItinClass iis, PatFrag opnode, 642 bit Commutable = 0> { 643 // shifted imm 644 def ri : t2PseudoInst<(outs rGPR:$Rd), 645 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p), 646 4, iii, 647 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 648 t2_so_imm:$imm))]>; 649 // register 650 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p), 651 4, iir, 652 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 653 rGPR:$Rm))]> { 654 let isCommutable = Commutable; 655 } 656 // shifted register 657 def rs : t2PseudoInst<(outs rGPR:$Rd), 658 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p), 659 4, iis, 660 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 661 t2_so_reg:$ShiftedRm))]>; 662} 663} 664 665/// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG 666/// operands are reversed. 667let hasPostISelHook = 1, Defs = [CPSR] in { 668multiclass T2I_rbin_s_is<PatFrag opnode> { 669 // shifted imm 670 def ri : t2PseudoInst<(outs rGPR:$Rd), 671 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p), 672 4, IIC_iALUi, 673 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, 674 rGPR:$Rn))]>; 675 // shifted register 676 def rs : t2PseudoInst<(outs rGPR:$Rd), 677 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p), 678 4, IIC_iALUsi, 679 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, 680 rGPR:$Rn))]>; 681} 682} 683 684/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 685/// patterns for a binary operation that produces a value. 686multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode, 687 bit Commutable = 0> { 688 // shifted imm 689 // The register-immediate version is re-materializable. This is useful 690 // in particular for taking the address of a local. 691 let isReMaterializable = 1 in { 692 def ri : T2sTwoRegImm< 693 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi, 694 opc, ".w\t$Rd, $Rn, $imm", 695 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> { 696 let Inst{31-27} = 0b11110; 697 let Inst{25} = 0; 698 let Inst{24} = 1; 699 let Inst{23-21} = op23_21; 700 let Inst{15} = 0; 701 } 702 } 703 // 12-bit imm 704 def ri12 : T2I< 705 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi, 706 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm", 707 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> { 708 bits<4> Rd; 709 bits<4> Rn; 710 bits<12> imm; 711 let Inst{31-27} = 0b11110; 712 let Inst{26} = imm{11}; 713 let Inst{25-24} = 0b10; 714 let Inst{23-21} = op23_21; 715 let Inst{20} = 0; // The S bit. 716 let Inst{19-16} = Rn; 717 let Inst{15} = 0; 718 let Inst{14-12} = imm{10-8}; 719 let Inst{11-8} = Rd; 720 let Inst{7-0} = imm{7-0}; 721 } 722 // register 723 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), 724 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm", 725 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> { 726 let isCommutable = Commutable; 727 let Inst{31-27} = 0b11101; 728 let Inst{26-25} = 0b01; 729 let Inst{24} = 1; 730 let Inst{23-21} = op23_21; 731 let Inst{14-12} = 0b000; // imm3 732 let Inst{7-6} = 0b00; // imm2 733 let Inst{5-4} = 0b00; // type 734 } 735 // shifted register 736 def rs : T2sTwoRegShiftedReg< 737 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), 738 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 739 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> { 740 let Inst{31-27} = 0b11101; 741 let Inst{26-25} = 0b01; 742 let Inst{24} = 1; 743 let Inst{23-21} = op23_21; 744 } 745} 746 747/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns 748/// for a binary operation that produces a value and use the carry 749/// bit. It's not predicable. 750let Defs = [CPSR], Uses = [CPSR] in { 751multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 752 bit Commutable = 0> { 753 // shifted imm 754 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), 755 IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 756 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>, 757 Requires<[IsThumb2]> { 758 let Inst{31-27} = 0b11110; 759 let Inst{25} = 0; 760 let Inst{24-21} = opcod; 761 let Inst{15} = 0; 762 } 763 // register 764 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 765 opc, ".w\t$Rd, $Rn, $Rm", 766 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>, 767 Requires<[IsThumb2]> { 768 let isCommutable = Commutable; 769 let Inst{31-27} = 0b11101; 770 let Inst{26-25} = 0b01; 771 let Inst{24-21} = opcod; 772 let Inst{14-12} = 0b000; // imm3 773 let Inst{7-6} = 0b00; // imm2 774 let Inst{5-4} = 0b00; // type 775 } 776 // shifted register 777 def rs : T2sTwoRegShiftedReg< 778 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 779 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 780 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>, 781 Requires<[IsThumb2]> { 782 let Inst{31-27} = 0b11101; 783 let Inst{26-25} = 0b01; 784 let Inst{24-21} = opcod; 785 } 786} 787} 788 789/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 790// rotate operation that produces a value. 791multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode, 792 string baseOpc> { 793 // 5-bit imm 794 def ri : T2sTwoRegShiftImm< 795 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi, 796 opc, ".w\t$Rd, $Rm, $imm", 797 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> { 798 let Inst{31-27} = 0b11101; 799 let Inst{26-21} = 0b010010; 800 let Inst{19-16} = 0b1111; // Rn 801 let Inst{5-4} = opcod; 802 } 803 // register 804 def rr : T2sThreeReg< 805 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr, 806 opc, ".w\t$Rd, $Rn, $Rm", 807 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> { 808 let Inst{31-27} = 0b11111; 809 let Inst{26-23} = 0b0100; 810 let Inst{22-21} = opcod; 811 let Inst{15-12} = 0b1111; 812 let Inst{7-4} = 0b0000; 813 } 814 815 // Optional destination register 816 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"), 817 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, 818 ty:$imm, pred:$p, 819 cc_out:$s)>; 820 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"), 821 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 822 rGPR:$Rm, pred:$p, 823 cc_out:$s)>; 824 825 // Assembler aliases w/o the ".w" suffix. 826 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"), 827 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn, 828 ty:$imm, pred:$p, 829 cc_out:$s)>; 830 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 831 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn, 832 rGPR:$Rm, pred:$p, 833 cc_out:$s)>; 834 835 // and with the optional destination operand, too. 836 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"), 837 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, 838 ty:$imm, pred:$p, 839 cc_out:$s)>; 840 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 841 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 842 rGPR:$Rm, pred:$p, 843 cc_out:$s)>; 844} 845 846/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 847/// patterns. Similar to T2I_bin_irs except the instruction does not produce 848/// a explicit result, only implicitly set CPSR. 849multiclass T2I_cmp_irs<bits<4> opcod, string opc, 850 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 851 PatFrag opnode, string baseOpc> { 852let isCompare = 1, Defs = [CPSR] in { 853 // shifted imm 854 def ri : T2OneRegCmpImm< 855 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii, 856 opc, ".w\t$Rn, $imm", 857 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> { 858 let Inst{31-27} = 0b11110; 859 let Inst{25} = 0; 860 let Inst{24-21} = opcod; 861 let Inst{20} = 1; // The S bit. 862 let Inst{15} = 0; 863 let Inst{11-8} = 0b1111; // Rd 864 } 865 // register 866 def rr : T2TwoRegCmp< 867 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir, 868 opc, ".w\t$Rn, $Rm", 869 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> { 870 let Inst{31-27} = 0b11101; 871 let Inst{26-25} = 0b01; 872 let Inst{24-21} = opcod; 873 let Inst{20} = 1; // The S bit. 874 let Inst{14-12} = 0b000; // imm3 875 let Inst{11-8} = 0b1111; // Rd 876 let Inst{7-6} = 0b00; // imm2 877 let Inst{5-4} = 0b00; // type 878 } 879 // shifted register 880 def rs : T2OneRegCmpShiftedReg< 881 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis, 882 opc, ".w\t$Rn, $ShiftedRm", 883 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> { 884 let Inst{31-27} = 0b11101; 885 let Inst{26-25} = 0b01; 886 let Inst{24-21} = opcod; 887 let Inst{20} = 1; // The S bit. 888 let Inst{11-8} = 0b1111; // Rd 889 } 890} 891 892 // Assembler aliases w/o the ".w" suffix. 893 // No alias here for 'rr' version as not all instantiations of this 894 // multiclass want one (CMP in particular, does not). 895 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"), 896 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn, 897 t2_so_imm:$imm, pred:$p)>; 898 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"), 899 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn, 900 t2_so_reg:$shift, 901 pred:$p)>; 902} 903 904/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 905multiclass T2I_ld<bit signed, bits<2> opcod, string opc, 906 InstrItinClass iii, InstrItinClass iis, RegisterClass target, 907 PatFrag opnode> { 908 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii, 909 opc, ".w\t$Rt, $addr", 910 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> { 911 bits<4> Rt; 912 bits<17> addr; 913 let Inst{31-25} = 0b1111100; 914 let Inst{24} = signed; 915 let Inst{23} = 1; 916 let Inst{22-21} = opcod; 917 let Inst{20} = 1; // load 918 let Inst{19-16} = addr{16-13}; // Rn 919 let Inst{15-12} = Rt; 920 let Inst{11-0} = addr{11-0}; // imm 921 } 922 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii, 923 opc, "\t$Rt, $addr", 924 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> { 925 bits<4> Rt; 926 bits<13> addr; 927 let Inst{31-27} = 0b11111; 928 let Inst{26-25} = 0b00; 929 let Inst{24} = signed; 930 let Inst{23} = 0; 931 let Inst{22-21} = opcod; 932 let Inst{20} = 1; // load 933 let Inst{19-16} = addr{12-9}; // Rn 934 let Inst{15-12} = Rt; 935 let Inst{11} = 1; 936 // Offset: index==TRUE, wback==FALSE 937 let Inst{10} = 1; // The P bit. 938 let Inst{9} = addr{8}; // U 939 let Inst{8} = 0; // The W bit. 940 let Inst{7-0} = addr{7-0}; // imm 941 } 942 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis, 943 opc, ".w\t$Rt, $addr", 944 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> { 945 let Inst{31-27} = 0b11111; 946 let Inst{26-25} = 0b00; 947 let Inst{24} = signed; 948 let Inst{23} = 0; 949 let Inst{22-21} = opcod; 950 let Inst{20} = 1; // load 951 let Inst{11-6} = 0b000000; 952 953 bits<4> Rt; 954 let Inst{15-12} = Rt; 955 956 bits<10> addr; 957 let Inst{19-16} = addr{9-6}; // Rn 958 let Inst{3-0} = addr{5-2}; // Rm 959 let Inst{5-4} = addr{1-0}; // imm 960 961 let DecoderMethod = "DecodeT2LoadShift"; 962 } 963 964 // pci variant is very similar to i12, but supports negative offsets 965 // from the PC. 966 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii, 967 opc, ".w\t$Rt, $addr", 968 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> { 969 let isReMaterializable = 1; 970 let Inst{31-27} = 0b11111; 971 let Inst{26-25} = 0b00; 972 let Inst{24} = signed; 973 let Inst{23} = ?; // add = (U == '1') 974 let Inst{22-21} = opcod; 975 let Inst{20} = 1; // load 976 let Inst{19-16} = 0b1111; // Rn 977 bits<4> Rt; 978 bits<12> addr; 979 let Inst{15-12} = Rt{3-0}; 980 let Inst{11-0} = addr{11-0}; 981 } 982} 983 984/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 985multiclass T2I_st<bits<2> opcod, string opc, 986 InstrItinClass iii, InstrItinClass iis, RegisterClass target, 987 PatFrag opnode> { 988 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii, 989 opc, ".w\t$Rt, $addr", 990 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> { 991 let Inst{31-27} = 0b11111; 992 let Inst{26-23} = 0b0001; 993 let Inst{22-21} = opcod; 994 let Inst{20} = 0; // !load 995 996 bits<4> Rt; 997 let Inst{15-12} = Rt; 998 999 bits<17> addr; 1000 let addr{12} = 1; // add = TRUE 1001 let Inst{19-16} = addr{16-13}; // Rn 1002 let Inst{23} = addr{12}; // U 1003 let Inst{11-0} = addr{11-0}; // imm 1004 } 1005 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii, 1006 opc, "\t$Rt, $addr", 1007 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> { 1008 let Inst{31-27} = 0b11111; 1009 let Inst{26-23} = 0b0000; 1010 let Inst{22-21} = opcod; 1011 let Inst{20} = 0; // !load 1012 let Inst{11} = 1; 1013 // Offset: index==TRUE, wback==FALSE 1014 let Inst{10} = 1; // The P bit. 1015 let Inst{8} = 0; // The W bit. 1016 1017 bits<4> Rt; 1018 let Inst{15-12} = Rt; 1019 1020 bits<13> addr; 1021 let Inst{19-16} = addr{12-9}; // Rn 1022 let Inst{9} = addr{8}; // U 1023 let Inst{7-0} = addr{7-0}; // imm 1024 } 1025 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis, 1026 opc, ".w\t$Rt, $addr", 1027 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> { 1028 let Inst{31-27} = 0b11111; 1029 let Inst{26-23} = 0b0000; 1030 let Inst{22-21} = opcod; 1031 let Inst{20} = 0; // !load 1032 let Inst{11-6} = 0b000000; 1033 1034 bits<4> Rt; 1035 let Inst{15-12} = Rt; 1036 1037 bits<10> addr; 1038 let Inst{19-16} = addr{9-6}; // Rn 1039 let Inst{3-0} = addr{5-2}; // Rm 1040 let Inst{5-4} = addr{1-0}; // imm 1041 } 1042} 1043 1044/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a 1045/// register and one whose operand is a register rotated by 8/16/24. 1046class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> 1047 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, 1048 opc, ".w\t$Rd, $Rm$rot", 1049 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, 1050 Requires<[IsThumb2]> { 1051 let Inst{31-27} = 0b11111; 1052 let Inst{26-23} = 0b0100; 1053 let Inst{22-20} = opcod; 1054 let Inst{19-16} = 0b1111; // Rn 1055 let Inst{15-12} = 0b1111; 1056 let Inst{7} = 1; 1057 1058 bits<2> rot; 1059 let Inst{5-4} = rot{1-0}; // rotate 1060} 1061 1062// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. 1063class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> 1064 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), 1065 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1066 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, 1067 Requires<[HasT2ExtractPack, IsThumb2]> { 1068 bits<2> rot; 1069 let Inst{31-27} = 0b11111; 1070 let Inst{26-23} = 0b0100; 1071 let Inst{22-20} = opcod; 1072 let Inst{19-16} = 0b1111; // Rn 1073 let Inst{15-12} = 0b1111; 1074 let Inst{7} = 1; 1075 let Inst{5-4} = rot; 1076} 1077 1078// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern 1079// supported yet. 1080class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> 1081 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, 1082 opc, "\t$Rd, $Rm$rot", []>, 1083 Requires<[IsThumb2, HasT2ExtractPack]> { 1084 bits<2> rot; 1085 let Inst{31-27} = 0b11111; 1086 let Inst{26-23} = 0b0100; 1087 let Inst{22-20} = opcod; 1088 let Inst{19-16} = 0b1111; // Rn 1089 let Inst{15-12} = 0b1111; 1090 let Inst{7} = 1; 1091 let Inst{5-4} = rot; 1092} 1093 1094/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a 1095/// register and one whose operand is a register rotated by 8/16/24. 1096class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> 1097 : T2ThreeReg<(outs rGPR:$Rd), 1098 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), 1099 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", 1100 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>, 1101 Requires<[HasT2ExtractPack, IsThumb2]> { 1102 bits<2> rot; 1103 let Inst{31-27} = 0b11111; 1104 let Inst{26-23} = 0b0100; 1105 let Inst{22-20} = opcod; 1106 let Inst{15-12} = 0b1111; 1107 let Inst{7} = 1; 1108 let Inst{5-4} = rot; 1109} 1110 1111class T2I_exta_rrot_np<bits<3> opcod, string opc> 1112 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot), 1113 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> { 1114 bits<2> rot; 1115 let Inst{31-27} = 0b11111; 1116 let Inst{26-23} = 0b0100; 1117 let Inst{22-20} = opcod; 1118 let Inst{15-12} = 0b1111; 1119 let Inst{7} = 1; 1120 let Inst{5-4} = rot; 1121} 1122 1123//===----------------------------------------------------------------------===// 1124// Instructions 1125//===----------------------------------------------------------------------===// 1126 1127//===----------------------------------------------------------------------===// 1128// Miscellaneous Instructions. 1129// 1130 1131class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin, 1132 string asm, list<dag> pattern> 1133 : T2XI<oops, iops, itin, asm, pattern> { 1134 bits<4> Rd; 1135 bits<12> label; 1136 1137 let Inst{11-8} = Rd; 1138 let Inst{26} = label{11}; 1139 let Inst{14-12} = label{10-8}; 1140 let Inst{7-0} = label{7-0}; 1141} 1142 1143// LEApcrel - Load a pc-relative address into a register without offending the 1144// assembler. 1145def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd), 1146 (ins t2adrlabel:$addr, pred:$p), 1147 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> { 1148 let Inst{31-27} = 0b11110; 1149 let Inst{25-24} = 0b10; 1150 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 1151 let Inst{22} = 0; 1152 let Inst{20} = 0; 1153 let Inst{19-16} = 0b1111; // Rn 1154 let Inst{15} = 0; 1155 1156 bits<4> Rd; 1157 bits<13> addr; 1158 let Inst{11-8} = Rd; 1159 let Inst{23} = addr{12}; 1160 let Inst{21} = addr{12}; 1161 let Inst{26} = addr{11}; 1162 let Inst{14-12} = addr{10-8}; 1163 let Inst{7-0} = addr{7-0}; 1164 1165 let DecoderMethod = "DecodeT2Adr"; 1166} 1167 1168let neverHasSideEffects = 1, isReMaterializable = 1 in 1169def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), 1170 4, IIC_iALUi, []>; 1171def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd), 1172 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1173 4, IIC_iALUi, 1174 []>; 1175 1176 1177//===----------------------------------------------------------------------===// 1178// Load / store Instructions. 1179// 1180 1181// Load 1182let canFoldAsLoad = 1, isReMaterializable = 1 in 1183defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, 1184 UnOpFrag<(load node:$Src)>>; 1185 1186// Loads with zero extension 1187defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1188 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>; 1189defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1190 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>; 1191 1192// Loads with sign extension 1193defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1194 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>; 1195defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1196 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>; 1197 1198let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 1199// Load doubleword 1200def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2), 1201 (ins t2addrmode_imm8s4:$addr), 1202 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>; 1203} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 1204 1205// zextload i1 -> zextload i8 1206def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 1207 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1208def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr), 1209 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1210def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 1211 (t2LDRBs t2addrmode_so_reg:$addr)>; 1212def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 1213 (t2LDRBpci tconstpool:$addr)>; 1214 1215// extload -> zextload 1216// FIXME: Reduce the number of patterns by legalizing extload to zextload 1217// earlier? 1218def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 1219 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1220def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr), 1221 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1222def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 1223 (t2LDRBs t2addrmode_so_reg:$addr)>; 1224def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 1225 (t2LDRBpci tconstpool:$addr)>; 1226 1227def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 1228 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1229def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr), 1230 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1231def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 1232 (t2LDRBs t2addrmode_so_reg:$addr)>; 1233def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 1234 (t2LDRBpci tconstpool:$addr)>; 1235 1236def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 1237 (t2LDRHi12 t2addrmode_imm12:$addr)>; 1238def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr), 1239 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 1240def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 1241 (t2LDRHs t2addrmode_so_reg:$addr)>; 1242def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 1243 (t2LDRHpci tconstpool:$addr)>; 1244 1245// FIXME: The destination register of the loads and stores can't be PC, but 1246// can be SP. We need another regclass (similar to rGPR) to represent 1247// that. Not a pressing issue since these are selected manually, 1248// not via pattern. 1249 1250// Indexed loads 1251 1252let mayLoad = 1, neverHasSideEffects = 1 in { 1253def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1254 (ins t2addrmode_imm8:$addr), 1255 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu, 1256 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1257 []> { 1258 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; 1259} 1260 1261def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1262 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1263 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu, 1264 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1265 1266def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1267 (ins t2addrmode_imm8:$addr), 1268 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1269 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1270 []> { 1271 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; 1272} 1273def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1274 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1275 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1276 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1277 1278def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1279 (ins t2addrmode_imm8:$addr), 1280 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1281 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1282 []> { 1283 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; 1284} 1285def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1286 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1287 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1288 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1289 1290def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1291 (ins t2addrmode_imm8:$addr), 1292 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1293 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1294 []> { 1295 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; 1296} 1297def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1298 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1299 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1300 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1301 1302def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1303 (ins t2addrmode_imm8:$addr), 1304 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1305 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1306 []> { 1307 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; 1308} 1309def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1310 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1311 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1312 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1313} // mayLoad = 1, neverHasSideEffects = 1 1314 1315// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110). 1316// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 1317class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii> 1318 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc, 1319 "\t$Rt, $addr", []> { 1320 bits<4> Rt; 1321 bits<13> addr; 1322 let Inst{31-27} = 0b11111; 1323 let Inst{26-25} = 0b00; 1324 let Inst{24} = signed; 1325 let Inst{23} = 0; 1326 let Inst{22-21} = type; 1327 let Inst{20} = 1; // load 1328 let Inst{19-16} = addr{12-9}; 1329 let Inst{15-12} = Rt; 1330 let Inst{11} = 1; 1331 let Inst{10-8} = 0b110; // PUW. 1332 let Inst{7-0} = addr{7-0}; 1333} 1334 1335def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>; 1336def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>; 1337def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>; 1338def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>; 1339def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>; 1340 1341// Store 1342defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, 1343 BinOpFrag<(store node:$LHS, node:$RHS)>>; 1344defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si, 1345 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 1346defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si, 1347 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 1348 1349// Store doubleword 1350let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in 1351def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs), 1352 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr), 1353 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>; 1354 1355// Indexed stores 1356 1357let mayStore = 1, neverHasSideEffects = 1 in { 1358def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb), 1359 (ins GPRnopc:$Rt, t2addrmode_imm8:$addr), 1360 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1361 "str", "\t$Rt, $addr!", 1362 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 1363 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8"; 1364} 1365def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb), 1366 (ins rGPR:$Rt, t2addrmode_imm8:$addr), 1367 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1368 "strh", "\t$Rt, $addr!", 1369 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 1370 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8"; 1371} 1372 1373def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb), 1374 (ins rGPR:$Rt, t2addrmode_imm8:$addr), 1375 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu, 1376 "strb", "\t$Rt, $addr!", 1377 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 1378 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8"; 1379} 1380} // mayStore = 1, neverHasSideEffects = 1 1381 1382def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb), 1383 (ins GPRnopc:$Rt, addr_offset_none:$Rn, 1384 t2am_imm8_offset:$offset), 1385 AddrModeT2_i8, IndexModePost, IIC_iStore_iu, 1386 "str", "\t$Rt, $Rn$offset", 1387 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1388 [(set GPRnopc:$Rn_wb, 1389 (post_store GPRnopc:$Rt, addr_offset_none:$Rn, 1390 t2am_imm8_offset:$offset))]>; 1391 1392def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb), 1393 (ins rGPR:$Rt, addr_offset_none:$Rn, 1394 t2am_imm8_offset:$offset), 1395 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1396 "strh", "\t$Rt, $Rn$offset", 1397 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1398 [(set GPRnopc:$Rn_wb, 1399 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn, 1400 t2am_imm8_offset:$offset))]>; 1401 1402def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb), 1403 (ins rGPR:$Rt, addr_offset_none:$Rn, 1404 t2am_imm8_offset:$offset), 1405 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1406 "strb", "\t$Rt, $Rn$offset", 1407 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1408 [(set GPRnopc:$Rn_wb, 1409 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn, 1410 t2am_imm8_offset:$offset))]>; 1411 1412// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 1413// put the patterns on the instruction definitions directly as ISel wants 1414// the address base and offset to be separate operands, not a single 1415// complex operand like we represent the instructions themselves. The 1416// pseudos map between the two. 1417let usesCustomInserter = 1, 1418 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 1419def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1420 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1421 4, IIC_iStore_ru, 1422 [(set GPRnopc:$Rn_wb, 1423 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>; 1424def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1425 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1426 4, IIC_iStore_ru, 1427 [(set GPRnopc:$Rn_wb, 1428 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>; 1429def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1430 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1431 4, IIC_iStore_ru, 1432 [(set GPRnopc:$Rn_wb, 1433 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>; 1434} 1435 1436// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly 1437// only. 1438// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 1439class T2IstT<bits<2> type, string opc, InstrItinClass ii> 1440 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, 1441 "\t$Rt, $addr", []> { 1442 let Inst{31-27} = 0b11111; 1443 let Inst{26-25} = 0b00; 1444 let Inst{24} = 0; // not signed 1445 let Inst{23} = 0; 1446 let Inst{22-21} = type; 1447 let Inst{20} = 0; // store 1448 let Inst{11} = 1; 1449 let Inst{10-8} = 0b110; // PUW 1450 1451 bits<4> Rt; 1452 bits<13> addr; 1453 let Inst{15-12} = Rt; 1454 let Inst{19-16} = addr{12-9}; 1455 let Inst{7-0} = addr{7-0}; 1456} 1457 1458def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>; 1459def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>; 1460def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>; 1461 1462// ldrd / strd pre / post variants 1463// For disassembly only. 1464 1465def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1466 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru, 1467 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> { 1468 let AsmMatchConverter = "cvtT2LdrdPre"; 1469 let DecoderMethod = "DecodeT2LDRDPreInstruction"; 1470} 1471 1472def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1473 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm), 1474 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm", 1475 "$addr.base = $wb", []>; 1476 1477def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb), 1478 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr), 1479 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!", 1480 "$addr.base = $wb", []> { 1481 let AsmMatchConverter = "cvtT2StrdPre"; 1482 let DecoderMethod = "DecodeT2STRDPreInstruction"; 1483} 1484 1485def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb), 1486 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr, 1487 t2am_imm8s4_offset:$imm), 1488 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm", 1489 "$addr.base = $wb", []>; 1490 1491// T2Ipl (Preload Data/Instruction) signals the memory system of possible future 1492// data/instruction access. 1493// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0), 1494// (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1). 1495multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> { 1496 1497 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc, 1498 "\t$addr", 1499 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> { 1500 let Inst{31-25} = 0b1111100; 1501 let Inst{24} = instr; 1502 let Inst{22} = 0; 1503 let Inst{21} = write; 1504 let Inst{20} = 1; 1505 let Inst{15-12} = 0b1111; 1506 1507 bits<17> addr; 1508 let addr{12} = 1; // add = TRUE 1509 let Inst{19-16} = addr{16-13}; // Rn 1510 let Inst{23} = addr{12}; // U 1511 let Inst{11-0} = addr{11-0}; // imm12 1512 } 1513 1514 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc, 1515 "\t$addr", 1516 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> { 1517 let Inst{31-25} = 0b1111100; 1518 let Inst{24} = instr; 1519 let Inst{23} = 0; // U = 0 1520 let Inst{22} = 0; 1521 let Inst{21} = write; 1522 let Inst{20} = 1; 1523 let Inst{15-12} = 0b1111; 1524 let Inst{11-8} = 0b1100; 1525 1526 bits<13> addr; 1527 let Inst{19-16} = addr{12-9}; // Rn 1528 let Inst{7-0} = addr{7-0}; // imm8 1529 } 1530 1531 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc, 1532 "\t$addr", 1533 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> { 1534 let Inst{31-25} = 0b1111100; 1535 let Inst{24} = instr; 1536 let Inst{23} = 0; // add = TRUE for T1 1537 let Inst{22} = 0; 1538 let Inst{21} = write; 1539 let Inst{20} = 1; 1540 let Inst{15-12} = 0b1111; 1541 let Inst{11-6} = 0000000; 1542 1543 bits<10> addr; 1544 let Inst{19-16} = addr{9-6}; // Rn 1545 let Inst{3-0} = addr{5-2}; // Rm 1546 let Inst{5-4} = addr{1-0}; // imm2 1547 1548 let DecoderMethod = "DecodeT2LoadShift"; 1549 } 1550 // FIXME: We should have a separate 'pci' variant here. As-is we represent 1551 // it via the i12 variant, which it's related to, but that means we can 1552 // represent negative immediates, which aren't legal for anything except 1553 // the 'pci' case (Rn == 15). 1554} 1555 1556defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>; 1557defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>; 1558defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>; 1559 1560//===----------------------------------------------------------------------===// 1561// Load / store multiple Instructions. 1562// 1563 1564multiclass thumb2_ld_mult<string asm, InstrItinClass itin, 1565 InstrItinClass itin_upd, bit L_bit> { 1566 def IA : 1567 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1568 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { 1569 bits<4> Rn; 1570 bits<16> regs; 1571 1572 let Inst{31-27} = 0b11101; 1573 let Inst{26-25} = 0b00; 1574 let Inst{24-23} = 0b01; // Increment After 1575 let Inst{22} = 0; 1576 let Inst{21} = 0; // No writeback 1577 let Inst{20} = L_bit; 1578 let Inst{19-16} = Rn; 1579 let Inst{15-0} = regs; 1580 } 1581 def IA_UPD : 1582 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1583 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> { 1584 bits<4> Rn; 1585 bits<16> regs; 1586 1587 let Inst{31-27} = 0b11101; 1588 let Inst{26-25} = 0b00; 1589 let Inst{24-23} = 0b01; // Increment After 1590 let Inst{22} = 0; 1591 let Inst{21} = 1; // Writeback 1592 let Inst{20} = L_bit; 1593 let Inst{19-16} = Rn; 1594 let Inst{15-0} = regs; 1595 } 1596 def DB : 1597 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1598 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> { 1599 bits<4> Rn; 1600 bits<16> regs; 1601 1602 let Inst{31-27} = 0b11101; 1603 let Inst{26-25} = 0b00; 1604 let Inst{24-23} = 0b10; // Decrement Before 1605 let Inst{22} = 0; 1606 let Inst{21} = 0; // No writeback 1607 let Inst{20} = L_bit; 1608 let Inst{19-16} = Rn; 1609 let Inst{15-0} = regs; 1610 } 1611 def DB_UPD : 1612 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1613 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 1614 bits<4> Rn; 1615 bits<16> regs; 1616 1617 let Inst{31-27} = 0b11101; 1618 let Inst{26-25} = 0b00; 1619 let Inst{24-23} = 0b10; // Decrement Before 1620 let Inst{22} = 0; 1621 let Inst{21} = 1; // Writeback 1622 let Inst{20} = L_bit; 1623 let Inst{19-16} = Rn; 1624 let Inst{15-0} = regs; 1625 } 1626} 1627 1628let neverHasSideEffects = 1 in { 1629 1630let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 1631defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>; 1632 1633multiclass thumb2_st_mult<string asm, InstrItinClass itin, 1634 InstrItinClass itin_upd, bit L_bit> { 1635 def IA : 1636 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1637 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { 1638 bits<4> Rn; 1639 bits<16> regs; 1640 1641 let Inst{31-27} = 0b11101; 1642 let Inst{26-25} = 0b00; 1643 let Inst{24-23} = 0b01; // Increment After 1644 let Inst{22} = 0; 1645 let Inst{21} = 0; // No writeback 1646 let Inst{20} = L_bit; 1647 let Inst{19-16} = Rn; 1648 let Inst{15} = 0; 1649 let Inst{14} = regs{14}; 1650 let Inst{13} = 0; 1651 let Inst{12-0} = regs{12-0}; 1652 } 1653 def IA_UPD : 1654 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1655 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> { 1656 bits<4> Rn; 1657 bits<16> regs; 1658 1659 let Inst{31-27} = 0b11101; 1660 let Inst{26-25} = 0b00; 1661 let Inst{24-23} = 0b01; // Increment After 1662 let Inst{22} = 0; 1663 let Inst{21} = 1; // Writeback 1664 let Inst{20} = L_bit; 1665 let Inst{19-16} = Rn; 1666 let Inst{15} = 0; 1667 let Inst{14} = regs{14}; 1668 let Inst{13} = 0; 1669 let Inst{12-0} = regs{12-0}; 1670 } 1671 def DB : 1672 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1673 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> { 1674 bits<4> Rn; 1675 bits<16> regs; 1676 1677 let Inst{31-27} = 0b11101; 1678 let Inst{26-25} = 0b00; 1679 let Inst{24-23} = 0b10; // Decrement Before 1680 let Inst{22} = 0; 1681 let Inst{21} = 0; // No writeback 1682 let Inst{20} = L_bit; 1683 let Inst{19-16} = Rn; 1684 let Inst{15} = 0; 1685 let Inst{14} = regs{14}; 1686 let Inst{13} = 0; 1687 let Inst{12-0} = regs{12-0}; 1688 } 1689 def DB_UPD : 1690 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1691 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 1692 bits<4> Rn; 1693 bits<16> regs; 1694 1695 let Inst{31-27} = 0b11101; 1696 let Inst{26-25} = 0b00; 1697 let Inst{24-23} = 0b10; // Decrement Before 1698 let Inst{22} = 0; 1699 let Inst{21} = 1; // Writeback 1700 let Inst{20} = L_bit; 1701 let Inst{19-16} = Rn; 1702 let Inst{15} = 0; 1703 let Inst{14} = regs{14}; 1704 let Inst{13} = 0; 1705 let Inst{12-0} = regs{12-0}; 1706 } 1707} 1708 1709 1710let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 1711defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>; 1712 1713} // neverHasSideEffects 1714 1715 1716//===----------------------------------------------------------------------===// 1717// Move Instructions. 1718// 1719 1720let neverHasSideEffects = 1 in 1721def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr, 1722 "mov", ".w\t$Rd, $Rm", []> { 1723 let Inst{31-27} = 0b11101; 1724 let Inst{26-25} = 0b01; 1725 let Inst{24-21} = 0b0010; 1726 let Inst{19-16} = 0b1111; // Rn 1727 let Inst{14-12} = 0b000; 1728 let Inst{7-4} = 0b0000; 1729} 1730def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm, 1731 pred:$p, zero_reg)>; 1732def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm, 1733 pred:$p, CPSR)>; 1734def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm, 1735 pred:$p, CPSR)>; 1736 1737// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16. 1738let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 1739 AddedComplexity = 1 in 1740def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi, 1741 "mov", ".w\t$Rd, $imm", 1742 [(set rGPR:$Rd, t2_so_imm:$imm)]> { 1743 let Inst{31-27} = 0b11110; 1744 let Inst{25} = 0; 1745 let Inst{24-21} = 0b0010; 1746 let Inst{19-16} = 0b1111; // Rn 1747 let Inst{15} = 0; 1748} 1749 1750// cc_out is handled as part of the explicit mnemonic in the parser for 'mov'. 1751// Use aliases to get that to play nice here. 1752def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1753 pred:$p, CPSR)>; 1754def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1755 pred:$p, CPSR)>; 1756 1757def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1758 pred:$p, zero_reg)>; 1759def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1760 pred:$p, zero_reg)>; 1761 1762let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 1763def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi, 1764 "movw", "\t$Rd, $imm", 1765 [(set rGPR:$Rd, imm0_65535:$imm)]> { 1766 let Inst{31-27} = 0b11110; 1767 let Inst{25} = 1; 1768 let Inst{24-21} = 0b0010; 1769 let Inst{20} = 0; // The S bit. 1770 let Inst{15} = 0; 1771 1772 bits<4> Rd; 1773 bits<16> imm; 1774 1775 let Inst{11-8} = Rd; 1776 let Inst{19-16} = imm{15-12}; 1777 let Inst{26} = imm{11}; 1778 let Inst{14-12} = imm{10-8}; 1779 let Inst{7-0} = imm{7-0}; 1780 let DecoderMethod = "DecodeT2MOVTWInstruction"; 1781} 1782 1783def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 1784 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; 1785 1786let Constraints = "$src = $Rd" in { 1787def t2MOVTi16 : T2I<(outs rGPR:$Rd), 1788 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi, 1789 "movt", "\t$Rd, $imm", 1790 [(set rGPR:$Rd, 1791 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> { 1792 let Inst{31-27} = 0b11110; 1793 let Inst{25} = 1; 1794 let Inst{24-21} = 0b0110; 1795 let Inst{20} = 0; // The S bit. 1796 let Inst{15} = 0; 1797 1798 bits<4> Rd; 1799 bits<16> imm; 1800 1801 let Inst{11-8} = Rd; 1802 let Inst{19-16} = imm{15-12}; 1803 let Inst{26} = imm{11}; 1804 let Inst{14-12} = imm{10-8}; 1805 let Inst{7-0} = imm{7-0}; 1806 let DecoderMethod = "DecodeT2MOVTWInstruction"; 1807} 1808 1809def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 1810 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; 1811} // Constraints 1812 1813def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>; 1814 1815//===----------------------------------------------------------------------===// 1816// Extend Instructions. 1817// 1818 1819// Sign extenders 1820 1821def t2SXTB : T2I_ext_rrot<0b100, "sxtb", 1822 UnOpFrag<(sext_inreg node:$Src, i8)>>; 1823def t2SXTH : T2I_ext_rrot<0b000, "sxth", 1824 UnOpFrag<(sext_inreg node:$Src, i16)>>; 1825def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; 1826 1827def t2SXTAB : T2I_exta_rrot<0b100, "sxtab", 1828 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 1829def t2SXTAH : T2I_exta_rrot<0b000, "sxtah", 1830 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 1831def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">; 1832 1833// Zero extenders 1834 1835let AddedComplexity = 16 in { 1836def t2UXTB : T2I_ext_rrot<0b101, "uxtb", 1837 UnOpFrag<(and node:$Src, 0x000000FF)>>; 1838def t2UXTH : T2I_ext_rrot<0b001, "uxth", 1839 UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 1840def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16", 1841 UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 1842 1843// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 1844// The transformation should probably be done as a combiner action 1845// instead so we can include a check for masking back in the upper 1846// eight bits of the source into the lower eight bits of the result. 1847//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF), 1848// (t2UXTB16 rGPR:$Src, 3)>, 1849// Requires<[HasT2ExtractPack, IsThumb2]>; 1850def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), 1851 (t2UXTB16 rGPR:$Src, 1)>, 1852 Requires<[HasT2ExtractPack, IsThumb2]>; 1853 1854def t2UXTAB : T2I_exta_rrot<0b101, "uxtab", 1855 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 1856def t2UXTAH : T2I_exta_rrot<0b001, "uxtah", 1857 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 1858def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">; 1859} 1860 1861//===----------------------------------------------------------------------===// 1862// Arithmetic Instructions. 1863// 1864 1865defm t2ADD : T2I_bin_ii12rs<0b000, "add", 1866 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 1867defm t2SUB : T2I_bin_ii12rs<0b101, "sub", 1868 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1869 1870// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 1871// 1872// Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the 1873// selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by 1874// AdjustInstrPostInstrSelection where we determine whether or not to 1875// set the "s" bit based on CPSR liveness. 1876// 1877// FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen 1878// support for an optional CPSR definition that corresponds to the DAG 1879// node's second value. We can then eliminate the implicit def of CPSR. 1880defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, 1881 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; 1882defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, 1883 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 1884 1885let hasPostISelHook = 1 in { 1886defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", 1887 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; 1888defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", 1889 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 1890} 1891 1892// RSB 1893defm t2RSB : T2I_rbin_irs <0b1110, "rsb", 1894 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1895 1896// FIXME: Eliminate them if we can write def : Pat patterns which defines 1897// CPSR and the implicit def of CPSR is not needed. 1898defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 1899 1900// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1901// The assume-no-carry-in form uses the negation of the input since add/sub 1902// assume opposite meanings of the carry flag (i.e., carry == !borrow). 1903// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 1904// details. 1905// The AddedComplexity preferences the first variant over the others since 1906// it can be shrunk to a 16-bit wide encoding, while the others cannot. 1907let AddedComplexity = 1 in 1908def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), 1909 (t2SUBri GPR:$src, imm0_255_neg:$imm)>; 1910def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 1911 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 1912def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 1913 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 1914let AddedComplexity = 1 in 1915def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm), 1916 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>; 1917def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm), 1918 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>; 1919// The with-carry-in form matches bitwise not instead of the negation. 1920// Effectively, the inverse interpretation of the carry flag already accounts 1921// for part of the negation. 1922let AddedComplexity = 1 in 1923def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR), 1924 (t2SBCri rGPR:$src, imm0_255_not:$imm)>; 1925def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR), 1926 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>; 1927 1928// Select Bytes -- for disassembly only 1929 1930def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1931 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>, 1932 Requires<[IsThumb2, HasThumb2DSP]> { 1933 let Inst{31-27} = 0b11111; 1934 let Inst{26-24} = 0b010; 1935 let Inst{23} = 0b1; 1936 let Inst{22-20} = 0b010; 1937 let Inst{15-12} = 0b1111; 1938 let Inst{7} = 0b1; 1939 let Inst{6-4} = 0b000; 1940} 1941 1942// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned) 1943// And Miscellaneous operations -- for disassembly only 1944class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc, 1945 list<dag> pat = [/* For disassembly only; pattern left blank */], 1946 dag iops = (ins rGPR:$Rn, rGPR:$Rm), 1947 string asm = "\t$Rd, $Rn, $Rm"> 1948 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>, 1949 Requires<[IsThumb2, HasThumb2DSP]> { 1950 let Inst{31-27} = 0b11111; 1951 let Inst{26-23} = 0b0101; 1952 let Inst{22-20} = op22_20; 1953 let Inst{15-12} = 0b1111; 1954 let Inst{7-4} = op7_4; 1955 1956 bits<4> Rd; 1957 bits<4> Rn; 1958 bits<4> Rm; 1959 1960 let Inst{11-8} = Rd; 1961 let Inst{19-16} = Rn; 1962 let Inst{3-0} = Rm; 1963} 1964 1965// Saturating add/subtract -- for disassembly only 1966 1967def t2QADD : T2I_pam<0b000, 0b1000, "qadd", 1968 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))], 1969 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1970def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">; 1971def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">; 1972def t2QASX : T2I_pam<0b010, 0b0001, "qasx">; 1973def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [], 1974 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1975def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [], 1976 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1977def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">; 1978def t2QSUB : T2I_pam<0b000, 0b1010, "qsub", 1979 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))], 1980 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1981def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">; 1982def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">; 1983def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">; 1984def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">; 1985def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">; 1986def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">; 1987def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">; 1988def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">; 1989 1990// Signed/Unsigned add/subtract -- for disassembly only 1991 1992def t2SASX : T2I_pam<0b010, 0b0000, "sasx">; 1993def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">; 1994def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">; 1995def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">; 1996def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">; 1997def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">; 1998def t2UASX : T2I_pam<0b010, 0b0100, "uasx">; 1999def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">; 2000def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">; 2001def t2USAX : T2I_pam<0b110, 0b0100, "usax">; 2002def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">; 2003def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">; 2004 2005// Signed/Unsigned halving add/subtract -- for disassembly only 2006 2007def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">; 2008def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">; 2009def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">; 2010def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">; 2011def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">; 2012def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">; 2013def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">; 2014def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">; 2015def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">; 2016def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">; 2017def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">; 2018def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">; 2019 2020// Helper class for disassembly only 2021// A6.3.16 & A6.3.17 2022// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions. 2023class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 2024 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 2025 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 2026 let Inst{31-27} = 0b11111; 2027 let Inst{26-24} = 0b011; 2028 let Inst{23} = long; 2029 let Inst{22-20} = op22_20; 2030 let Inst{7-4} = op7_4; 2031} 2032 2033class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 2034 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 2035 : T2FourReg<oops, iops, itin, opc, asm, pattern> { 2036 let Inst{31-27} = 0b11111; 2037 let Inst{26-24} = 0b011; 2038 let Inst{23} = long; 2039 let Inst{22-20} = op22_20; 2040 let Inst{7-4} = op7_4; 2041} 2042 2043// Unsigned Sum of Absolute Differences [and Accumulate]. 2044def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 2045 (ins rGPR:$Rn, rGPR:$Rm), 2046 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>, 2047 Requires<[IsThumb2, HasThumb2DSP]> { 2048 let Inst{15-12} = 0b1111; 2049} 2050def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 2051 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary, 2052 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>, 2053 Requires<[IsThumb2, HasThumb2DSP]>; 2054 2055// Signed/Unsigned saturate. 2056class T2SatI<dag oops, dag iops, InstrItinClass itin, 2057 string opc, string asm, list<dag> pattern> 2058 : T2I<oops, iops, itin, opc, asm, pattern> { 2059 bits<4> Rd; 2060 bits<4> Rn; 2061 bits<5> sat_imm; 2062 bits<7> sh; 2063 2064 let Inst{11-8} = Rd; 2065 let Inst{19-16} = Rn; 2066 let Inst{4-0} = sat_imm; 2067 let Inst{21} = sh{5}; 2068 let Inst{14-12} = sh{4-2}; 2069 let Inst{7-6} = sh{1-0}; 2070} 2071 2072def t2SSAT: T2SatI< 2073 (outs rGPR:$Rd), 2074 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), 2075 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { 2076 let Inst{31-27} = 0b11110; 2077 let Inst{25-22} = 0b1100; 2078 let Inst{20} = 0; 2079 let Inst{15} = 0; 2080 let Inst{5} = 0; 2081} 2082 2083def t2SSAT16: T2SatI< 2084 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary, 2085 "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 2086 Requires<[IsThumb2, HasThumb2DSP]> { 2087 let Inst{31-27} = 0b11110; 2088 let Inst{25-22} = 0b1100; 2089 let Inst{20} = 0; 2090 let Inst{15} = 0; 2091 let Inst{21} = 1; // sh = '1' 2092 let Inst{14-12} = 0b000; // imm3 = '000' 2093 let Inst{7-6} = 0b00; // imm2 = '00' 2094 let Inst{5-4} = 0b00; 2095} 2096 2097def t2USAT: T2SatI< 2098 (outs rGPR:$Rd), 2099 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), 2100 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { 2101 let Inst{31-27} = 0b11110; 2102 let Inst{25-22} = 0b1110; 2103 let Inst{20} = 0; 2104 let Inst{15} = 0; 2105} 2106 2107def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn), 2108 NoItinerary, 2109 "usat16", "\t$Rd, $sat_imm, $Rn", []>, 2110 Requires<[IsThumb2, HasThumb2DSP]> { 2111 let Inst{31-22} = 0b1111001110; 2112 let Inst{20} = 0; 2113 let Inst{15} = 0; 2114 let Inst{21} = 1; // sh = '1' 2115 let Inst{14-12} = 0b000; // imm3 = '000' 2116 let Inst{7-6} = 0b00; // imm2 = '00' 2117 let Inst{5-4} = 0b00; 2118} 2119 2120def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>; 2121def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>; 2122 2123//===----------------------------------------------------------------------===// 2124// Shift and rotate Instructions. 2125// 2126 2127defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31, 2128 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">; 2129defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, 2130 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">; 2131defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, 2132 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">; 2133defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31, 2134 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">; 2135 2136// (rotr x, (and y, 0x...1f)) ==> (ROR x, y) 2137def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)), 2138 (t2RORrr rGPR:$lhs, rGPR:$rhs)>; 2139 2140let Uses = [CPSR] in { 2141def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2142 "rrx", "\t$Rd, $Rm", 2143 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> { 2144 let Inst{31-27} = 0b11101; 2145 let Inst{26-25} = 0b01; 2146 let Inst{24-21} = 0b0010; 2147 let Inst{19-16} = 0b1111; // Rn 2148 let Inst{14-12} = 0b000; 2149 let Inst{7-4} = 0b0011; 2150} 2151} 2152 2153let isCodeGenOnly = 1, Defs = [CPSR] in { 2154def t2MOVsrl_flag : T2TwoRegShiftImm< 2155 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2156 "lsrs", ".w\t$Rd, $Rm, #1", 2157 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> { 2158 let Inst{31-27} = 0b11101; 2159 let Inst{26-25} = 0b01; 2160 let Inst{24-21} = 0b0010; 2161 let Inst{20} = 1; // The S bit. 2162 let Inst{19-16} = 0b1111; // Rn 2163 let Inst{5-4} = 0b01; // Shift type. 2164 // Shift amount = Inst{14-12:7-6} = 1. 2165 let Inst{14-12} = 0b000; 2166 let Inst{7-6} = 0b01; 2167} 2168def t2MOVsra_flag : T2TwoRegShiftImm< 2169 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2170 "asrs", ".w\t$Rd, $Rm, #1", 2171 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> { 2172 let Inst{31-27} = 0b11101; 2173 let Inst{26-25} = 0b01; 2174 let Inst{24-21} = 0b0010; 2175 let Inst{20} = 1; // The S bit. 2176 let Inst{19-16} = 0b1111; // Rn 2177 let Inst{5-4} = 0b10; // Shift type. 2178 // Shift amount = Inst{14-12:7-6} = 1. 2179 let Inst{14-12} = 0b000; 2180 let Inst{7-6} = 0b01; 2181} 2182} 2183 2184//===----------------------------------------------------------------------===// 2185// Bitwise Instructions. 2186// 2187 2188defm t2AND : T2I_bin_w_irs<0b0000, "and", 2189 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2190 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>; 2191defm t2ORR : T2I_bin_w_irs<0b0010, "orr", 2192 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2193 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>; 2194defm t2EOR : T2I_bin_w_irs<0b0100, "eor", 2195 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2196 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>; 2197 2198defm t2BIC : T2I_bin_w_irs<0b0001, "bic", 2199 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2200 BinOpFrag<(and node:$LHS, (not node:$RHS))>, 2201 "t2BIC">; 2202 2203class T2BitFI<dag oops, dag iops, InstrItinClass itin, 2204 string opc, string asm, list<dag> pattern> 2205 : T2I<oops, iops, itin, opc, asm, pattern> { 2206 bits<4> Rd; 2207 bits<5> msb; 2208 bits<5> lsb; 2209 2210 let Inst{11-8} = Rd; 2211 let Inst{4-0} = msb{4-0}; 2212 let Inst{14-12} = lsb{4-2}; 2213 let Inst{7-6} = lsb{1-0}; 2214} 2215 2216class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin, 2217 string opc, string asm, list<dag> pattern> 2218 : T2BitFI<oops, iops, itin, opc, asm, pattern> { 2219 bits<4> Rn; 2220 2221 let Inst{19-16} = Rn; 2222} 2223 2224let Constraints = "$src = $Rd" in 2225def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm), 2226 IIC_iUNAsi, "bfc", "\t$Rd, $imm", 2227 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> { 2228 let Inst{31-27} = 0b11110; 2229 let Inst{26} = 0; // should be 0. 2230 let Inst{25} = 1; 2231 let Inst{24-20} = 0b10110; 2232 let Inst{19-16} = 0b1111; // Rn 2233 let Inst{15} = 0; 2234 let Inst{5} = 0; // should be 0. 2235 2236 bits<10> imm; 2237 let msb{4-0} = imm{9-5}; 2238 let lsb{4-0} = imm{4-0}; 2239} 2240 2241def t2SBFX: T2TwoRegBitFI< 2242 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2243 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> { 2244 let Inst{31-27} = 0b11110; 2245 let Inst{25} = 1; 2246 let Inst{24-20} = 0b10100; 2247 let Inst{15} = 0; 2248} 2249 2250def t2UBFX: T2TwoRegBitFI< 2251 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2252 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> { 2253 let Inst{31-27} = 0b11110; 2254 let Inst{25} = 1; 2255 let Inst{24-20} = 0b11100; 2256 let Inst{15} = 0; 2257} 2258 2259// A8.6.18 BFI - Bitfield insert (Encoding T1) 2260let Constraints = "$src = $Rd" in { 2261 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd), 2262 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm), 2263 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm", 2264 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn, 2265 bf_inv_mask_imm:$imm))]> { 2266 let Inst{31-27} = 0b11110; 2267 let Inst{26} = 0; // should be 0. 2268 let Inst{25} = 1; 2269 let Inst{24-20} = 0b10110; 2270 let Inst{15} = 0; 2271 let Inst{5} = 0; // should be 0. 2272 2273 bits<10> imm; 2274 let msb{4-0} = imm{9-5}; 2275 let lsb{4-0} = imm{4-0}; 2276 } 2277} 2278 2279defm t2ORN : T2I_bin_irs<0b0011, "orn", 2280 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2281 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 2282 "t2ORN", 0, "">; 2283 2284/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 2285/// unary operation that produces a value. These are predicable and can be 2286/// changed to modify CPSR. 2287multiclass T2I_un_irs<bits<4> opcod, string opc, 2288 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 2289 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> { 2290 // shifted imm 2291 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii, 2292 opc, "\t$Rd, $imm", 2293 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> { 2294 let isAsCheapAsAMove = Cheap; 2295 let isReMaterializable = ReMat; 2296 let Inst{31-27} = 0b11110; 2297 let Inst{25} = 0; 2298 let Inst{24-21} = opcod; 2299 let Inst{19-16} = 0b1111; // Rn 2300 let Inst{15} = 0; 2301 } 2302 // register 2303 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir, 2304 opc, ".w\t$Rd, $Rm", 2305 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> { 2306 let Inst{31-27} = 0b11101; 2307 let Inst{26-25} = 0b01; 2308 let Inst{24-21} = opcod; 2309 let Inst{19-16} = 0b1111; // Rn 2310 let Inst{14-12} = 0b000; // imm3 2311 let Inst{7-6} = 0b00; // imm2 2312 let Inst{5-4} = 0b00; // type 2313 } 2314 // shifted register 2315 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis, 2316 opc, ".w\t$Rd, $ShiftedRm", 2317 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> { 2318 let Inst{31-27} = 0b11101; 2319 let Inst{26-25} = 0b01; 2320 let Inst{24-21} = opcod; 2321 let Inst{19-16} = 0b1111; // Rn 2322 } 2323} 2324 2325// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 2326let AddedComplexity = 1 in 2327defm t2MVN : T2I_un_irs <0b0011, "mvn", 2328 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi, 2329 UnOpFrag<(not node:$Src)>, 1, 1>; 2330 2331let AddedComplexity = 1 in 2332def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm), 2333 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>; 2334 2335// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 2336def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm), 2337 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>, 2338 Requires<[IsThumb2]>; 2339 2340def : T2Pat<(t2_so_imm_not:$src), 2341 (t2MVNi t2_so_imm_not:$src)>; 2342 2343//===----------------------------------------------------------------------===// 2344// Multiply Instructions. 2345// 2346let isCommutable = 1 in 2347def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2348 "mul", "\t$Rd, $Rn, $Rm", 2349 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> { 2350 let Inst{31-27} = 0b11111; 2351 let Inst{26-23} = 0b0110; 2352 let Inst{22-20} = 0b000; 2353 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2354 let Inst{7-4} = 0b0000; // Multiply 2355} 2356 2357def t2MLA: T2FourReg< 2358 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2359 "mla", "\t$Rd, $Rn, $Rm, $Ra", 2360 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> { 2361 let Inst{31-27} = 0b11111; 2362 let Inst{26-23} = 0b0110; 2363 let Inst{22-20} = 0b000; 2364 let Inst{7-4} = 0b0000; // Multiply 2365} 2366 2367def t2MLS: T2FourReg< 2368 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2369 "mls", "\t$Rd, $Rn, $Rm, $Ra", 2370 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> { 2371 let Inst{31-27} = 0b11111; 2372 let Inst{26-23} = 0b0110; 2373 let Inst{22-20} = 0b000; 2374 let Inst{7-4} = 0b0001; // Multiply and Subtract 2375} 2376 2377// Extra precision multiplies with low / high results 2378let neverHasSideEffects = 1 in { 2379let isCommutable = 1 in { 2380def t2SMULL : T2MulLong<0b000, 0b0000, 2381 (outs rGPR:$RdLo, rGPR:$RdHi), 2382 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, 2383 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2384 2385def t2UMULL : T2MulLong<0b010, 0b0000, 2386 (outs rGPR:$RdLo, rGPR:$RdHi), 2387 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, 2388 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2389} // isCommutable 2390 2391// Multiply + accumulate 2392def t2SMLAL : T2MulLong<0b100, 0b0000, 2393 (outs rGPR:$RdLo, rGPR:$RdHi), 2394 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, 2395 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2396 2397def t2UMLAL : T2MulLong<0b110, 0b0000, 2398 (outs rGPR:$RdLo, rGPR:$RdHi), 2399 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, 2400 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2401 2402def t2UMAAL : T2MulLong<0b110, 0b0110, 2403 (outs rGPR:$RdLo, rGPR:$RdHi), 2404 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, 2405 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 2406 Requires<[IsThumb2, HasThumb2DSP]>; 2407} // neverHasSideEffects 2408 2409// Rounding variants of the below included for disassembly only 2410 2411// Most significant word multiply 2412def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2413 "smmul", "\t$Rd, $Rn, $Rm", 2414 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>, 2415 Requires<[IsThumb2, HasThumb2DSP]> { 2416 let Inst{31-27} = 0b11111; 2417 let Inst{26-23} = 0b0110; 2418 let Inst{22-20} = 0b101; 2419 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2420 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2421} 2422 2423def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2424 "smmulr", "\t$Rd, $Rn, $Rm", []>, 2425 Requires<[IsThumb2, HasThumb2DSP]> { 2426 let Inst{31-27} = 0b11111; 2427 let Inst{26-23} = 0b0110; 2428 let Inst{22-20} = 0b101; 2429 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2430 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2431} 2432 2433def t2SMMLA : T2FourReg< 2434 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2435 "smmla", "\t$Rd, $Rn, $Rm, $Ra", 2436 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>, 2437 Requires<[IsThumb2, HasThumb2DSP]> { 2438 let Inst{31-27} = 0b11111; 2439 let Inst{26-23} = 0b0110; 2440 let Inst{22-20} = 0b101; 2441 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2442} 2443 2444def t2SMMLAR: T2FourReg< 2445 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2446 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 2447 Requires<[IsThumb2, HasThumb2DSP]> { 2448 let Inst{31-27} = 0b11111; 2449 let Inst{26-23} = 0b0110; 2450 let Inst{22-20} = 0b101; 2451 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2452} 2453 2454def t2SMMLS: T2FourReg< 2455 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2456 "smmls", "\t$Rd, $Rn, $Rm, $Ra", 2457 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>, 2458 Requires<[IsThumb2, HasThumb2DSP]> { 2459 let Inst{31-27} = 0b11111; 2460 let Inst{26-23} = 0b0110; 2461 let Inst{22-20} = 0b110; 2462 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2463} 2464 2465def t2SMMLSR:T2FourReg< 2466 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2467 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 2468 Requires<[IsThumb2, HasThumb2DSP]> { 2469 let Inst{31-27} = 0b11111; 2470 let Inst{26-23} = 0b0110; 2471 let Inst{22-20} = 0b110; 2472 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2473} 2474 2475multiclass T2I_smul<string opc, PatFrag opnode> { 2476 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2477 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 2478 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16), 2479 (sext_inreg rGPR:$Rm, i16)))]>, 2480 Requires<[IsThumb2, HasThumb2DSP]> { 2481 let Inst{31-27} = 0b11111; 2482 let Inst{26-23} = 0b0110; 2483 let Inst{22-20} = 0b001; 2484 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2485 let Inst{7-6} = 0b00; 2486 let Inst{5-4} = 0b00; 2487 } 2488 2489 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2490 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 2491 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16), 2492 (sra rGPR:$Rm, (i32 16))))]>, 2493 Requires<[IsThumb2, HasThumb2DSP]> { 2494 let Inst{31-27} = 0b11111; 2495 let Inst{26-23} = 0b0110; 2496 let Inst{22-20} = 0b001; 2497 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2498 let Inst{7-6} = 0b00; 2499 let Inst{5-4} = 0b01; 2500 } 2501 2502 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2503 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 2504 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)), 2505 (sext_inreg rGPR:$Rm, i16)))]>, 2506 Requires<[IsThumb2, HasThumb2DSP]> { 2507 let Inst{31-27} = 0b11111; 2508 let Inst{26-23} = 0b0110; 2509 let Inst{22-20} = 0b001; 2510 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2511 let Inst{7-6} = 0b00; 2512 let Inst{5-4} = 0b10; 2513 } 2514 2515 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2516 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 2517 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)), 2518 (sra rGPR:$Rm, (i32 16))))]>, 2519 Requires<[IsThumb2, HasThumb2DSP]> { 2520 let Inst{31-27} = 0b11111; 2521 let Inst{26-23} = 0b0110; 2522 let Inst{22-20} = 0b001; 2523 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2524 let Inst{7-6} = 0b00; 2525 let Inst{5-4} = 0b11; 2526 } 2527 2528 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2529 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 2530 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn, 2531 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>, 2532 Requires<[IsThumb2, HasThumb2DSP]> { 2533 let Inst{31-27} = 0b11111; 2534 let Inst{26-23} = 0b0110; 2535 let Inst{22-20} = 0b011; 2536 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2537 let Inst{7-6} = 0b00; 2538 let Inst{5-4} = 0b00; 2539 } 2540 2541 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2542 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 2543 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn, 2544 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>, 2545 Requires<[IsThumb2, HasThumb2DSP]> { 2546 let Inst{31-27} = 0b11111; 2547 let Inst{26-23} = 0b0110; 2548 let Inst{22-20} = 0b011; 2549 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2550 let Inst{7-6} = 0b00; 2551 let Inst{5-4} = 0b01; 2552 } 2553} 2554 2555 2556multiclass T2I_smla<string opc, PatFrag opnode> { 2557 def BB : T2FourReg< 2558 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2559 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 2560 [(set rGPR:$Rd, (add rGPR:$Ra, 2561 (opnode (sext_inreg rGPR:$Rn, i16), 2562 (sext_inreg rGPR:$Rm, i16))))]>, 2563 Requires<[IsThumb2, HasThumb2DSP]> { 2564 let Inst{31-27} = 0b11111; 2565 let Inst{26-23} = 0b0110; 2566 let Inst{22-20} = 0b001; 2567 let Inst{7-6} = 0b00; 2568 let Inst{5-4} = 0b00; 2569 } 2570 2571 def BT : T2FourReg< 2572 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2573 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 2574 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16), 2575 (sra rGPR:$Rm, (i32 16)))))]>, 2576 Requires<[IsThumb2, HasThumb2DSP]> { 2577 let Inst{31-27} = 0b11111; 2578 let Inst{26-23} = 0b0110; 2579 let Inst{22-20} = 0b001; 2580 let Inst{7-6} = 0b00; 2581 let Inst{5-4} = 0b01; 2582 } 2583 2584 def TB : T2FourReg< 2585 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2586 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 2587 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)), 2588 (sext_inreg rGPR:$Rm, i16))))]>, 2589 Requires<[IsThumb2, HasThumb2DSP]> { 2590 let Inst{31-27} = 0b11111; 2591 let Inst{26-23} = 0b0110; 2592 let Inst{22-20} = 0b001; 2593 let Inst{7-6} = 0b00; 2594 let Inst{5-4} = 0b10; 2595 } 2596 2597 def TT : T2FourReg< 2598 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2599 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 2600 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)), 2601 (sra rGPR:$Rm, (i32 16)))))]>, 2602 Requires<[IsThumb2, HasThumb2DSP]> { 2603 let Inst{31-27} = 0b11111; 2604 let Inst{26-23} = 0b0110; 2605 let Inst{22-20} = 0b001; 2606 let Inst{7-6} = 0b00; 2607 let Inst{5-4} = 0b11; 2608 } 2609 2610 def WB : T2FourReg< 2611 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2612 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 2613 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn, 2614 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>, 2615 Requires<[IsThumb2, HasThumb2DSP]> { 2616 let Inst{31-27} = 0b11111; 2617 let Inst{26-23} = 0b0110; 2618 let Inst{22-20} = 0b011; 2619 let Inst{7-6} = 0b00; 2620 let Inst{5-4} = 0b00; 2621 } 2622 2623 def WT : T2FourReg< 2624 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2625 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 2626 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn, 2627 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>, 2628 Requires<[IsThumb2, HasThumb2DSP]> { 2629 let Inst{31-27} = 0b11111; 2630 let Inst{26-23} = 0b0110; 2631 let Inst{22-20} = 0b011; 2632 let Inst{7-6} = 0b00; 2633 let Inst{5-4} = 0b01; 2634 } 2635} 2636 2637defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2638defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2639 2640// Halfword multiple accumulate long: SMLAL<x><y> 2641def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd), 2642 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm", 2643 [/* For disassembly only; pattern left blank */]>, 2644 Requires<[IsThumb2, HasThumb2DSP]>; 2645def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd), 2646 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm", 2647 [/* For disassembly only; pattern left blank */]>, 2648 Requires<[IsThumb2, HasThumb2DSP]>; 2649def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd), 2650 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm", 2651 [/* For disassembly only; pattern left blank */]>, 2652 Requires<[IsThumb2, HasThumb2DSP]>; 2653def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd), 2654 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm", 2655 [/* For disassembly only; pattern left blank */]>, 2656 Requires<[IsThumb2, HasThumb2DSP]>; 2657 2658// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 2659def t2SMUAD: T2ThreeReg_mac< 2660 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2661 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>, 2662 Requires<[IsThumb2, HasThumb2DSP]> { 2663 let Inst{15-12} = 0b1111; 2664} 2665def t2SMUADX:T2ThreeReg_mac< 2666 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2667 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>, 2668 Requires<[IsThumb2, HasThumb2DSP]> { 2669 let Inst{15-12} = 0b1111; 2670} 2671def t2SMUSD: T2ThreeReg_mac< 2672 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2673 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>, 2674 Requires<[IsThumb2, HasThumb2DSP]> { 2675 let Inst{15-12} = 0b1111; 2676} 2677def t2SMUSDX:T2ThreeReg_mac< 2678 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2679 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>, 2680 Requires<[IsThumb2, HasThumb2DSP]> { 2681 let Inst{15-12} = 0b1111; 2682} 2683def t2SMLAD : T2FourReg_mac< 2684 0, 0b010, 0b0000, (outs rGPR:$Rd), 2685 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad", 2686 "\t$Rd, $Rn, $Rm, $Ra", []>, 2687 Requires<[IsThumb2, HasThumb2DSP]>; 2688def t2SMLADX : T2FourReg_mac< 2689 0, 0b010, 0b0001, (outs rGPR:$Rd), 2690 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx", 2691 "\t$Rd, $Rn, $Rm, $Ra", []>, 2692 Requires<[IsThumb2, HasThumb2DSP]>; 2693def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd), 2694 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd", 2695 "\t$Rd, $Rn, $Rm, $Ra", []>, 2696 Requires<[IsThumb2, HasThumb2DSP]>; 2697def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd), 2698 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx", 2699 "\t$Rd, $Rn, $Rm, $Ra", []>, 2700 Requires<[IsThumb2, HasThumb2DSP]>; 2701def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd), 2702 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald", 2703 "\t$Ra, $Rd, $Rn, $Rm", []>, 2704 Requires<[IsThumb2, HasThumb2DSP]>; 2705def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd), 2706 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx", 2707 "\t$Ra, $Rd, $Rn, $Rm", []>, 2708 Requires<[IsThumb2, HasThumb2DSP]>; 2709def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd), 2710 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld", 2711 "\t$Ra, $Rd, $Rn, $Rm", []>, 2712 Requires<[IsThumb2, HasThumb2DSP]>; 2713def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd), 2714 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx", 2715 "\t$Ra, $Rd, $Rn, $Rm", []>, 2716 Requires<[IsThumb2, HasThumb2DSP]>; 2717 2718//===----------------------------------------------------------------------===// 2719// Division Instructions. 2720// Signed and unsigned division on v7-M 2721// 2722def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi, 2723 "sdiv", "\t$Rd, $Rn, $Rm", 2724 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>, 2725 Requires<[HasDivide, IsThumb2]> { 2726 let Inst{31-27} = 0b11111; 2727 let Inst{26-21} = 0b011100; 2728 let Inst{20} = 0b1; 2729 let Inst{15-12} = 0b1111; 2730 let Inst{7-4} = 0b1111; 2731} 2732 2733def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi, 2734 "udiv", "\t$Rd, $Rn, $Rm", 2735 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>, 2736 Requires<[HasDivide, IsThumb2]> { 2737 let Inst{31-27} = 0b11111; 2738 let Inst{26-21} = 0b011101; 2739 let Inst{20} = 0b1; 2740 let Inst{15-12} = 0b1111; 2741 let Inst{7-4} = 0b1111; 2742} 2743 2744//===----------------------------------------------------------------------===// 2745// Misc. Arithmetic Instructions. 2746// 2747 2748class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, 2749 InstrItinClass itin, string opc, string asm, list<dag> pattern> 2750 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 2751 let Inst{31-27} = 0b11111; 2752 let Inst{26-22} = 0b01010; 2753 let Inst{21-20} = op1; 2754 let Inst{15-12} = 0b1111; 2755 let Inst{7-6} = 0b10; 2756 let Inst{5-4} = op2; 2757 let Rn{3-0} = Rm; 2758} 2759 2760def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2761 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>; 2762 2763def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2764 "rbit", "\t$Rd, $Rm", 2765 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>; 2766 2767def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2768 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>; 2769 2770def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2771 "rev16", ".w\t$Rd, $Rm", 2772 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>; 2773 2774def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2775 "revsh", ".w\t$Rd, $Rm", 2776 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>; 2777 2778def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)), 2779 (and (srl rGPR:$Rm, (i32 8)), 0xFF)), 2780 (t2REVSH rGPR:$Rm)>; 2781 2782def t2PKHBT : T2ThreeReg< 2783 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh), 2784 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 2785 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF), 2786 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh), 2787 0xFFFF0000)))]>, 2788 Requires<[HasT2ExtractPack, IsThumb2]> { 2789 let Inst{31-27} = 0b11101; 2790 let Inst{26-25} = 0b01; 2791 let Inst{24-20} = 0b01100; 2792 let Inst{5} = 0; // BT form 2793 let Inst{4} = 0; 2794 2795 bits<5> sh; 2796 let Inst{14-12} = sh{4-2}; 2797 let Inst{7-6} = sh{1-0}; 2798} 2799 2800// Alternate cases for PKHBT where identities eliminate some nodes. 2801def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)), 2802 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>, 2803 Requires<[HasT2ExtractPack, IsThumb2]>; 2804def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)), 2805 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 2806 Requires<[HasT2ExtractPack, IsThumb2]>; 2807 2808// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 2809// will match the pattern below. 2810def t2PKHTB : T2ThreeReg< 2811 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh), 2812 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 2813 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000), 2814 (and (sra rGPR:$Rm, pkh_asr_amt:$sh), 2815 0xFFFF)))]>, 2816 Requires<[HasT2ExtractPack, IsThumb2]> { 2817 let Inst{31-27} = 0b11101; 2818 let Inst{26-25} = 0b01; 2819 let Inst{24-20} = 0b01100; 2820 let Inst{5} = 1; // TB form 2821 let Inst{4} = 0; 2822 2823 bits<5> sh; 2824 let Inst{14-12} = sh{4-2}; 2825 let Inst{7-6} = sh{1-0}; 2826} 2827 2828// Alternate cases for PKHTB where identities eliminate some nodes. Note that 2829// a shift amount of 0 is *not legal* here, it is PKHBT instead. 2830def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)), 2831 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 2832 Requires<[HasT2ExtractPack, IsThumb2]>; 2833def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), 2834 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)), 2835 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>, 2836 Requires<[HasT2ExtractPack, IsThumb2]>; 2837 2838//===----------------------------------------------------------------------===// 2839// Comparison Instructions... 2840// 2841defm t2CMP : T2I_cmp_irs<0b1101, "cmp", 2842 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, 2843 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">; 2844 2845def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm), 2846 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>; 2847def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs), 2848 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>; 2849def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs), 2850 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>; 2851 2852let isCompare = 1, Defs = [CPSR] in { 2853 // shifted imm 2854 def t2CMNri : T2OneRegCmpImm< 2855 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi, 2856 "cmn", ".w\t$Rn, $imm", 2857 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]> { 2858 let Inst{31-27} = 0b11110; 2859 let Inst{25} = 0; 2860 let Inst{24-21} = 0b1000; 2861 let Inst{20} = 1; // The S bit. 2862 let Inst{15} = 0; 2863 let Inst{11-8} = 0b1111; // Rd 2864 } 2865 // register 2866 def t2CMNzrr : T2TwoRegCmp< 2867 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr, 2868 "cmn", ".w\t$Rn, $Rm", 2869 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 2870 GPRnopc:$Rn, rGPR:$Rm)]> { 2871 let Inst{31-27} = 0b11101; 2872 let Inst{26-25} = 0b01; 2873 let Inst{24-21} = 0b1000; 2874 let Inst{20} = 1; // The S bit. 2875 let Inst{14-12} = 0b000; // imm3 2876 let Inst{11-8} = 0b1111; // Rd 2877 let Inst{7-6} = 0b00; // imm2 2878 let Inst{5-4} = 0b00; // type 2879 } 2880 // shifted register 2881 def t2CMNzrs : T2OneRegCmpShiftedReg< 2882 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi, 2883 "cmn", ".w\t$Rn, $ShiftedRm", 2884 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 2885 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> { 2886 let Inst{31-27} = 0b11101; 2887 let Inst{26-25} = 0b01; 2888 let Inst{24-21} = 0b1000; 2889 let Inst{20} = 1; // The S bit. 2890 let Inst{11-8} = 0b1111; // Rd 2891 } 2892} 2893 2894// Assembler aliases w/o the ".w" suffix. 2895// No alias here for 'rr' version as not all instantiations of this multiclass 2896// want one (CMP in particular, does not). 2897def : t2InstAlias<!strconcat("cmn", "${p}", " $Rn, $imm"), 2898 (!cast<Instruction>(!strconcat("t2CMN", "ri")) GPRnopc:$Rn, 2899 t2_so_imm:$imm, pred:$p)>; 2900def : t2InstAlias<!strconcat("cmn", "${p}", " $Rn, $shift"), 2901 (!cast<Instruction>(!strconcat("t2CMNz", "rs")) GPRnopc:$Rn, 2902 t2_so_reg:$shift, 2903 pred:$p)>; 2904 2905def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 2906 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 2907 2908def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm), 2909 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>; 2910 2911defm t2TST : T2I_cmp_irs<0b0000, "tst", 2912 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 2913 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 2914 "t2TST">; 2915defm t2TEQ : T2I_cmp_irs<0b0100, "teq", 2916 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 2917 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 2918 "t2TEQ">; 2919 2920// Conditional moves 2921// FIXME: should be able to write a pattern for ARMcmov, but can't use 2922// a two-value operand where a dag node expects two operands. :( 2923let neverHasSideEffects = 1 in { 2924 2925let isCommutable = 1 in 2926def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd), 2927 (ins rGPR:$false, rGPR:$Rm, pred:$p), 2928 4, IIC_iCMOVr, 2929 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>, 2930 RegConstraint<"$false = $Rd">; 2931 2932let isMoveImm = 1 in 2933def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd), 2934 (ins rGPR:$false, t2_so_imm:$imm, pred:$p), 2935 4, IIC_iCMOVi, 2936[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>, 2937 RegConstraint<"$false = $Rd">; 2938 2939// FIXME: Pseudo-ize these. For now, just mark codegen only. 2940let isCodeGenOnly = 1 in { 2941let isMoveImm = 1 in 2942def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm), 2943 IIC_iCMOVi, 2944 "movw", "\t$Rd, $imm", []>, 2945 RegConstraint<"$false = $Rd"> { 2946 let Inst{31-27} = 0b11110; 2947 let Inst{25} = 1; 2948 let Inst{24-21} = 0b0010; 2949 let Inst{20} = 0; // The S bit. 2950 let Inst{15} = 0; 2951 2952 bits<4> Rd; 2953 bits<16> imm; 2954 2955 let Inst{11-8} = Rd; 2956 let Inst{19-16} = imm{15-12}; 2957 let Inst{26} = imm{11}; 2958 let Inst{14-12} = imm{10-8}; 2959 let Inst{7-0} = imm{7-0}; 2960} 2961 2962let isMoveImm = 1 in 2963def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst), 2964 (ins rGPR:$false, i32imm:$src, pred:$p), 2965 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">; 2966 2967let isMoveImm = 1 in 2968def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm), 2969 IIC_iCMOVi, "mvn", "\t$Rd, $imm", 2970[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm, 2971 imm:$cc, CCR:$ccr))*/]>, 2972 RegConstraint<"$false = $Rd"> { 2973 let Inst{31-27} = 0b11110; 2974 let Inst{25} = 0; 2975 let Inst{24-21} = 0b0011; 2976 let Inst{20} = 0; // The S bit. 2977 let Inst{19-16} = 0b1111; // Rn 2978 let Inst{15} = 0; 2979} 2980 2981class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 2982 string opc, string asm, list<dag> pattern> 2983 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> { 2984 let Inst{31-27} = 0b11101; 2985 let Inst{26-25} = 0b01; 2986 let Inst{24-21} = 0b0010; 2987 let Inst{20} = 0; // The S bit. 2988 let Inst{19-16} = 0b1111; // Rn 2989 let Inst{5-4} = opcod; // Shift type. 2990} 2991def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd), 2992 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 2993 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>, 2994 RegConstraint<"$false = $Rd">; 2995def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd), 2996 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 2997 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>, 2998 RegConstraint<"$false = $Rd">; 2999def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd), 3000 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 3001 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>, 3002 RegConstraint<"$false = $Rd">; 3003def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd), 3004 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 3005 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>, 3006 RegConstraint<"$false = $Rd">; 3007} // isCodeGenOnly = 1 3008 3009multiclass T2I_bincc_irs<Instruction iri, Instruction irr, Instruction irs, 3010 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> { 3011 // shifted imm 3012 def ri : t2PseudoExpand<(outs rGPR:$Rd), 3013 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s), 3014 4, iii, [], 3015 (iri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>, 3016 RegConstraint<"$Rn = $Rd">; 3017 // register 3018 def rr : t2PseudoExpand<(outs rGPR:$Rd), 3019 (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s), 3020 4, iir, [], 3021 (irr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>, 3022 RegConstraint<"$Rn = $Rd">; 3023 // shifted register 3024 def rs : t2PseudoExpand<(outs rGPR:$Rd), 3025 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s), 3026 4, iis, [], 3027 (irs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>, 3028 RegConstraint<"$Rn = $Rd">; 3029} // T2I_bincc_irs 3030 3031defm t2ANDCC : T2I_bincc_irs<t2ANDri, t2ANDrr, t2ANDrs, 3032 IIC_iBITi, IIC_iBITr, IIC_iBITsi>; 3033defm t2ORRCC : T2I_bincc_irs<t2ORRri, t2ORRrr, t2ORRrs, 3034 IIC_iBITi, IIC_iBITr, IIC_iBITsi>; 3035defm t2EORCC : T2I_bincc_irs<t2EORri, t2EORrr, t2EORrs, 3036 IIC_iBITi, IIC_iBITr, IIC_iBITsi>; 3037} // neverHasSideEffects 3038 3039//===----------------------------------------------------------------------===// 3040// Atomic operations intrinsics 3041// 3042 3043// memory barriers protect the atomic sequences 3044let hasSideEffects = 1 in { 3045def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, 3046 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>, 3047 Requires<[IsThumb, HasDB]> { 3048 bits<4> opt; 3049 let Inst{31-4} = 0xf3bf8f5; 3050 let Inst{3-0} = opt; 3051} 3052} 3053 3054def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, 3055 "dsb", "\t$opt", []>, 3056 Requires<[IsThumb, HasDB]> { 3057 bits<4> opt; 3058 let Inst{31-4} = 0xf3bf8f4; 3059 let Inst{3-0} = opt; 3060} 3061 3062def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, 3063 "isb", "\t$opt", 3064 []>, Requires<[IsThumb, HasDB]> { 3065 bits<4> opt; 3066 let Inst{31-4} = 0xf3bf8f6; 3067 let Inst{3-0} = opt; 3068} 3069 3070class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz, 3071 InstrItinClass itin, string opc, string asm, string cstr, 3072 list<dag> pattern, bits<4> rt2 = 0b1111> 3073 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 3074 let Inst{31-27} = 0b11101; 3075 let Inst{26-20} = 0b0001101; 3076 let Inst{11-8} = rt2; 3077 let Inst{7-6} = 0b01; 3078 let Inst{5-4} = opcod; 3079 let Inst{3-0} = 0b1111; 3080 3081 bits<4> addr; 3082 bits<4> Rt; 3083 let Inst{19-16} = addr; 3084 let Inst{15-12} = Rt; 3085} 3086class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz, 3087 InstrItinClass itin, string opc, string asm, string cstr, 3088 list<dag> pattern, bits<4> rt2 = 0b1111> 3089 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 3090 let Inst{31-27} = 0b11101; 3091 let Inst{26-20} = 0b0001100; 3092 let Inst{11-8} = rt2; 3093 let Inst{7-6} = 0b01; 3094 let Inst{5-4} = opcod; 3095 3096 bits<4> Rd; 3097 bits<4> addr; 3098 bits<4> Rt; 3099 let Inst{3-0} = Rd; 3100 let Inst{19-16} = addr; 3101 let Inst{15-12} = Rt; 3102} 3103 3104let mayLoad = 1 in { 3105def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3106 AddrModeNone, 4, NoItinerary, 3107 "ldrexb", "\t$Rt, $addr", "", []>; 3108def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3109 AddrModeNone, 4, NoItinerary, 3110 "ldrexh", "\t$Rt, $addr", "", []>; 3111def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr), 3112 AddrModeNone, 4, NoItinerary, 3113 "ldrex", "\t$Rt, $addr", "", []> { 3114 bits<4> Rt; 3115 bits<12> addr; 3116 let Inst{31-27} = 0b11101; 3117 let Inst{26-20} = 0b0000101; 3118 let Inst{19-16} = addr{11-8}; 3119 let Inst{15-12} = Rt; 3120 let Inst{11-8} = 0b1111; 3121 let Inst{7-0} = addr{7-0}; 3122} 3123let hasExtraDefRegAllocReq = 1 in 3124def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), 3125 (ins addr_offset_none:$addr), 3126 AddrModeNone, 4, NoItinerary, 3127 "ldrexd", "\t$Rt, $Rt2, $addr", "", 3128 [], {?, ?, ?, ?}> { 3129 bits<4> Rt2; 3130 let Inst{11-8} = Rt2; 3131} 3132} 3133 3134let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 3135def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), 3136 (ins rGPR:$Rt, addr_offset_none:$addr), 3137 AddrModeNone, 4, NoItinerary, 3138 "strexb", "\t$Rd, $Rt, $addr", "", []>; 3139def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), 3140 (ins rGPR:$Rt, addr_offset_none:$addr), 3141 AddrModeNone, 4, NoItinerary, 3142 "strexh", "\t$Rd, $Rt, $addr", "", []>; 3143def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, 3144 t2addrmode_imm0_1020s4:$addr), 3145 AddrModeNone, 4, NoItinerary, 3146 "strex", "\t$Rd, $Rt, $addr", "", 3147 []> { 3148 bits<4> Rd; 3149 bits<4> Rt; 3150 bits<12> addr; 3151 let Inst{31-27} = 0b11101; 3152 let Inst{26-20} = 0b0000100; 3153 let Inst{19-16} = addr{11-8}; 3154 let Inst{15-12} = Rt; 3155 let Inst{11-8} = Rd; 3156 let Inst{7-0} = addr{7-0}; 3157} 3158let hasExtraSrcRegAllocReq = 1 in 3159def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd), 3160 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr), 3161 AddrModeNone, 4, NoItinerary, 3162 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], 3163 {?, ?, ?, ?}> { 3164 bits<4> Rt2; 3165 let Inst{11-8} = Rt2; 3166} 3167} 3168 3169def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>, 3170 Requires<[IsThumb2, HasV7]> { 3171 let Inst{31-16} = 0xf3bf; 3172 let Inst{15-14} = 0b10; 3173 let Inst{13} = 0; 3174 let Inst{12} = 0; 3175 let Inst{11-8} = 0b1111; 3176 let Inst{7-4} = 0b0010; 3177 let Inst{3-0} = 0b1111; 3178} 3179 3180//===----------------------------------------------------------------------===// 3181// SJLJ Exception handling intrinsics 3182// eh_sjlj_setjmp() is an instruction sequence to store the return 3183// address and save #0 in R0 for the non-longjmp case. 3184// Since by its nature we may be coming from some other function to get 3185// here, and we're using the stack frame for the containing function to 3186// save/restore registers, we can't keep anything live in regs across 3187// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 3188// when we get here from a longjmp(). We force everything out of registers 3189// except for our own input by listing the relevant registers in Defs. By 3190// doing so, we also cause the prologue/epilogue code to actively preserve 3191// all of the callee-saved resgisters, which is exactly what we want. 3192// $val is a scratch register for our use. 3193let Defs = 3194 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 3195 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15], 3196 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 3197 usesCustomInserter = 1 in { 3198 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 3199 AddrModeNone, 0, NoItinerary, "", "", 3200 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 3201 Requires<[IsThumb2, HasVFP2]>; 3202} 3203 3204let Defs = 3205 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 3206 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 3207 usesCustomInserter = 1 in { 3208 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 3209 AddrModeNone, 0, NoItinerary, "", "", 3210 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 3211 Requires<[IsThumb2, NoVFP]>; 3212} 3213 3214 3215//===----------------------------------------------------------------------===// 3216// Control-Flow Instructions 3217// 3218 3219// FIXME: remove when we have a way to marking a MI with these properties. 3220// FIXME: Should pc be an implicit operand like PICADD, etc? 3221let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3222 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3223def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3224 reglist:$regs, variable_ops), 3225 4, IIC_iLoad_mBr, [], 3226 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3227 RegConstraint<"$Rn = $wb">; 3228 3229let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 3230let isPredicable = 1 in 3231def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br, 3232 "b", ".w\t$target", 3233 [(br bb:$target)]> { 3234 let Inst{31-27} = 0b11110; 3235 let Inst{15-14} = 0b10; 3236 let Inst{12} = 1; 3237 3238 bits<20> target; 3239 let Inst{26} = target{19}; 3240 let Inst{11} = target{18}; 3241 let Inst{13} = target{17}; 3242 let Inst{21-16} = target{16-11}; 3243 let Inst{10-0} = target{10-0}; 3244 let DecoderMethod = "DecodeT2BInstruction"; 3245} 3246 3247let isNotDuplicable = 1, isIndirectBranch = 1 in { 3248def t2BR_JT : t2PseudoInst<(outs), 3249 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id), 3250 0, IIC_Br, 3251 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>; 3252 3253// FIXME: Add a non-pc based case that can be predicated. 3254def t2TBB_JT : t2PseudoInst<(outs), 3255 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>; 3256 3257def t2TBH_JT : t2PseudoInst<(outs), 3258 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>; 3259 3260def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br, 3261 "tbb", "\t$addr", []> { 3262 bits<4> Rn; 3263 bits<4> Rm; 3264 let Inst{31-20} = 0b111010001101; 3265 let Inst{19-16} = Rn; 3266 let Inst{15-5} = 0b11110000000; 3267 let Inst{4} = 0; // B form 3268 let Inst{3-0} = Rm; 3269 3270 let DecoderMethod = "DecodeThumbTableBranch"; 3271} 3272 3273def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br, 3274 "tbh", "\t$addr", []> { 3275 bits<4> Rn; 3276 bits<4> Rm; 3277 let Inst{31-20} = 0b111010001101; 3278 let Inst{19-16} = Rn; 3279 let Inst{15-5} = 0b11110000000; 3280 let Inst{4} = 1; // H form 3281 let Inst{3-0} = Rm; 3282 3283 let DecoderMethod = "DecodeThumbTableBranch"; 3284} 3285} // isNotDuplicable, isIndirectBranch 3286 3287} // isBranch, isTerminator, isBarrier 3288 3289// FIXME: should be able to write a pattern for ARMBrcond, but can't use 3290// a two-value operand where a dag node expects ", "two operands. :( 3291let isBranch = 1, isTerminator = 1 in 3292def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 3293 "b", ".w\t$target", 3294 [/*(ARMbrcond bb:$target, imm:$cc)*/]> { 3295 let Inst{31-27} = 0b11110; 3296 let Inst{15-14} = 0b10; 3297 let Inst{12} = 0; 3298 3299 bits<4> p; 3300 let Inst{25-22} = p; 3301 3302 bits<21> target; 3303 let Inst{26} = target{20}; 3304 let Inst{11} = target{19}; 3305 let Inst{13} = target{18}; 3306 let Inst{21-16} = target{17-12}; 3307 let Inst{10-0} = target{11-1}; 3308 3309 let DecoderMethod = "DecodeThumb2BCCInstruction"; 3310} 3311 3312// Tail calls. The IOS version of thumb tail calls uses a t2 branch, so 3313// it goes here. 3314let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 3315 // IOS version. 3316 let Uses = [SP] in 3317 def tTAILJMPd: tPseudoExpand<(outs), 3318 (ins uncondbrtarget:$dst, pred:$p, variable_ops), 3319 4, IIC_Br, [], 3320 (t2B uncondbrtarget:$dst, pred:$p)>, 3321 Requires<[IsThumb2, IsIOS]>; 3322} 3323 3324let isCall = 1, Defs = [LR], Uses = [SP] in { 3325 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 3326 // return stack predictor. 3327 def t2BMOVPCB_CALL : tPseudoInst<(outs), 3328 (ins t_bltarget:$func, variable_ops), 3329 6, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 3330 Requires<[IsThumb]>; 3331} 3332 3333// Direct calls 3334def : T2Pat<(ARMcall_nolink texternalsym:$func), 3335 (t2BMOVPCB_CALL texternalsym:$func)>, 3336 Requires<[IsThumb]>; 3337 3338// IT block 3339let Defs = [ITSTATE] in 3340def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 3341 AddrModeNone, 2, IIC_iALUx, 3342 "it$mask\t$cc", "", []> { 3343 // 16-bit instruction. 3344 let Inst{31-16} = 0x0000; 3345 let Inst{15-8} = 0b10111111; 3346 3347 bits<4> cc; 3348 bits<4> mask; 3349 let Inst{7-4} = cc; 3350 let Inst{3-0} = mask; 3351 3352 let DecoderMethod = "DecodeIT"; 3353} 3354 3355// Branch and Exchange Jazelle -- for disassembly only 3356// Rm = Inst{19-16} 3357def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> { 3358 bits<4> func; 3359 let Inst{31-27} = 0b11110; 3360 let Inst{26} = 0; 3361 let Inst{25-20} = 0b111100; 3362 let Inst{19-16} = func; 3363 let Inst{15-0} = 0b1000111100000000; 3364} 3365 3366// Compare and branch on zero / non-zero 3367let isBranch = 1, isTerminator = 1 in { 3368 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br, 3369 "cbz\t$Rn, $target", []>, 3370 T1Misc<{0,0,?,1,?,?,?}>, 3371 Requires<[IsThumb2]> { 3372 // A8.6.27 3373 bits<6> target; 3374 bits<3> Rn; 3375 let Inst{9} = target{5}; 3376 let Inst{7-3} = target{4-0}; 3377 let Inst{2-0} = Rn; 3378 } 3379 3380 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br, 3381 "cbnz\t$Rn, $target", []>, 3382 T1Misc<{1,0,?,1,?,?,?}>, 3383 Requires<[IsThumb2]> { 3384 // A8.6.27 3385 bits<6> target; 3386 bits<3> Rn; 3387 let Inst{9} = target{5}; 3388 let Inst{7-3} = target{4-0}; 3389 let Inst{2-0} = Rn; 3390 } 3391} 3392 3393 3394// Change Processor State is a system instruction. 3395// FIXME: Since the asm parser has currently no clean way to handle optional 3396// operands, create 3 versions of the same instruction. Once there's a clean 3397// framework to represent optional operands, change this behavior. 3398class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary, 3399 !strconcat("cps", asm_op), []> { 3400 bits<2> imod; 3401 bits<3> iflags; 3402 bits<5> mode; 3403 bit M; 3404 3405 let Inst{31-27} = 0b11110; 3406 let Inst{26} = 0; 3407 let Inst{25-20} = 0b111010; 3408 let Inst{19-16} = 0b1111; 3409 let Inst{15-14} = 0b10; 3410 let Inst{12} = 0; 3411 let Inst{10-9} = imod; 3412 let Inst{8} = M; 3413 let Inst{7-5} = iflags; 3414 let Inst{4-0} = mode; 3415 let DecoderMethod = "DecodeT2CPSInstruction"; 3416} 3417 3418let M = 1 in 3419 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 3420 "$imod.w\t$iflags, $mode">; 3421let mode = 0, M = 0 in 3422 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags), 3423 "$imod.w\t$iflags">; 3424let imod = 0, iflags = 0, M = 1 in 3425 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">; 3426 3427// A6.3.4 Branches and miscellaneous control 3428// Table A6-14 Change Processor State, and hint instructions 3429class T2I_hint<bits<8> op7_0, string opc, string asm> 3430 : T2I<(outs), (ins), NoItinerary, opc, asm, []> { 3431 let Inst{31-20} = 0xf3a; 3432 let Inst{19-16} = 0b1111; 3433 let Inst{15-14} = 0b10; 3434 let Inst{12} = 0; 3435 let Inst{10-8} = 0b000; 3436 let Inst{7-0} = op7_0; 3437} 3438 3439def t2NOP : T2I_hint<0b00000000, "nop", ".w">; 3440def t2YIELD : T2I_hint<0b00000001, "yield", ".w">; 3441def t2WFE : T2I_hint<0b00000010, "wfe", ".w">; 3442def t2WFI : T2I_hint<0b00000011, "wfi", ".w">; 3443def t2SEV : T2I_hint<0b00000100, "sev", ".w">; 3444 3445def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> { 3446 bits<4> opt; 3447 let Inst{31-20} = 0b111100111010; 3448 let Inst{19-16} = 0b1111; 3449 let Inst{15-8} = 0b10000000; 3450 let Inst{7-4} = 0b1111; 3451 let Inst{3-0} = opt; 3452} 3453 3454// Secure Monitor Call is a system instruction. 3455// Option = Inst{19-16} 3456def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> { 3457 let Inst{31-27} = 0b11110; 3458 let Inst{26-20} = 0b1111111; 3459 let Inst{15-12} = 0b1000; 3460 3461 bits<4> opt; 3462 let Inst{19-16} = opt; 3463} 3464 3465class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin, 3466 string opc, string asm, list<dag> pattern> 3467 : T2I<oops, iops, itin, opc, asm, pattern> { 3468 bits<5> mode; 3469 let Inst{31-25} = 0b1110100; 3470 let Inst{24-23} = Op; 3471 let Inst{22} = 0; 3472 let Inst{21} = W; 3473 let Inst{20-16} = 0b01101; 3474 let Inst{15-5} = 0b11000000000; 3475 let Inst{4-0} = mode{4-0}; 3476} 3477 3478// Store Return State is a system instruction. 3479def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary, 3480 "srsdb", "\tsp!, $mode", []>; 3481def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary, 3482 "srsdb","\tsp, $mode", []>; 3483def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary, 3484 "srsia","\tsp!, $mode", []>; 3485def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary, 3486 "srsia","\tsp, $mode", []>; 3487 3488// Return From Exception is a system instruction. 3489class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin, 3490 string opc, string asm, list<dag> pattern> 3491 : T2I<oops, iops, itin, opc, asm, pattern> { 3492 let Inst{31-20} = op31_20{11-0}; 3493 3494 bits<4> Rn; 3495 let Inst{19-16} = Rn; 3496 let Inst{15-0} = 0xc000; 3497} 3498 3499def t2RFEDBW : T2RFE<0b111010000011, 3500 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!", 3501 [/* For disassembly only; pattern left blank */]>; 3502def t2RFEDB : T2RFE<0b111010000001, 3503 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn", 3504 [/* For disassembly only; pattern left blank */]>; 3505def t2RFEIAW : T2RFE<0b111010011011, 3506 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!", 3507 [/* For disassembly only; pattern left blank */]>; 3508def t2RFEIA : T2RFE<0b111010011001, 3509 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn", 3510 [/* For disassembly only; pattern left blank */]>; 3511 3512//===----------------------------------------------------------------------===// 3513// Non-Instruction Patterns 3514// 3515 3516// 32-bit immediate using movw + movt. 3517// This is a single pseudo instruction to make it re-materializable. 3518// FIXME: Remove this when we can do generalized remat. 3519let isReMaterializable = 1, isMoveImm = 1 in 3520def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 3521 [(set rGPR:$dst, (i32 imm:$src))]>, 3522 Requires<[IsThumb, HasV6T2]>; 3523 3524// Pseudo instruction that combines movw + movt + add pc (if pic). 3525// It also makes it possible to rematerialize the instructions. 3526// FIXME: Remove this when we can do generalized remat and when machine licm 3527// can properly the instructions. 3528let isReMaterializable = 1 in { 3529def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr), 3530 IIC_iMOVix2addpc, 3531 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 3532 Requires<[IsThumb2, UseMovt]>; 3533 3534def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr), 3535 IIC_iMOVix2, 3536 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>, 3537 Requires<[IsThumb2, UseMovt]>; 3538} 3539 3540// ConstantPool, GlobalAddress, and JumpTable 3541def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>, 3542 Requires<[IsThumb2, DontUseMovt]>; 3543def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 3544def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>, 3545 Requires<[IsThumb2, UseMovt]>; 3546 3547def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 3548 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 3549 3550// Pseudo instruction that combines ldr from constpool and add pc. This should 3551// be expanded into two instructions late to allow if-conversion and 3552// scheduling. 3553let canFoldAsLoad = 1, isReMaterializable = 1 in 3554def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp), 3555 IIC_iLoadiALU, 3556 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 3557 imm:$cp))]>, 3558 Requires<[IsThumb2]>; 3559 3560// Pseudo isntruction that combines movs + predicated rsbmi 3561// to implement integer ABS 3562let usesCustomInserter = 1, Defs = [CPSR] in { 3563def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src), 3564 NoItinerary, []>, Requires<[IsThumb2]>; 3565} 3566 3567//===----------------------------------------------------------------------===// 3568// Coprocessor load/store -- for disassembly only 3569// 3570class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm> 3571 : T2I<oops, iops, NoItinerary, opc, asm, []> { 3572 let Inst{31-28} = op31_28; 3573 let Inst{27-25} = 0b110; 3574} 3575 3576multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> { 3577 def _OFFSET : T2CI<op31_28, 3578 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 3579 asm, "\t$cop, $CRd, $addr"> { 3580 bits<13> addr; 3581 bits<4> cop; 3582 bits<4> CRd; 3583 let Inst{24} = 1; // P = 1 3584 let Inst{23} = addr{8}; 3585 let Inst{22} = Dbit; 3586 let Inst{21} = 0; // W = 0 3587 let Inst{20} = load; 3588 let Inst{19-16} = addr{12-9}; 3589 let Inst{15-12} = CRd; 3590 let Inst{11-8} = cop; 3591 let Inst{7-0} = addr{7-0}; 3592 let DecoderMethod = "DecodeCopMemInstruction"; 3593 } 3594 def _PRE : T2CI<op31_28, 3595 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 3596 asm, "\t$cop, $CRd, $addr!"> { 3597 bits<13> addr; 3598 bits<4> cop; 3599 bits<4> CRd; 3600 let Inst{24} = 1; // P = 1 3601 let Inst{23} = addr{8}; 3602 let Inst{22} = Dbit; 3603 let Inst{21} = 1; // W = 1 3604 let Inst{20} = load; 3605 let Inst{19-16} = addr{12-9}; 3606 let Inst{15-12} = CRd; 3607 let Inst{11-8} = cop; 3608 let Inst{7-0} = addr{7-0}; 3609 let DecoderMethod = "DecodeCopMemInstruction"; 3610 } 3611 def _POST: T2CI<op31_28, 3612 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 3613 postidx_imm8s4:$offset), 3614 asm, "\t$cop, $CRd, $addr, $offset"> { 3615 bits<9> offset; 3616 bits<4> addr; 3617 bits<4> cop; 3618 bits<4> CRd; 3619 let Inst{24} = 0; // P = 0 3620 let Inst{23} = offset{8}; 3621 let Inst{22} = Dbit; 3622 let Inst{21} = 1; // W = 1 3623 let Inst{20} = load; 3624 let Inst{19-16} = addr; 3625 let Inst{15-12} = CRd; 3626 let Inst{11-8} = cop; 3627 let Inst{7-0} = offset{7-0}; 3628 let DecoderMethod = "DecodeCopMemInstruction"; 3629 } 3630 def _OPTION : T2CI<op31_28, (outs), 3631 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 3632 coproc_option_imm:$option), 3633 asm, "\t$cop, $CRd, $addr, $option"> { 3634 bits<8> option; 3635 bits<4> addr; 3636 bits<4> cop; 3637 bits<4> CRd; 3638 let Inst{24} = 0; // P = 0 3639 let Inst{23} = 1; // U = 1 3640 let Inst{22} = Dbit; 3641 let Inst{21} = 0; // W = 0 3642 let Inst{20} = load; 3643 let Inst{19-16} = addr; 3644 let Inst{15-12} = CRd; 3645 let Inst{11-8} = cop; 3646 let Inst{7-0} = option; 3647 let DecoderMethod = "DecodeCopMemInstruction"; 3648 } 3649} 3650 3651defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">; 3652defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">; 3653defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">; 3654defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">; 3655defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">; 3656defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">; 3657defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">; 3658defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">; 3659 3660 3661//===----------------------------------------------------------------------===// 3662// Move between special register and ARM core register -- for disassembly only 3663// 3664// Move to ARM core register from Special Register 3665 3666// A/R class MRS. 3667// 3668// A/R class can only move from CPSR or SPSR. 3669def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", 3670 []>, Requires<[IsThumb2,IsARClass]> { 3671 bits<4> Rd; 3672 let Inst{31-12} = 0b11110011111011111000; 3673 let Inst{11-8} = Rd; 3674 let Inst{7-0} = 0b0000; 3675} 3676 3677def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>; 3678 3679def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", 3680 []>, Requires<[IsThumb2,IsARClass]> { 3681 bits<4> Rd; 3682 let Inst{31-12} = 0b11110011111111111000; 3683 let Inst{11-8} = Rd; 3684 let Inst{7-0} = 0b0000; 3685} 3686 3687// M class MRS. 3688// 3689// This MRS has a mask field in bits 7-0 and can take more values than 3690// the A/R class (a full msr_mask). 3691def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary, 3692 "mrs", "\t$Rd, $mask", []>, 3693 Requires<[IsThumb,IsMClass]> { 3694 bits<4> Rd; 3695 bits<8> mask; 3696 let Inst{31-12} = 0b11110011111011111000; 3697 let Inst{11-8} = Rd; 3698 let Inst{19-16} = 0b1111; 3699 let Inst{7-0} = mask; 3700} 3701 3702 3703// Move from ARM core register to Special Register 3704// 3705// A/R class MSR. 3706// 3707// No need to have both system and application versions, the encodings are the 3708// same and the assembly parser has no way to distinguish between them. The mask 3709// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 3710// the mask with the fields to be accessed in the special register. 3711def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn), 3712 NoItinerary, "msr", "\t$mask, $Rn", []>, 3713 Requires<[IsThumb2,IsARClass]> { 3714 bits<5> mask; 3715 bits<4> Rn; 3716 let Inst{31-21} = 0b11110011100; 3717 let Inst{20} = mask{4}; // R Bit 3718 let Inst{19-16} = Rn; 3719 let Inst{15-12} = 0b1000; 3720 let Inst{11-8} = mask{3-0}; 3721 let Inst{7-0} = 0; 3722} 3723 3724// M class MSR. 3725// 3726// Move from ARM core register to Special Register 3727def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn), 3728 NoItinerary, "msr", "\t$SYSm, $Rn", []>, 3729 Requires<[IsThumb,IsMClass]> { 3730 bits<12> SYSm; 3731 bits<4> Rn; 3732 let Inst{31-21} = 0b11110011100; 3733 let Inst{20} = 0b0; 3734 let Inst{19-16} = Rn; 3735 let Inst{15-12} = 0b1000; 3736 let Inst{11-0} = SYSm; 3737} 3738 3739 3740//===----------------------------------------------------------------------===// 3741// Move between coprocessor and ARM core register 3742// 3743 3744class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops, 3745 list<dag> pattern> 3746 : T2Cop<Op, oops, iops, 3747 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), 3748 pattern> { 3749 let Inst{27-24} = 0b1110; 3750 let Inst{20} = direction; 3751 let Inst{4} = 1; 3752 3753 bits<4> Rt; 3754 bits<4> cop; 3755 bits<3> opc1; 3756 bits<3> opc2; 3757 bits<4> CRm; 3758 bits<4> CRn; 3759 3760 let Inst{15-12} = Rt; 3761 let Inst{11-8} = cop; 3762 let Inst{23-21} = opc1; 3763 let Inst{7-5} = opc2; 3764 let Inst{3-0} = CRm; 3765 let Inst{19-16} = CRn; 3766} 3767 3768class t2MovRRCopro<bits<4> Op, string opc, bit direction, 3769 list<dag> pattern = []> 3770 : T2Cop<Op, (outs), 3771 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), 3772 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> { 3773 let Inst{27-24} = 0b1100; 3774 let Inst{23-21} = 0b010; 3775 let Inst{20} = direction; 3776 3777 bits<4> Rt; 3778 bits<4> Rt2; 3779 bits<4> cop; 3780 bits<4> opc1; 3781 bits<4> CRm; 3782 3783 let Inst{15-12} = Rt; 3784 let Inst{19-16} = Rt2; 3785 let Inst{11-8} = cop; 3786 let Inst{7-4} = opc1; 3787 let Inst{3-0} = CRm; 3788} 3789 3790/* from ARM core register to coprocessor */ 3791def t2MCR : t2MovRCopro<0b1110, "mcr", 0, 3792 (outs), 3793 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 3794 c_imm:$CRm, imm0_7:$opc2), 3795 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 3796 imm:$CRm, imm:$opc2)]>; 3797def : t2InstAlias<"mcr $cop, $opc1, $Rt, $CRn, $CRm", 3798 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 3799 c_imm:$CRm, 0)>; 3800def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0, 3801 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 3802 c_imm:$CRm, imm0_7:$opc2), 3803 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 3804 imm:$CRm, imm:$opc2)]>; 3805def : t2InstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 3806 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 3807 c_imm:$CRm, 0)>; 3808 3809/* from coprocessor to ARM core register */ 3810def t2MRC : t2MovRCopro<0b1110, "mrc", 1, 3811 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 3812 c_imm:$CRm, imm0_7:$opc2), []>; 3813def : t2InstAlias<"mrc $cop, $opc1, $Rt, $CRn, $CRm", 3814 (t2MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 3815 c_imm:$CRm, 0)>; 3816 3817def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1, 3818 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 3819 c_imm:$CRm, imm0_7:$opc2), []>; 3820def : t2InstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 3821 (t2MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 3822 c_imm:$CRm, 0)>; 3823 3824def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 3825 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 3826 3827def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 3828 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 3829 3830 3831/* from ARM core register to coprocessor */ 3832def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, 3833 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, 3834 imm:$CRm)]>; 3835def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, 3836 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, 3837 GPR:$Rt2, imm:$CRm)]>; 3838/* from coprocessor to ARM core register */ 3839def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>; 3840 3841def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>; 3842 3843//===----------------------------------------------------------------------===// 3844// Other Coprocessor Instructions. 3845// 3846 3847def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 3848 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 3849 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 3850 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 3851 imm:$CRm, imm:$opc2)]> { 3852 let Inst{27-24} = 0b1110; 3853 3854 bits<4> opc1; 3855 bits<4> CRn; 3856 bits<4> CRd; 3857 bits<4> cop; 3858 bits<3> opc2; 3859 bits<4> CRm; 3860 3861 let Inst{3-0} = CRm; 3862 let Inst{4} = 0; 3863 let Inst{7-5} = opc2; 3864 let Inst{11-8} = cop; 3865 let Inst{15-12} = CRd; 3866 let Inst{19-16} = CRn; 3867 let Inst{23-20} = opc1; 3868} 3869 3870def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1, 3871 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 3872 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 3873 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 3874 imm:$CRm, imm:$opc2)]> { 3875 let Inst{27-24} = 0b1110; 3876 3877 bits<4> opc1; 3878 bits<4> CRn; 3879 bits<4> CRd; 3880 bits<4> cop; 3881 bits<3> opc2; 3882 bits<4> CRm; 3883 3884 let Inst{3-0} = CRm; 3885 let Inst{4} = 0; 3886 let Inst{7-5} = opc2; 3887 let Inst{11-8} = cop; 3888 let Inst{15-12} = CRd; 3889 let Inst{19-16} = CRn; 3890 let Inst{23-20} = opc1; 3891} 3892 3893 3894 3895//===----------------------------------------------------------------------===// 3896// Non-Instruction Patterns 3897// 3898 3899// SXT/UXT with no rotate 3900let AddedComplexity = 16 in { 3901def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>, 3902 Requires<[IsThumb2]>; 3903def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>, 3904 Requires<[IsThumb2]>; 3905def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>, 3906 Requires<[HasT2ExtractPack, IsThumb2]>; 3907def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)), 3908 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 3909 Requires<[HasT2ExtractPack, IsThumb2]>; 3910def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)), 3911 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 3912 Requires<[HasT2ExtractPack, IsThumb2]>; 3913} 3914 3915def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>, 3916 Requires<[IsThumb2]>; 3917def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>, 3918 Requires<[IsThumb2]>; 3919def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)), 3920 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 3921 Requires<[HasT2ExtractPack, IsThumb2]>; 3922def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)), 3923 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 3924 Requires<[HasT2ExtractPack, IsThumb2]>; 3925 3926// Atomic load/store patterns 3927def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr), 3928 (t2LDRBi12 t2addrmode_imm12:$addr)>; 3929def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr), 3930 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 3931def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr), 3932 (t2LDRBs t2addrmode_so_reg:$addr)>; 3933def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr), 3934 (t2LDRHi12 t2addrmode_imm12:$addr)>; 3935def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr), 3936 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 3937def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr), 3938 (t2LDRHs t2addrmode_so_reg:$addr)>; 3939def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr), 3940 (t2LDRi12 t2addrmode_imm12:$addr)>; 3941def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr), 3942 (t2LDRi8 t2addrmode_negimm8:$addr)>; 3943def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr), 3944 (t2LDRs t2addrmode_so_reg:$addr)>; 3945def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val), 3946 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>; 3947def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val), 3948 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>; 3949def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val), 3950 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>; 3951def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val), 3952 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>; 3953def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val), 3954 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>; 3955def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val), 3956 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>; 3957def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val), 3958 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>; 3959def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val), 3960 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>; 3961def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val), 3962 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>; 3963 3964 3965//===----------------------------------------------------------------------===// 3966// Assembler aliases 3967// 3968 3969// Aliases for ADC without the ".w" optional width specifier. 3970def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm", 3971 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 3972def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm", 3973 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 3974 pred:$p, cc_out:$s)>; 3975 3976// Aliases for SBC without the ".w" optional width specifier. 3977def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm", 3978 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 3979def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm", 3980 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 3981 pred:$p, cc_out:$s)>; 3982 3983// Aliases for ADD without the ".w" optional width specifier. 3984def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm", 3985 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 3986def : t2InstAlias<"add${p} $Rd, $Rn, $imm", 3987 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>; 3988def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm", 3989 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 3990def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm", 3991 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, 3992 pred:$p, cc_out:$s)>; 3993// ... and with the destination and source register combined. 3994def : t2InstAlias<"add${s}${p} $Rdn, $imm", 3995 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 3996def : t2InstAlias<"add${p} $Rdn, $imm", 3997 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>; 3998def : t2InstAlias<"add${s}${p} $Rdn, $Rm", 3999 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4000def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm", 4001 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, 4002 pred:$p, cc_out:$s)>; 4003 4004// add w/ negative immediates is just a sub. 4005def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm", 4006 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p, 4007 cc_out:$s)>; 4008def : t2InstAlias<"add${p} $Rd, $Rn, $imm", 4009 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>; 4010def : t2InstAlias<"add${s}${p} $Rdn, $imm", 4011 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p, 4012 cc_out:$s)>; 4013def : t2InstAlias<"add${p} $Rdn, $imm", 4014 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>; 4015 4016def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm", 4017 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p, 4018 cc_out:$s)>; 4019def : t2InstAlias<"addw${p} $Rd, $Rn, $imm", 4020 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>; 4021def : t2InstAlias<"add${s}${p}.w $Rdn, $imm", 4022 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p, 4023 cc_out:$s)>; 4024def : t2InstAlias<"addw${p} $Rdn, $imm", 4025 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>; 4026 4027 4028// Aliases for SUB without the ".w" optional width specifier. 4029def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm", 4030 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4031def : t2InstAlias<"sub${p} $Rd, $Rn, $imm", 4032 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>; 4033def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm", 4034 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4035def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm", 4036 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, 4037 pred:$p, cc_out:$s)>; 4038// ... and with the destination and source register combined. 4039def : t2InstAlias<"sub${s}${p} $Rdn, $imm", 4040 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4041def : t2InstAlias<"sub${p} $Rdn, $imm", 4042 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>; 4043def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm", 4044 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4045def : t2InstAlias<"sub${s}${p} $Rdn, $Rm", 4046 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4047def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm", 4048 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, 4049 pred:$p, cc_out:$s)>; 4050 4051// Alias for compares without the ".w" optional width specifier. 4052def : t2InstAlias<"cmn${p} $Rn, $Rm", 4053 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 4054def : t2InstAlias<"teq${p} $Rn, $Rm", 4055 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 4056def : t2InstAlias<"tst${p} $Rn, $Rm", 4057 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 4058 4059// Memory barriers 4060def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb, HasDB]>; 4061def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb, HasDB]>; 4062def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb, HasDB]>; 4063 4064// Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional 4065// width specifier. 4066def : t2InstAlias<"ldr${p} $Rt, $addr", 4067 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4068def : t2InstAlias<"ldrb${p} $Rt, $addr", 4069 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4070def : t2InstAlias<"ldrh${p} $Rt, $addr", 4071 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4072def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4073 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4074def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4075 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4076 4077def : t2InstAlias<"ldr${p} $Rt, $addr", 4078 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4079def : t2InstAlias<"ldrb${p} $Rt, $addr", 4080 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4081def : t2InstAlias<"ldrh${p} $Rt, $addr", 4082 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4083def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4084 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4085def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4086 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4087 4088def : t2InstAlias<"ldr${p} $Rt, $addr", 4089 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4090def : t2InstAlias<"ldrb${p} $Rt, $addr", 4091 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4092def : t2InstAlias<"ldrh${p} $Rt, $addr", 4093 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4094def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4095 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4096def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4097 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4098 4099// Alias for MVN with(out) the ".w" optional width specifier. 4100def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm", 4101 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4102def : t2InstAlias<"mvn${s}${p} $Rd, $Rm", 4103 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>; 4104def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm", 4105 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>; 4106 4107// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the 4108// shift amount is zero (i.e., unspecified). 4109def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 4110 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>, 4111 Requires<[HasT2ExtractPack, IsThumb2]>; 4112def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 4113 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>, 4114 Requires<[HasT2ExtractPack, IsThumb2]>; 4115 4116// PUSH/POP aliases for STM/LDM 4117def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; 4118def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; 4119def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; 4120def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; 4121 4122// STMIA/STMIA_UPD aliases w/o the optional .w suffix 4123def : t2InstAlias<"stm${p} $Rn, $regs", 4124 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; 4125def : t2InstAlias<"stm${p} $Rn!, $regs", 4126 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4127 4128// LDMIA/LDMIA_UPD aliases w/o the optional .w suffix 4129def : t2InstAlias<"ldm${p} $Rn, $regs", 4130 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>; 4131def : t2InstAlias<"ldm${p} $Rn!, $regs", 4132 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4133 4134// STMDB/STMDB_UPD aliases w/ the optional .w suffix 4135def : t2InstAlias<"stmdb${p}.w $Rn, $regs", 4136 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>; 4137def : t2InstAlias<"stmdb${p}.w $Rn!, $regs", 4138 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4139 4140// LDMDB/LDMDB_UPD aliases w/ the optional .w suffix 4141def : t2InstAlias<"ldmdb${p}.w $Rn, $regs", 4142 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>; 4143def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs", 4144 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4145 4146// Alias for REV/REV16/REVSH without the ".w" optional width specifier. 4147def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>; 4148def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>; 4149def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>; 4150 4151 4152// Alias for RSB without the ".w" optional width specifier, and with optional 4153// implied destination register. 4154def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm", 4155 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4156def : t2InstAlias<"rsb${s}${p} $Rdn, $imm", 4157 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4158def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm", 4159 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4160def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm", 4161 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, 4162 cc_out:$s)>; 4163 4164// SSAT/USAT optional shift operand. 4165def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 4166 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>; 4167def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn", 4168 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>; 4169 4170// STM w/o the .w suffix. 4171def : t2InstAlias<"stm${p} $Rn, $regs", 4172 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; 4173 4174// Alias for STR, STRB, and STRH without the ".w" optional 4175// width specifier. 4176def : t2InstAlias<"str${p} $Rt, $addr", 4177 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4178def : t2InstAlias<"strb${p} $Rt, $addr", 4179 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4180def : t2InstAlias<"strh${p} $Rt, $addr", 4181 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4182 4183def : t2InstAlias<"str${p} $Rt, $addr", 4184 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4185def : t2InstAlias<"strb${p} $Rt, $addr", 4186 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4187def : t2InstAlias<"strh${p} $Rt, $addr", 4188 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4189 4190// Extend instruction optional rotate operand. 4191def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm", 4192 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4193def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm", 4194 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4195def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 4196 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4197 4198def : t2InstAlias<"sxtb${p} $Rd, $Rm", 4199 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4200def : t2InstAlias<"sxtb16${p} $Rd, $Rm", 4201 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4202def : t2InstAlias<"sxth${p} $Rd, $Rm", 4203 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4204def : t2InstAlias<"sxtb${p}.w $Rd, $Rm", 4205 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4206def : t2InstAlias<"sxth${p}.w $Rd, $Rm", 4207 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4208 4209def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm", 4210 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4211def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm", 4212 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4213def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 4214 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4215def : t2InstAlias<"uxtb${p} $Rd, $Rm", 4216 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4217def : t2InstAlias<"uxtb16${p} $Rd, $Rm", 4218 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4219def : t2InstAlias<"uxth${p} $Rd, $Rm", 4220 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4221 4222def : t2InstAlias<"uxtb${p}.w $Rd, $Rm", 4223 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4224def : t2InstAlias<"uxth${p}.w $Rd, $Rm", 4225 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4226 4227// Extend instruction w/o the ".w" optional width specifier. 4228def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot", 4229 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4230def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot", 4231 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4232def : t2InstAlias<"uxth${p} $Rd, $Rm$rot", 4233 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4234 4235def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot", 4236 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4237def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot", 4238 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4239def : t2InstAlias<"sxth${p} $Rd, $Rm$rot", 4240 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4241 4242 4243// "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like 4244// for isel. 4245def : t2InstAlias<"mov${p} $Rd, $imm", 4246 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>; 4247def : t2InstAlias<"mvn${p} $Rd, $imm", 4248 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>; 4249// Same for AND <--> BIC 4250def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm", 4251 (t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 4252 pred:$p, cc_out:$s)>; 4253def : t2InstAlias<"bic${s}${p} $Rdn, $imm", 4254 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 4255 pred:$p, cc_out:$s)>; 4256def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm", 4257 (t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 4258 pred:$p, cc_out:$s)>; 4259def : t2InstAlias<"and${s}${p} $Rdn, $imm", 4260 (t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 4261 pred:$p, cc_out:$s)>; 4262// Likewise, "add Rd, t2_so_imm_neg" -> sub 4263def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm", 4264 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, 4265 pred:$p, cc_out:$s)>; 4266def : t2InstAlias<"add${s}${p} $Rd, $imm", 4267 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm, 4268 pred:$p, cc_out:$s)>; 4269// Same for CMP <--> CMN via t2_so_imm_neg 4270def : t2InstAlias<"cmp${p} $Rd, $imm", 4271 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>; 4272def : t2InstAlias<"cmn${p} $Rd, $imm", 4273 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>; 4274 4275 4276// Wide 'mul' encoding can be specified with only two operands. 4277def : t2InstAlias<"mul${p} $Rn, $Rm", 4278 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>; 4279 4280// "neg" is and alias for "rsb rd, rn, #0" 4281def : t2InstAlias<"neg${s}${p} $Rd, $Rm", 4282 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>; 4283 4284// MOV so_reg assembler pseudos. InstAlias isn't expressive enough for 4285// these, unfortunately. 4286def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift", 4287 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 4288def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift", 4289 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 4290 4291def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift", 4292 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 4293def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift", 4294 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 4295 4296// ADR w/o the .w suffix 4297def : t2InstAlias<"adr${p} $Rd, $addr", 4298 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>; 4299 4300// LDR(literal) w/ alternate [pc, #imm] syntax. 4301def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr", 4302 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4303def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr", 4304 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4305def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr", 4306 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4307def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr", 4308 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4309def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr", 4310 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4311 // Version w/ the .w suffix. 4312def : t2InstAlias<"ldr${p}.w $Rt, $addr", 4313 (t2LDRpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4314def : t2InstAlias<"ldrb${p}.w $Rt, $addr", 4315 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4316def : t2InstAlias<"ldrh${p}.w $Rt, $addr", 4317 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4318def : t2InstAlias<"ldrsb${p}.w $Rt, $addr", 4319 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4320def : t2InstAlias<"ldrsh${p}.w $Rt, $addr", 4321 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4322 4323def : t2InstAlias<"add${p} $Rd, pc, $imm", 4324 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>; 4325