ARMInstrVFP.td revision c4e600362e0adec4660c317e0f87e4344e76f139 
1//===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under the
6// University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM VP instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// ARM VFP Instruction templates.
16//
17
18// ARM Float Instruction
19class ASI<dag ops, string asm, list<dag> pattern> : AI<ops, asm, pattern> {
20  // TODO: Mark the instructions with the appropriate subtarget info.
21}
22
23class ASI5<dag ops, string asm, list<dag> pattern>
24  : I<ops, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
25  // TODO: Mark the instructions with the appropriate subtarget info.
26}
27
28// ARM Double Instruction
29class ADI<dag ops, string asm, list<dag> pattern> : AI<ops, asm, pattern> {
30  // TODO: Mark the instructions with the appropriate subtarget info.
31}
32
33class ADI5<dag ops, string asm, list<dag> pattern>
34  : I<ops, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
35  // TODO: Mark the instructions with the appropriate subtarget info.
36}
37
38def SDT_FTOI :
39SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
40def SDT_ITOF :
41SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
42def SDT_CMPFP0 :
43SDTypeProfile<0, 1, [SDTCisFP<0>]>;
44def SDT_FMDRR :
45SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
46                     SDTCisSameAs<1, 2>]>;
47
48def arm_ftoui  : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
49def arm_ftosi  : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
50def arm_sitof  : SDNode<"ARMISD::SITOF", SDT_ITOF>;
51def arm_uitof  : SDNode<"ARMISD::UITOF", SDT_ITOF>;
52def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTRet, [SDNPInFlag,SDNPOutFlag]>;
53def arm_cmpfp  : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
54def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
55def arm_fmdrr  : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
56
57//===----------------------------------------------------------------------===//
58//  Load / store Instructions.
59//
60
61let isLoad = 1 in {
62def FLDD  : ADI5<(ops DPR:$dst, addrmode5:$addr),
63                 "fldd $dst, $addr",
64                 [(set DPR:$dst, (load addrmode5:$addr))]>;
65
66def FLDS  : ASI5<(ops SPR:$dst, addrmode5:$addr),
67                 "flds $dst, $addr",
68                 [(set SPR:$dst, (load addrmode5:$addr))]>;
69} // isLoad
70
71let isStore = 1 in {
72def FSTD  : ADI5<(ops DPR:$src, addrmode5:$addr),
73                 "fstd $src, $addr",
74                 [(store DPR:$src, addrmode5:$addr)]>;
75
76def FSTS  : ASI5<(ops SPR:$src, addrmode5:$addr),
77                 "fsts $src, $addr",
78                 [(store SPR:$src, addrmode5:$addr)]>;
79} // isStore
80
81//===----------------------------------------------------------------------===//
82//  Load / store multiple Instructions.
83//
84
85let isLoad = 1 in {
86def FLDMD : ADI5<(ops addrmode5:$addr, reglist:$dst1, variable_ops),
87                 "fldm${addr:submode}d ${addr:base}, $dst1",
88                 []>;
89
90def FLDMS : ASI5<(ops addrmode5:$addr, reglist:$dst1, variable_ops),
91                 "fldm${addr:submode}s ${addr:base}, $dst1",
92                 []>;
93} // isLoad
94
95let isStore = 1 in {
96def FSTMD : ADI5<(ops addrmode5:$addr, reglist:$src1, variable_ops),
97                 "fstm${addr:submode}d ${addr:base}, $src1",
98                 []>;
99
100def FSTMS : ASI5<(ops addrmode5:$addr, reglist:$src1, variable_ops),
101                 "fstm${addr:submode}s ${addr:base}, $src1",
102                 []>;
103} // isStore
104
105// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
106
107//===----------------------------------------------------------------------===//
108// FP Binary Operations.
109//
110
111def FADDD  : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
112                 "faddd $dst, $a, $b",
113                 [(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
114
115def FADDS  : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
116                 "fadds $dst, $a, $b",
117                 [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
118
119def FCMPED : ADI<(ops DPR:$a, DPR:$b),
120                 "fcmped $a, $b",
121                 [(arm_cmpfp DPR:$a, DPR:$b)]>;
122
123def FCMPES : ASI<(ops SPR:$a, SPR:$b),
124                 "fcmpes $a, $b",
125                 [(arm_cmpfp SPR:$a, SPR:$b)]>;
126
127def FDIVD  : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
128                 "fdivd $dst, $a, $b",
129                 [(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
130
131def FDIVS  : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
132                 "fdivs $dst, $a, $b",
133                 [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
134
135def FMULD  : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
136                 "fmuld $dst, $a, $b",
137                 [(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
138
139def FMULS  : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
140                 "fmuls $dst, $a, $b",
141                 [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
142                 
143def FNMULD  : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
144                  "fnmuld $dst, $a, $b",
145                  [(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]>;
146
147def FNMULS  : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
148                  "fnmuls $dst, $a, $b",
149                  [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>;
150
151// Match reassociated forms only if not sign dependent rounding.
152def : Pat<(fmul (fneg DPR:$a), DPR:$b),
153          (FNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
154def : Pat<(fmul (fneg SPR:$a), SPR:$b),
155          (FNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
156
157
158def FSUBD  : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
159                 "fsubd $dst, $a, $b",
160                 [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>;
161
162def FSUBS  : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
163                 "fsubs $dst, $a, $b",
164                 [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
165
166//===----------------------------------------------------------------------===//
167// FP Unary Operations.
168//
169
170def FABSD  : ADI<(ops DPR:$dst, DPR:$a),
171                 "fabsd $dst, $a",
172                 [(set DPR:$dst, (fabs DPR:$a))]>;
173
174def FABSS  : ASI<(ops SPR:$dst, SPR:$a),
175                 "fabss $dst, $a",
176                 [(set SPR:$dst, (fabs SPR:$a))]>;
177
178def FCMPEZD : ADI<(ops DPR:$a),
179                  "fcmpezd $a",
180                  [(arm_cmpfp0 DPR:$a)]>;
181
182def FCMPEZS : ASI<(ops SPR:$a),
183                  "fcmpezs $a",
184                  [(arm_cmpfp0 SPR:$a)]>;
185
186def FCVTDS : ADI<(ops DPR:$dst, SPR:$a),
187                 "fcvtds $dst, $a",
188                 [(set DPR:$dst, (fextend SPR:$a))]>;
189
190def FCVTSD : ADI<(ops SPR:$dst, DPR:$a),
191                 "fcvtsd $dst, $a",
192                 [(set SPR:$dst, (fround DPR:$a))]>;
193
194def FCPYD  : ADI<(ops DPR:$dst, DPR:$a),
195                 "fcpyd $dst, $a",
196                 [/*(set DPR:$dst, DPR:$a)*/]>;
197
198def FCPYS  : ASI<(ops SPR:$dst, SPR:$a),
199                 "fcpys $dst, $a",
200                 [/*(set SPR:$dst, SPR:$a)*/]>;
201
202def FNEGD  : ADI<(ops DPR:$dst, DPR:$a),
203                 "fnegd $dst, $a",
204                 [(set DPR:$dst, (fneg DPR:$a))]>;
205
206def FNEGS  : ASI<(ops SPR:$dst, SPR:$a),
207                 "fnegs $dst, $a",
208                 [(set SPR:$dst, (fneg SPR:$a))]>;
209
210def FSQRTD  : ADI<(ops DPR:$dst, DPR:$a),
211                 "fsqrtd $dst, $a",
212                 [(set DPR:$dst, (fsqrt DPR:$a))]>;
213
214def FSQRTS  : ASI<(ops SPR:$dst, SPR:$a),
215                 "fsqrts $dst, $a",
216                 [(set SPR:$dst, (fsqrt SPR:$a))]>;
217
218//===----------------------------------------------------------------------===//
219// FP <-> GPR Copies.  Int <-> FP Conversions.
220//
221
222def IMPLICIT_DEF_SPR : PseudoInst<(ops SPR:$rD),
223                                  "@ IMPLICIT_DEF_SPR $rD",
224                                  [(set SPR:$rD, (undef))]>;
225def IMPLICIT_DEF_DPR : PseudoInst<(ops DPR:$rD),
226                                  "@ IMPLICIT_DEF_DPR $rD",
227                                  [(set DPR:$rD, (undef))]>;
228
229def FMRS   : ASI<(ops GPR:$dst, SPR:$src),
230                 "fmrs $dst, $src",
231                 [(set GPR:$dst, (bitconvert SPR:$src))]>;
232
233def FMSR   : ASI<(ops SPR:$dst, GPR:$src),
234                 "fmsr $dst, $src",
235                 [(set SPR:$dst, (bitconvert GPR:$src))]>;
236
237
238def FMRRD  : ADI<(ops GPR:$dst1, GPR:$dst2, DPR:$src),
239                 "fmrrd $dst1, $dst2, $src",
240                 [/* FIXME: Can't write pattern for multiple result instr*/]>;
241
242// FMDHR: GPR -> SPR
243// FMDLR: GPR -> SPR
244
245def FMDRR : ADI<(ops DPR:$dst, GPR:$src1, GPR:$src2),
246                "fmdrr $dst, $src1, $src2",
247                [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
248
249// FMRDH: SPR -> GPR
250// FMRDL: SPR -> GPR
251// FMRRS: SPR -> GPR
252// FMRX : SPR system reg -> GPR
253
254// FMSRR: GPR -> SPR
255
256
257def FMSTAT : ASI<(ops), "fmstat", [(arm_fmstat)]>;
258
259// FMXR: GPR -> VFP Sstem reg
260
261
262// Int to FP:
263
264def FSITOD : ADI<(ops DPR:$dst, SPR:$a),
265                 "fsitod $dst, $a",
266                 [(set DPR:$dst, (arm_sitof SPR:$a))]>;
267
268def FSITOS : ASI<(ops SPR:$dst, SPR:$a),
269                 "fsitos $dst, $a",
270                 [(set SPR:$dst, (arm_sitof SPR:$a))]>;
271
272def FUITOD : ADI<(ops DPR:$dst, SPR:$a),
273                 "fuitod $dst, $a",
274                 [(set DPR:$dst, (arm_uitof SPR:$a))]>;
275
276def FUITOS : ASI<(ops SPR:$dst, SPR:$a),
277                 "fuitos $dst, $a",
278                 [(set SPR:$dst, (arm_uitof SPR:$a))]>;
279
280// FP to Int:
281// Always set Z bit in the instruction, i.e. "round towards zero" variants.
282
283def FTOSIZD : ADI<(ops SPR:$dst, DPR:$a),
284                 "ftosizd $dst, $a",
285                 [(set SPR:$dst, (arm_ftosi DPR:$a))]>;
286
287def FTOSIZS : ASI<(ops SPR:$dst, SPR:$a),
288                 "ftosizs $dst, $a",
289                 [(set SPR:$dst, (arm_ftosi SPR:$a))]>;
290
291def FTOUIZD : ADI<(ops SPR:$dst, DPR:$a),
292                 "ftouizd $dst, $a",
293                 [(set SPR:$dst, (arm_ftoui DPR:$a))]>;
294
295def FTOUIZS : ASI<(ops SPR:$dst, SPR:$a),
296                 "ftouizs $dst, $a",
297                 [(set SPR:$dst, (arm_ftoui SPR:$a))]>;
298
299//===----------------------------------------------------------------------===//
300// FP FMA Operations.
301//
302
303def FMACD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
304                "fmacd $dst, $a, $b",
305                [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
306                RegConstraint<"$dstin = $dst">;
307
308def FMACS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
309                "fmacs $dst, $a, $b",
310                [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
311                RegConstraint<"$dstin = $dst">;
312
313def FMSCD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
314                "fmscd $dst, $a, $b",
315                [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
316                RegConstraint<"$dstin = $dst">;
317
318def FMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
319                "fmscs $dst, $a, $b",
320                [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
321                RegConstraint<"$dstin = $dst">;
322
323def FNMACD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
324                 "fnmacd $dst, $a, $b",
325             [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
326                RegConstraint<"$dstin = $dst">;
327
328def FNMACS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
329                "fnmacs $dst, $a, $b",
330             [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
331                RegConstraint<"$dstin = $dst">;
332
333def FNMSCD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
334                 "fnmscd $dst, $a, $b",
335             [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
336                RegConstraint<"$dstin = $dst">;
337
338def FNMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
339                "fnmscs $dst, $a, $b",
340             [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
341                RegConstraint<"$dstin = $dst">;
342
343//===----------------------------------------------------------------------===//
344// FP Conditional moves.
345//
346
347def FCPYDcc  : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc),
348                   "fcpyd$cc $dst, $true",
349                   [(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))]>,
350                   RegConstraint<"$false = $dst">;
351
352def FCPYScc  : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc),
353                   "fcpys$cc $dst, $true",
354                   [(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))]>,
355                   RegConstraint<"$false = $dst">;
356
357def FNEGDcc  : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc),
358                   "fnegd$cc $dst, $true",
359                   [(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))]>,
360                   RegConstraint<"$false = $dst">;
361
362def FNEGScc  : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc),
363                   "fnegs$cc $dst, $true",
364                   [(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))]>,
365                   RegConstraint<"$false = $dst">;
366