ARMRegisterInfo.cpp revision 0f3ac8d8d4ce23eb2ae6f9d850f389250874eea5
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 167bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineInstrBuilder.h" 187bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFunction.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 207bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/Type.h" 227bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 237bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include <iostream> 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 257bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 267bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaARMRegisterInfo::ARMRegisterInfo() 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) { 287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 297bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 307bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 317bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola // On the order of operands here: think "[FI + 0] = SrcReg". 357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola assert (RC == ARM::IntRegsRegisterClass); 367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola BuildMI(MBB, I, ARM::str, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg); 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 407bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 437bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola assert (RC == ARM::IntRegsRegisterClass); 447bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola BuildMI(MBB, I, ARM::ldr, 2, DestReg).addFrameIndex(FI).addImm(0); 457bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 487bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I, 497bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, unsigned SrcReg, 507bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 517bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola assert (RC == ARM::IntRegsRegisterClass); 527bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola BuildMI(MBB, I, ARM::mov, 1, DestReg).addReg(SrcReg); 537bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 547bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 557bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI, 567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned OpNum, 577bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola int FI) const { 587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola return NULL; 597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 607bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 610f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst unsigned* ARMRegisterInfo::getCalleeSaveRegs() const { 620f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng static const unsigned CalleeSaveRegs[] = { 0 }; 630f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng return CalleeSaveRegs; 640f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 650f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 660f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 670f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan ChengARMRegisterInfo::getCalleeSaveRegClasses() const { 680f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 }; 690f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng return CalleeSaveRegClasses; 700f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 710f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 727bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 737bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 747bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 757bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 767bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 777bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 787bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid 797bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 807bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola assert(0 && "Not Implemented"); 817bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 827bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 837bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 847bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaprocessFunctionBeforeFrameFinalized(MachineFunction &MF) const {} 857bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 867bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 877bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 887bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 897bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 907bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock &MBB) const { 917bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 927bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 937bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 947bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola return ARM::R14; 957bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 967bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 977bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 987bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola return ARM::R13; 997bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1007bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1017bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 1027bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 103