ARMRegisterInfo.cpp revision 13ab020ea08826f1b87db6ec3da63889a12e3d9d
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 285ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng#include "llvm/CodeGen/RegisterScavenging.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 30b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 317ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 32b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 35ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng#include "llvm/Support/CommandLine.h" 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 39e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Chengstatic cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging", 40e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::Hidden, 41e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::desc("Enable register scavenging on Thumb")); 42ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng 43a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 76a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 798fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 80a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 8115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 8215f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 8315f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 84a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 86c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 884c6d20a096ad28aa6f812c07a48268e8a6ccb8feLauro Ramos Venancio FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng} 905ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng 91a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 100ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 101ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng unsigned Reg = CSI[i-1].getReg(); 102ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng // Add the callee-saved register as live-in. It's killed at the spill. 103ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MBB.addLiveIn(Reg); 104ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); 105ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng } 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 109a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1179d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1239d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1249d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1259d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1367bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 143ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true) 144a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 146ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true) 1473b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL) 1483b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addReg(0); 149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 150ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true) 1513b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0); 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 154ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true) 1553b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0); 156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1577bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1607bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1617bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1627bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1678e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 170a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 1713b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL) 1723b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addReg(0); 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 1753b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0); 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 1793b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0); 180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1817bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1827bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1837bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 19044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (AFI->isThumbFunction()) 19144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg); 19244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng else 19344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg).addReg(SrcReg) 19413ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((int64_t)ARMCC::AL).addReg(0).addReg(0); 195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 19644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg) 1973b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm((int64_t)ARMCC::AL).addReg(0); 198a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 19944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg) 2003b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm((int64_t)ARMCC::AL).addReg(0); 201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 2037bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2047bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 205bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize the 206bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// specified immediate. 207bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 208bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator &MBBI, 2093b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned DestReg, int Val, 2103b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 211bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const TargetInstrInfo &TII, bool isThumb) { 212bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineFunction &MF = *MBB.getParent(); 213bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 214bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, Val); 215bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 216bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (isThumb) 217bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx); 218bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng else 219bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx) 2203b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg); 221bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 222bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 223bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengvoid ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 224bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator I, 225bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned DestReg, 226bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const MachineInstr *Orig) const { 227bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (Orig->getOpcode() == ARM::MOVi2pieces) { 22844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitLoadConstPool(MBB, I, DestReg, 22944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng Orig->getOperand(1).getImmedValue(), 2303b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(), 2313b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng Orig->getOperand(3).getReg(), 232bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng TII, false); 233bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng return; 234bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng } 235bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 236bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineInstr *MI = Orig->clone(); 237bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MI->getOperand(0).setReg(DestReg); 238bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MBB.insert(I, MI); 239bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 240bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 24140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 24240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 24340984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 24440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 24540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 24640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 24740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 24840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 24940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 25040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 25140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 25240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 25340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 254a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 2609f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::MOVr: { 26113ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng if (MI->getOperand(4).getReg() == ARM::CPSR) 26213ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng // If it is updating CPSR, then it cannot be foled. 26313ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng break; 26444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 2653b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 2693b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 2733b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 274a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 2779f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::tMOVr: { 278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 280bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 2818e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 28240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2838e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 286a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 287bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 2888e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 28940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2908e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 29644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 2973b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 298a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 299a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 300a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 3013b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 303a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 30444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI) 3053b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 306a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 307a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 308a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 309a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 31044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 3113b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 312a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 313a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 314a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 3153b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 316a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 317a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 31844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI) 3193b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 320a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 321a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 322a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 323a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 324a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 325a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 326a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 327a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 3287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 3297bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 330c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 331c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 332a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 333a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 334a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 335a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 336a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 337a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 338ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 339a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 340a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 341a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 342a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 343a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 344a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 345a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 346a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 347a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 348970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 3490f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3500f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 3510f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 352c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 353c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 354a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 355a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 356a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 357a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 358a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 359a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 360a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 361ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 362c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 3630f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3640f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 365b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 366c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // FIXME: avoid re-calculating this everytime. 367b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 368b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::SP); 369ad78ef215485389bb5c5698fa6f1ac670f0076d8Evan Cheng Reserved.set(ARM::PC); 370b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 371b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(FramePtr); 372b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // Some targets reserve R9. 373b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isR9Reserved()) 374b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::R9); 375b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 376b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 377b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 37836230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Chengbool 379140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { 380140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng switch (Reg) { 381140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng default: break; 382140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::SP: 383140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::PC: 384140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 385140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R7: 386140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R11: 387140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 388140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 389140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng break; 390140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R9: 391140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return STI.isR9Reserved(); 392140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 393140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 394140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return false; 395140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 396140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 397140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengbool 39836230cdda48edf6c634f2dcf69f9d78ac5a17377Evan ChengARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 39936230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 400e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng return ThumbRegScavenging || !AFI->isThumbFunction(); 4011b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng} 4021b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng 403a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 404a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 405a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 406a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 407dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 409a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 410a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 4115c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 4125c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// not required, we reserve argument space for call sites in the function 4135c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// immediately on entry to the current function. This eliminates the need for 4145c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// add/sub sp brackets around call sites. Returns true if the call frame is 4155c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// included as part of the stack frame. 4165c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Chengbool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { 4175c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 4185c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng unsigned CFSize = FFI->getMaxCallFrameSize(); 4195c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 4205c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // It's not always a good idea to include the call frame as part of the 4215c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // stack frame. ARM (especially Thumb) has small immediate offset to 4225c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // address the stack frame. So a large call frame can cause poor codegen 4235c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // and may even makes it impossible to scavenge a register. 4245c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (AFI->isThumbFunction()) { 4255c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 4265c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return false; 4275c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng } else { 4285c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 4295c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return false; 4305c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng } 4315c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return !hasFP(MF); 4325c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng} 4335c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng 43436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 435a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 436a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 437a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 438a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 4393b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 4403b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 4413b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng const TargetInstrInfo &TII) { 442a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 443a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 444a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 445a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 446a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 447a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 448a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 449a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 450a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 451a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 452a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 453a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 454a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 455a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 456a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 457a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 458a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 45944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addReg(BaseReg, false, false, true).addImm(SOImmVal) 46013ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 461a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 462a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 463a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 464a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 46536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 46636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 46736640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 46836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 46936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 47036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 47136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 47236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 47336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 47436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 47536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 47636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 4773d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 1; // Followed by a number of tADDi8. 47836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 47936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 48036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 48136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 48236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 48336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 48436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 48536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 48636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 48736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 48836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 489403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 490403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 491403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 49236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 49336640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 494403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 49536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 49636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 497a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 498a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 4997142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 5007142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 50136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 50236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 503a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 504a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 505a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 506a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 50736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 50836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 50936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 51036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 51136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 51236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 51336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 5149f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12) 5155ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 51636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 517a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 518a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 5199f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 5208bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 5219f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 5225ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) 5235ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(LdReg, false, false, true); 5248bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 5253b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true); 5267142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 52736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 52836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 52936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 5305ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng if (DestReg == ARM::SP || isSub) 5315ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(BaseReg).addReg(LdReg, false, false, true); 53236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 5335ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(LdReg).addReg(BaseReg, false, false, true); 53436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 5359f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3) 5365ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 53736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 53836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 53936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 541a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 542a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 547a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 548a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 550a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 5518e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 552a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 5535b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 55436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 55536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 556a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 557a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 559a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 5605b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 561a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 562a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 563a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 5645b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 5655b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 5665b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 5675b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 568a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 569a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 570a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 571a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 572a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 5735b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 574a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 575a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 57636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 57736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 57836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 57936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 5808e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 582a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 583a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 584a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 585a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 58636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 5878e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 58836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 58936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 59036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 591403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 59236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 59336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 59436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5958e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 59636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 59736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 59836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 59936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 60036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 60136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 6025ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(ThisVal); 60336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 6049f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg) 6055ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true); 60636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 60736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 60836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 60936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 6105b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 611a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 612a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 6135b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 6145b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 615a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 616a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 6173fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 6195ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng bool isKill = BaseReg != ARM::SP; 6205ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg) 6215ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, isKill).addImm(ThisVal); 622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 623a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 624a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 626a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 627a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 628a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 6295b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 6305b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 631a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 632a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 633a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 634a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 635a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 636a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 6385ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg) 6395ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true) 640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 643a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 644a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 6453b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, 6463b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng bool isThumb, const TargetInstrInfo &TII) { 647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 649a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 6503b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, 6513b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng Pred, PredReg, TII); 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 653a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 6547bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 6557bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 6567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 6575c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (!hasReservedCallFrame(MF)) { 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 660a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 661b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 662b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 663b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 665a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 666a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 668b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 669b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 670b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 67244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Opc = Old->getOpcode(); 67344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng bool isThumb = AFI->isThumbFunction(); 67444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ARMCC::CondCodes Pred = isThumb 67544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue(); 6763b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg(); 67744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 6783b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII); 679b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 68044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 6813b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII); 682b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 683b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 6847ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 6857bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 6867bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 6877bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 688a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 689a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 690a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 692a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 693a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 694a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 696a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 7009f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); 701a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 702a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 703a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 7045ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg) 7055ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true); 706a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 707a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 708c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// findScratchRegister - Find a 'free' ARM register. If register scavenger 709c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// is not being used, R12 is available. Otherwise, try for a call-clobbered 710c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// register first and then a spilled callee-saved register if that fails. 711c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengstatic 712c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengunsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 713c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng ARMFunctionInfo *AFI) { 714c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12; 715c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng if (Reg == 0) 716c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // Try a already spilled CS register. 717c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters()); 718c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 719c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng return Reg; 720c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng} 721c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 7221b051fc6a491c40cf3f926c089ad082938b653f0Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 72397de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng int SPAdj, RegScavenger *RS) const{ 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 72558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 72658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 72758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 728a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 729a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 73058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 731a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 732a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 733a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 734a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 735a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 736a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 737a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 738a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 73997de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng MF.getFrameInfo()->getStackSize() + SPAdj; 74058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 741a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 745a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 746a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 74775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 74897de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng assert(SPAdj == 0 && "Unexpected"); 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 750a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 751a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 752b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 753a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 754a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 755a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 756a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 757a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 758a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 7593d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 760a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 761a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 762a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 763a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 7649f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVr)); 765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 768a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 769a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 770a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 772a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 77358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 774a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 775a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 776a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 777a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 778a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 779a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 780a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 781a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 782a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 783a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 784a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 785a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 786a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 787b03eacdbf39b37a98b65b936046b22cca8215d8dEvan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 788a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 789a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 790a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 791a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 792a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 793a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 794a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 795a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 796a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 797a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 7983d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 7993d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng // Can't use tADDrSPi if it's based off the frame pointer. 8003d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumBits = 0; 8013d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Scale = 1; 8023d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (FrameReg != ARM::SP) { 8033d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Opcode = ARM::tADDi3; 8043d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDi3)); 8053d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 3; 8063d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } else { 8073d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 8; 8083d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 4; 8093d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng assert((Offset & 3) == 0 && 8103d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 8113d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } 8123d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 813a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 814a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 8159f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVr)); 816a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 817a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 818a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 819a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 820a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 821a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 8223d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Mask = (1 << NumBits) - 1; 8233d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (((Offset / Scale) & ~Mask) == 0) { 824a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 825a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 8263d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset / Scale); 827a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 828a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 829a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 830a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 831a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 8323d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale); 833a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 834a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 835a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 83688b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 837a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 838a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 839a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 840a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 841a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 842a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 843a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 844a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 845a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 8463d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Mask); 8473d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Offset = (Offset - Mask * Scale); 848a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 849a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 850a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 851a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 852a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 853a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 854a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 855a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 8565ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); 857a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 858a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 859a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 860a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 861a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 862a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 863a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 864a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 865a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 866a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 867a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 868a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 869a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 870a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 871a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 872a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 873a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 874a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 875a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 876a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 877a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 878a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 879a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 880a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 881a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 882a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 883a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 884a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 885a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 886a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 887a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 888a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 889a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 890a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 891a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 892a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 893a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 8947142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 8957142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 896a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 897a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 898a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 8998fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 900a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 901a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 902a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 90358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 904a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 9059312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 906a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 907a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 908a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 909a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 91058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 911a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 9128e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 9138e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 9148e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 9158e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 9168e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 9178e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 9188e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 9198e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 9208e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 9218e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 9228e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 92388b633165a20398d1015eec561856500fcf30d7dEvan Cheng 9245ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 9255ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 9265ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 9275ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 9285ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 9295ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 9305ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 931a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 932a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 9335ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 9345ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 9355ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 93688b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 93788b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 938a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 939a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 940a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 94188b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 942a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 943a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 944a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 945a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 946a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 947a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 948a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 94958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 950a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 951a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 952a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 953a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 9547142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 9557142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 9567142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 957403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 9587142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 9593b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true); 9607142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 9617142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 9627142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 963a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 9645b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 9655ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 9667142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 9677142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 9687142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 9695ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 970a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 971a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 972a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 973a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 974a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 975a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 976a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 9778bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 978a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 9795b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 980a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 9817142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 9825b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 9839f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 9845ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R2, false, false, true); 985a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 986a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 987f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 9889f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 9895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 9907142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 9917142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 992403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 9937142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 9943b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true); 9957142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 9967142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 9977142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 998a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 9995b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 10005ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 10017142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 10027142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 10037142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 10047142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 10058bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 10068bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 10078bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 10089f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2) 10095ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 1010f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 10119f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3) 10125ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 1013a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 1014a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 1015a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 1016a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 1017a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 1018a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 1019a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 1020c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); 1021140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (ScratchReg == 0) 1022140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // No register is "free". Scavenge a register. 102397de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); 102462ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng int PIdx = MI.findFirstPredOperandIdx(); 102562ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng ARMCC::CondCodes Pred = (PIdx == -1) 102662ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue(); 10273b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 10283b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, 10293b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng isSub ? -Offset : Offset, Pred, PredReg, TII); 10301b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1031a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 10327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 10337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1034140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengstatic unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 1035140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 1036140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int Offset = 0; 1037140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 1038140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int FixedOff = -FFI->getObjectOffset(i); 1039140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FixedOff > Offset) Offset = FixedOff; 1040140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1041140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 1042140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset += FFI->getObjectSize(i); 1043140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Align = FFI->getObjectAlignment(i); 1044140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Adjust to alignment boundary 1045140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset = (Offset+Align-1)/Align*Align; 1046140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1047140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return (unsigned)Offset; 1048140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 1049140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 1050140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengvoid 1051140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1052140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RegScavenger *RS) const { 105375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 105475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 105575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 1056a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 105775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 1058a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 1059a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 1060a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 1061a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 1062a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 1063f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 106475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 106575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 106675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 106775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 106875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 106975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 107075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 107175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 107275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 1073f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 107475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 107575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 107675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 107775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 107875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 107975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 108075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 108175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 1082a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1083a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 108475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 1085a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 108675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 108775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 108875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 108975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 1090c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1091c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 1092c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 1093356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio CS1Spilled = true; 1094c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1095c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1096c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 109775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 109875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 109975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 110075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 110175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 110275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 110375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 110475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 110575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 110675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 110775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 110875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 110975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 111075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 111175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 1112c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1113c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 1114c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1115c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1116c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 111775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 111875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 111975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 112075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 112175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 112275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 112375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 112475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 112575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 112675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 112775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 1128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1133d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 1134d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 1135d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 1136f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // Force LR to be spilled if the Thumb function size is > 2048. This enables 1137d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 1138f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // then the branch fix up path will undo it. 1139d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 1140d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 1141d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 1142d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1143d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1144d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 1145140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng bool ExtraCSSpill = false; 11467588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 114775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 1148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 11526c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(ARM::LR); 1153f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 1155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1157d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 1158140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ExtraCSSpill = true; 1159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 11613548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 11623548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 11637588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 11646c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(FramePtr); 11653548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 11663548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 11673548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1168356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // If stack and double are 8-byte aligned and we are spilling an odd number 1169356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // of GPRs. Spill one extra callee save GPR so we won't have to pad between 1170356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // the integer and double callee save areas. 1171356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1172356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1173356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1174356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1175356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned Reg = UnspilledCS1GPRs[i]; 1176356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // Don't spiil high register if the function is thumb 1177356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) { 1178356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Reg); 1179356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Reg); 1180356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!isReservedReg(MF, Reg)) 1181356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio ExtraCSSpill = true; 1182356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio break; 1183356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1184356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1185356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } else if (!UnspilledCS2GPRs.empty() && 1186356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio !AFI->isThumbFunction()) { 1187356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned Reg = UnspilledCS2GPRs.front(); 1188356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Reg); 1189356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Reg); 1190356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!isReservedReg(MF, Reg)) 1191356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio ExtraCSSpill = true; 1192356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1193356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1194356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio 1195140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Estimate if we might need to scavenge a register at some point in order 1196140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // to materialize a stack offset. If so, either spill one additiona 1197140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // callee-saved register or reserve a special spill slot to facilitate 1198140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // register scavenging. 1199140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) { 1200140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng MachineFrameInfo *MFI = MF.getFrameInfo(); 1201140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Size = estimateStackSize(MF, MFI); 1202140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Limit = (1 << 12) - 1; 1203140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) 1204140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) { 1205140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) 1206140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (I->getOperand(i).isFrameIndex()) { 1207140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Opcode = I->getOpcode(); 1208140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 1209140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1210140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (AddrMode == ARMII::AddrMode3) { 1211140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Limit = (1 << 8) - 1; 1212140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng goto DoneEstimating; 1213140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else if (AddrMode == ARMII::AddrMode5) { 12145c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng unsigned ThisLimit = ((1 << 8) - 1) * 4; 12155c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (ThisLimit < Limit) 12165c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng Limit = ThisLimit; 1217140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1218140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1219140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1220140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng DoneEstimating: 1221140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (Size >= Limit) { 1222140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // If any non-reserved CS register isn't spilled, just spill one or two 1223140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // extra. That should take care of it! 1224356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned NumExtras = TargetAlign / 4; 1225356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio SmallVector<unsigned, 2> Extras; 1226356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio while (NumExtras && !UnspilledCS1GPRs.empty()) { 1227140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS1GPRs.back(); 1228140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS1GPRs.pop_back(); 1229140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1230356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio Extras.push_back(Reg); 1231356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio NumExtras--; 1232140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1233140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1234356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio while (NumExtras && !UnspilledCS2GPRs.empty()) { 1235140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS2GPRs.back(); 1236140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS2GPRs.pop_back(); 1237140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1238356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio Extras.push_back(Reg); 1239356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio NumExtras--; 1240140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1241140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1242356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (Extras.size() && NumExtras == 0) { 1243356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1244356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Extras[i]); 1245356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Extras[i]); 1246356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1247140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else { 1248140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Reserve a slot closest to SP or frame pointer. 1249140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetRegisterClass *RC = &ARM::GPRRegClass; 1250140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1251140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RC->getAlignment())); 1252140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1253f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng } 1254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 125678268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 1257d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 12586c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(ARM::LR); 1259f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1260f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setLRIsSpilledForFarJump(true); 1261d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1264a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 1265a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 1266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 1267a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1274a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 127775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1280a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 128175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1282970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 128475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 128575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1286a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1287a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1288a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1289a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1298a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 12997bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 13007bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1301355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 130244819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1303355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1304a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1305a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1306a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1307a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1308a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1309355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1310236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 13118bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 13128bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 13138bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 13148bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 13158bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 13168bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 13178bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 13188bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 13198bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1320236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1321236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1322236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1323236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1324236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1325a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1326a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1327a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1328a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1329acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1330acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (VARegSaveSize) 13313b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII); 1332acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1333236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1334236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 13353b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII); 1336236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1337236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1338236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1339236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1340236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1341236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1342236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1343236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1344236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1345236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1346236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1347236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1348236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1349236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1350236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1351236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1352236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1353236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1354236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1355236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1356236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1357236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1358236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1359236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1360236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1361236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1362236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1363a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1364a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1365a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1366236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1367236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1368236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1369236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1370a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1371236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1372a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1373236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1374236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 13753b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII); 1376236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1377236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1378236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1379a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 13803548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 13813548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 138244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 138344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng MachineInstrBuilder MIB = 138444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr) 1385236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 138613ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng if (!isThumb) MIB.addImm(ARMCC::AL).addReg(0).addReg(0); 138744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng } 1388a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1389236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1390236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 13913b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII); 1392a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1393236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1394236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 13953b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII); 1396a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 13977ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1398a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1399236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1400236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1401236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1402236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1403236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1404236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1405236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1406a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1407236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1408236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1409236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1410236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1411236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 14123b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII); 1413236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 141415f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1415e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio if(STI.isTargetELF() && hasFP(MF)) { 1416e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1417e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio AFI->getFramePtrSpillOffset()); 1418e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio } 1419e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio 1420a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1421a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1422a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1423a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 14247ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1425a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1426a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1427a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1428a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1429a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1430a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1431a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1432a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1433a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1434a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 14358e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1436a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1437a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 14387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 14397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 14407bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 1441bed2946a96ecb15b0b636fa74cb26ce61b1c648eAnton Korobeynikov MachineBasicBlock &MBB) const { 1442355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1443a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1444a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1445a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1446355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1447355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1448355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1449a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1450a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1451a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1452a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1453236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1454236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 14553b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 14569d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 1457acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Unwind MBBI to point to first LDR / FLDD. 1458acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio const unsigned *CSRegs = getCalleeSavedRegs(); 1459acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI != MBB.begin()) { 1460acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio do 1461acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio --MBBI; 1462acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1463acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (!isCSRestore(MBBI, CSRegs)) 1464acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio ++MBBI; 1465acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1466acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1467acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of FP callee save spill area. 1468acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1469acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getGPRCalleeSavedArea2Size() + 1470acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize()); 1471acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (isThumb) { 1472acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (hasFP(MF)) { 1473acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1474acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1475acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1476236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1477acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 1478236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 14799f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); 1480acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1481acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI->getOpcode() == ARM::tBX_RET && 1482acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio &MBB.front() != MBBI && 1483acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio prior(MBBI)->getOpcode() == ARM::tPOP) { 1484acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio MachineBasicBlock::iterator PMBBI = prior(MBBI); 14853b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 1486acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else 14873b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 1488acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1489acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1490acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Darwin ABI requires FP to point to the stack slot that contains the 1491acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // previous FP. 14929f8e50d4ed7dcc5ca0f137830ff1185b2afa38bfDale Johannesen if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) { 1493acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1494acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1495acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1496acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (AFI->getGPRCalleeSavedArea2Size() || 1497acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize() || 1498acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 1499acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio hasFP(MF)) 1500acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (NumBytes) 1501acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 150213ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm(NumBytes) 150313ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1504acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio else 150544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr) 150613ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1507acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else if (NumBytes) { 15083b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII); 1509acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 15103548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1511acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 2. 1512acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 15133b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0, 151444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1515236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1516acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 1. 1517acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 15183b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0, 151944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1520236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1521acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to SP upon entry to the function. 1522acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 15233b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0, 152444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1525acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1526a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1527236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 15289d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1529f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1530f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1531f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1532f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1533f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 15343b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII); 1535f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1536f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1537f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1538f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1539f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 15409d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 15417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 15427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 15437bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 15457bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 15467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 15477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1548267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio if (STI.isTargetDarwin() || hasFP(MF)) 15494c6d20a096ad28aa6f812c07a48268e8a6ccb8feLauro Ramos Venancio return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11; 1550267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio else 1551267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio return ARM::SP; 15527bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 15537bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 155462819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHExceptionRegister() const { 155562819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception register"); 155662819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 155762819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 155862819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 155962819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHHandlerRegister() const { 156062819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception handler register"); 156162819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 156262819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 156362819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 15647bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 15657bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1566