ARMRegisterInfo.cpp revision 267bfb553e3ab44de2d4bac2866afc6de808c3f8
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 285ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng#include "llvm/CodeGen/RegisterScavenging.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 30b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 317ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 32b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 35ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng#include "llvm/Support/CommandLine.h" 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 39e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Chengstatic cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging", 40e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::Hidden, 41e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::desc("Enable register scavenging on Thumb")); 42ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng 43a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 76a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 798fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 80a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 8115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 8215f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 8315f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 84a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 86c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 88a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) { 895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng} 905ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng 91a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 100ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 101ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng unsigned Reg = CSI[i-1].getReg(); 102ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng // Add the callee-saved register as live-in. It's killed at the spill. 103ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MBB.addLiveIn(Reg); 104ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); 105ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng } 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 109a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1179d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1239d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1249d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1259d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1367bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 143ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true) 144a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 146ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true) 147a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 149ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true) 150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 153ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true) 154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1577bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1597bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1607bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1617bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1668e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 170a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1797bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1807bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1817bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1889f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVr : ARM::MOVr), 189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng DestReg).addReg(SrcReg); 190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 191c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); 192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 193c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg); 194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 1967bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1977bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 198bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize the 199bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// specified immediate. 200bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 201bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator &MBBI, 202bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned DestReg, int Val, 203bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const TargetInstrInfo &TII, bool isThumb) { 204bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineFunction &MF = *MBB.getParent(); 205bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 206bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, Val); 207bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 208bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (isThumb) 209bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx); 210bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng else 211bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx) 212bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng .addReg(0).addImm(0); 213bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 214bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 215bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengvoid ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 216bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator I, 217bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned DestReg, 218bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const MachineInstr *Orig) const { 219bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (Orig->getOpcode() == ARM::MOVi2pieces) { 220bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImmedValue(), 221bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng TII, false); 222bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng return; 223bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng } 224bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 225bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineInstr *MI = Orig->clone(); 226bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MI->getOperand(0).setReg(DestReg); 227bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MBB.insert(I, MI); 228bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 229bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 23040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 23140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 23240984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 23340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 23440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 23540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 23640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 23740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 23840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 23940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 24040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 24140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 24240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 243a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 247a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 248a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 2499f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::MOVr: { 250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(0).addImm(0); 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 2619f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::tMOVr: { 262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 264bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 2658e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 26640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2678e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 271bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 2728e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 27340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2748e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 280a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 281a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 282a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 286a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0); 287a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 288a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 289a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0); 298a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 299a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 300a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 301a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 303a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 304a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 305a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 3067bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 3077bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 308c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 309c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 310a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 311a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 312a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 313a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 314a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 315a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 316ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 317a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 318a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 319a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 320a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 321a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 322a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 323a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 324a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 325a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 326970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 3270f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3280f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 3290f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 330c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 331c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 332a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 333a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 334a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 335a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 336a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 337a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 338a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 339ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 340c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 3410f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3420f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 343b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 344c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // FIXME: avoid re-calculating this everytime. 345b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 346b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::SP); 347ad78ef215485389bb5c5698fa6f1ac670f0076d8Evan Cheng Reserved.set(ARM::PC); 348b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 349b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(FramePtr); 350b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // Some targets reserve R9. 351b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isR9Reserved()) 352b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::R9); 353b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // At PEI time, if LR is used, it will be spilled upon entry. 354b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR)) 355b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::LR); 356b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 357b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 358b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 35936230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Chengbool 360140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { 361140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng switch (Reg) { 362140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng default: break; 363140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::SP: 364140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::PC: 365140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 366140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R7: 367140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R11: 368140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 369140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 370140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng break; 371140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R9: 372140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return STI.isR9Reserved(); 373140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 374140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 375140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return false; 376140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 377140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 378140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengbool 37936230cdda48edf6c634f2dcf69f9d78ac5a17377Evan ChengARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 38036230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 381e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng return ThumbRegScavenging || !AFI->isThumbFunction(); 3821b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng} 3831b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng 384a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 385a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 386a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 387a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 388dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 389a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 390a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 391a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 39236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 393a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 394a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 395a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 396a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 397a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 398a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 399a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 400a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 401a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 402a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 403a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 404a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 405a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 406a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 407a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 409a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 410a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 411a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 412a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 413a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 414a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 415a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 4165ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(SOImmVal); 417a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 418a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 419a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 420a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 42136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 42236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 42336640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 42436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 42536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 42636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 42736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 42836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 42936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 43036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 43136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 43236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 4333d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 1; // Followed by a number of tADDi8. 43436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 43536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 43636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 43736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 43836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 43936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 44036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 44136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 44236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 44336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 44436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 445403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 446403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 447403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 44836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 44936640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 450403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 45136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 45236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 453a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 454a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 4557142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 4567142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 45736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 45836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 459a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 460a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 461a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 462a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 46336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 46436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 46536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 46636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 46736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 46836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 46936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 4709f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12) 4715ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 47236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 473a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 474a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 4759f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 4768bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 4779f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 4785ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) 4795ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(LdReg, false, false, true); 4808bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 481bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII, true); 4827142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 48336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 48436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 48536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 4865ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng if (DestReg == ARM::SP || isSub) 4875ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(BaseReg).addReg(LdReg, false, false, true); 48836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 4895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(LdReg).addReg(BaseReg, false, false, true); 49036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 4919f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3) 4925ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 49336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 49436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 49536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 496a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 497a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 498a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 499a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 500a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 501a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 502a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 503a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 504a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 505a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 506a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 5078e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 508a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 5095b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 51036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 51136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 512a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 513a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 514a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 515a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 5165b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 517a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 518a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 519a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 5205b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 5215b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 5225b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 5235b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 524a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 525a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 526a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 527a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 528a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 5295b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 531a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 53236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 53336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 53436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 53536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 5368e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 537a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 538a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 539a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 541a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 54236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 5438e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 54436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 54536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 54636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 547403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 54836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 54936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 55036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5518e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 55236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 55336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 55436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 55536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 55636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 55736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 5585ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(ThisVal); 55936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 5609f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg) 5615ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true); 56236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 56336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 56436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 56536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5665b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 567a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 568a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 5695b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 5705b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 571a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 572a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 5733fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 574a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 5755ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng bool isKill = BaseReg != ARM::SP; 5765ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg) 5775ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, isKill).addImm(ThisVal); 578a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 579a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 580a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 582a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 583a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 584a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 5855b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 5865b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 587a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 588a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 589a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 590a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 592a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 5945ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg) 5955ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true) 596a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 597a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 598a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 599a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 600a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 601a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, bool isThumb, const TargetInstrInfo &TII) { 602a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 603a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 604a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 605a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 607a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 6087bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 6097bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 6107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 61175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (hasFP(MF)) { 612a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 613a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 614a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 615b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 616b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 617b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 619a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 620a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 621a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 622b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 623b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 624b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 626b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) { 627a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII); 628b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 629b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola assert(Old->getOpcode() == ARM::ADJCALLSTACKUP); 630a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII); 631b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 632b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 6337ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 6347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 6357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 6367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 638a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 639a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 643a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 644a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 645a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 6499f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); 650a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 651a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 6535ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg) 6545ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true); 655a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 656a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 657c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// findScratchRegister - Find a 'free' ARM register. If register scavenger 658c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// is not being used, R12 is available. Otherwise, try for a call-clobbered 659c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// register first and then a spilled callee-saved register if that fails. 660c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengstatic 661c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengunsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 662c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng ARMFunctionInfo *AFI) { 663c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12; 664c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng if (Reg == 0) 665c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // Try a already spilled CS register. 666c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters()); 667c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 668c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng return Reg; 669c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng} 670c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 6711b051fc6a491c40cf3f926c089ad082938b653f0Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 6721b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng RegScavenger *RS) const{ 673a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 67458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 67558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 67658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 677a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 67958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 687a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 688a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.getFrameInfo()->getStackSize(); 68958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 690a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 692a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 693a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 694a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 69675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 700b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 701a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 702a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 703a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 704a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 705a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 706a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 7073d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 708a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 709a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 710a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 711a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 7129f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVr)); 713a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 714a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 715a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 716a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 717a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 72158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 725a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 726a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 727a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 728a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 729a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 730a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 731a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 732a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 733a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 734a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 735b03eacdbf39b37a98b65b936046b22cca8215d8dEvan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 736a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 737a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 738a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 739a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 740a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 741a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 745a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 7463d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 7473d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng // Can't use tADDrSPi if it's based off the frame pointer. 7483d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumBits = 0; 7493d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Scale = 1; 7503d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (FrameReg != ARM::SP) { 7513d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Opcode = ARM::tADDi3; 7523d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDi3)); 7533d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 3; 7543d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } else { 7553d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 8; 7563d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 4; 7573d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng assert((Offset & 3) == 0 && 7583d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 7593d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } 7603d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 761a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 762a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 7639f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVr)); 764a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 768a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 769a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 7703d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Mask = (1 << NumBits) - 1; 7713d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (((Offset / Scale) & ~Mask) == 0) { 772a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 773a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 7743d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset / Scale); 775a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 776a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 777a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 778a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 779a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 7803d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale); 781a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 782a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 783a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 78488b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 785a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 786a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 787a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 788a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 789a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 790a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 791a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 792a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 793a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 7943d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Mask); 7953d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Offset = (Offset - Mask * Scale); 796a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 797a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 798a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 799a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 800a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 801a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 802a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 803a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 8045ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); 805a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 806a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 807a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 808a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 809a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 810a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 811a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 812a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 813a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 814a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 815a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 816a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 817a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 818a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 819a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 820a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 821a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 822a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 823a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 824a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 825a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 826a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 827a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 828a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 829a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 830a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 831a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 832a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 833a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 834a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 835a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 836a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 837a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 838a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 839a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 840a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 841a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 8427142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 8437142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 844a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 845a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 846a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 8478fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 848a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 849a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 850a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 85158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 852a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 8539312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 854a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 855a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 856a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 857a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 85858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 859a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 8608e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 8618e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 8628e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 8638e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 8648e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 8658e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 8668e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 8678e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 8688e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 8698e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 8708e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 87188b633165a20398d1015eec561856500fcf30d7dEvan Cheng 8725ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 8735ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 8745ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 8755ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 8765ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 8775ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 8785ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 879a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 880a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 8815ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 8825ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 8835ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 88488b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 88588b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 886a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 887a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 888a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 88988b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 890a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 891a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 892a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 893a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 894a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 895a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 896a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 89758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 898a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 899a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 900a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 901a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 9027142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 9037142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 9047142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 905403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 9067142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 907bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true); 9087142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 9097142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 9107142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 911a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 9125b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 9135ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 9147142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 9157142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 9167142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 9175ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 918a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 919a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 920a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 921a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 922a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 923a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 924a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 9258bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 926a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 9275b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 928a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 9297142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 9305b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 9319f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 9325ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R2, false, false, true); 933a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 934a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 935f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 9369f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 9375ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 9387142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 9397142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 940403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 9417142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 942bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true); 9437142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 9447142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 9457142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 946a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 9475b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 9485ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 9497142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 9507142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 9517142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 9527142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 9538bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 9548bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 9558bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 9569f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2) 9575ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 958f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 9599f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3) 9605ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 961a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 962a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 963a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 964a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 965a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 966a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 967a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 968c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); 969140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (ScratchReg == 0) 970140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // No register is "free". Scavenge a register. 971140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II); 9721b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, 973a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 9741b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 975a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 9767bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 9777bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 978140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengstatic unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 979140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 980140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int Offset = 0; 981140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 982140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int FixedOff = -FFI->getObjectOffset(i); 983140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FixedOff > Offset) Offset = FixedOff; 984140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 985140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 986140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset += FFI->getObjectSize(i); 987140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Align = FFI->getObjectAlignment(i); 988140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Adjust to alignment boundary 989140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset = (Offset+Align-1)/Align*Align; 990140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 991140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return (unsigned)Offset; 992140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 993140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 994140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengvoid 995140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 996140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RegScavenger *RS) const { 99775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 99875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 99975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 1000a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 100175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 1002a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 1003a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 1004a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 1005a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 1006a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 1007f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 100875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 100975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 101075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 101175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 101275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 101375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 101475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 101575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 101675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 1017f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 101875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 101975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 102075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 102175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 102275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 102375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 102475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 102575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 1026a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1027a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 102875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 1029a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 103075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 103175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 103275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 103375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 1034c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1035c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 1036c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 1037c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else 1038c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng CS1Spilled = true; 1039c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1040c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1041c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 104275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 104375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 104475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 104575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 104675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 104775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 104875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 104975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 105075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 105175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 105275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 105375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 105475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 105575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 105675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 1057c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1058c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 1059c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1060c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1061c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 106275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 106375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 106475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 106575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 106675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 106775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 106875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 106975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 107075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 107175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 107275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 1073a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1074a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1075a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1076a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1077a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1078d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 1079d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 1080d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 1081f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // Force LR to be spilled if the Thumb function size is > 2048. This enables 1082d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 1083f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // then the branch fix up path will undo it. 1084d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 1085d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 1086d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 1087d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1088d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1089d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 1090140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng bool ExtraCSSpill = false; 10917588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 109275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 1093a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1094a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1095a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1096a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 1097a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(ARM::LR, true); 1098f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1099a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 1100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1102d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 1103140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ExtraCSSpill = true; 1104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1105a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 11063548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 11073548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 11087588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 11093548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng MF.changePhyRegUsed(FramePtr, true); 11103548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 11113548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 11123548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1113c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng // If stack and double are 8-byte aligned and we are spilling an odd number 1114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of GPRs. Spill one extra callee save GPR so we won't have to pad between 1115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // the integer and double callee save areas. 1116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1118f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1119f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng unsigned Reg = UnspilledCS1GPRs.front(); 1120f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng MF.changePhyRegUsed(Reg, true); 1121f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 1122140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) 1123140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ExtraCSSpill = true; 1124f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng } else if (!UnspilledCS2GPRs.empty()) { 1125f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng unsigned Reg = UnspilledCS2GPRs.front(); 1126f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng MF.changePhyRegUsed(Reg, true); 1127f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 1128140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) 1129140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ExtraCSSpill = true; 1130140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1131140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1132140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 1133140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Estimate if we might need to scavenge a register at some point in order 1134140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // to materialize a stack offset. If so, either spill one additiona 1135140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // callee-saved register or reserve a special spill slot to facilitate 1136140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // register scavenging. 1137140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) { 1138140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng MachineFrameInfo *MFI = MF.getFrameInfo(); 1139140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Size = estimateStackSize(MF, MFI); 1140140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Limit = (1 << 12) - 1; 1141140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) 1142140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) { 1143140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) 1144140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (I->getOperand(i).isFrameIndex()) { 1145140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Opcode = I->getOpcode(); 1146140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 1147140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1148140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (AddrMode == ARMII::AddrMode3) { 1149140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Limit = (1 << 8) - 1; 1150140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng goto DoneEstimating; 1151140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else if (AddrMode == ARMII::AddrMode5) { 1152140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Limit = ((1 << 8) - 1) * 4; 1153140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng goto DoneEstimating; 1154140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1155140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1156140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1157140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng DoneEstimating: 1158140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (Size >= Limit) { 1159140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // If any non-reserved CS register isn't spilled, just spill one or two 1160140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // extra. That should take care of it! 1161140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned NumExtras = TargetAlign / 4; 1162140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng SmallVector<unsigned, 2> Extras; 1163140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng while (NumExtras && !UnspilledCS1GPRs.empty()) { 1164140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS1GPRs.back(); 1165140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS1GPRs.pop_back(); 1166140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1167140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Extras.push_back(Reg); 1168140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng NumExtras--; 1169140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1170140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1171140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng while (NumExtras && !UnspilledCS2GPRs.empty()) { 1172140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS2GPRs.back(); 1173140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS2GPRs.pop_back(); 1174140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1175140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Extras.push_back(Reg); 1176140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng NumExtras--; 1177140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1178140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1179140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (Extras.size() && NumExtras == 0) { 1180140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1181140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng MF.changePhyRegUsed(Extras[i], true); 1182140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng AFI->setCSRegisterIsSpilled(Extras[i]); 1183140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1184140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else { 1185140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Reserve a slot closest to SP or frame pointer. 1186140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetRegisterClass *RC = &ARM::GPRRegClass; 1187140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1188140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RC->getAlignment())); 1189140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1190f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng } 1191a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 119378268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 1194d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 1195d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng MF.changePhyRegUsed(ARM::LR, true); 1196f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1197f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setLRIsSpilledForFarJump(true); 1198d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1200a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 1202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 1203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 1204a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 121475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 121875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1219970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 122175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 122275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1230a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 12367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1238355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 123944819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1240355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1241a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1242a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1243a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1247355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1248236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 12498bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 12508bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 12518bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 12528bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 12538bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 12548bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 12558bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 12568bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 12578bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1258236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1259236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1260236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1261236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1262236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1264a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1265a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1267acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1268acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (VARegSaveSize) 1269acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII); 1270acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1271236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1272236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 1273236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1274236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1275236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1276236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1277236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1278236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1279236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1280236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1281236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1282236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1283236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1284236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1285236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1286236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1287236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1288236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1289236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1290236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1291236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1292236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1293236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1294236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1295236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1296236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1297236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1298236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1299236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1300236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1301a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1303a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1304236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1305236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1306236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1307236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1308a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1309236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1310a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1311236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Align == 8 && (GPRCS1Size & 7) != 0) 1312236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Pad CS1 to ensure proper alignment. 1313236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1314c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 1315236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1316236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1317236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII); 1318236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1319236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1320236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1321a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 13223548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 13233548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 13243548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 1325236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr) 1326236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 1327a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1328236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1329236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1330236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII); 1331a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1332236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1333236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 1334236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII); 1335a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 13367ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1337a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1338236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1339236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1340236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1341236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1342236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1343236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1344236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1345a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1346236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1347236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1348236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1349236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1350236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 1351a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1352236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 135315f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1354a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1355a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1356a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1357a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 13587ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1359a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1360a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1361a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1362a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1363a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1364a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1365a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1366a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1367a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1368a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 13698e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1370a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1371a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 13727bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 13737bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 13747bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 1375bed2946a96ecb15b0b636fa74cb26ce61b1c648eAnton Korobeynikov MachineBasicBlock &MBB) const { 1376355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1377a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1378a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1379a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1380355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1381355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1382355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1383a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1384a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1385a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1386a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1387236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1388236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 13893df62bde9b3f2557cccfa1f18d25b57bf0477f60Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 13909d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 1391acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Unwind MBBI to point to first LDR / FLDD. 1392acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio const unsigned *CSRegs = getCalleeSavedRegs(); 1393acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI != MBB.begin()) { 1394acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio do 1395acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio --MBBI; 1396acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1397acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (!isCSRestore(MBBI, CSRegs)) 1398acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio ++MBBI; 1399acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1400acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1401acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of FP callee save spill area. 1402acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1403acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getGPRCalleeSavedArea2Size() + 1404acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize()); 1405acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (isThumb) { 1406acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (hasFP(MF)) { 1407acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1408acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1409acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1410236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1411acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 1412236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 14139f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); 1414acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1415acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI->getOpcode() == ARM::tBX_RET && 1416acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio &MBB.front() != MBBI && 1417acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio prior(MBBI)->getOpcode() == ARM::tPOP) { 1418acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio MachineBasicBlock::iterator PMBBI = prior(MBBI); 1419acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII); 1420acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else 1421acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 1422acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1423acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1424acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Darwin ABI requires FP to point to the stack slot that contains the 1425acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // previous FP. 14269f8e50d4ed7dcc5ca0f137830ff1185b2afa38bfDale Johannesen if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) { 1427acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1428acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1429acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1430acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (AFI->getGPRCalleeSavedArea2Size() || 1431acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize() || 1432acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 1433acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio hasFP(MF)) 1434acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (NumBytes) 1435acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 1436acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio .addImm(NumBytes); 1437acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio else 14389f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr); 1439acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else if (NumBytes) { 1440acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, NumBytes, false, TII); 1441acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 14423548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1443acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 2. 1444acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 1445acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII); 1446236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1447acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 1. 1448acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 1449acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII); 1450236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1451acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to SP upon entry to the function. 1452acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 1453acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII); 1454acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1455a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1456236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 14579d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1458f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1459f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1460f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1461f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1462f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1463236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII); 1464f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1465f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1466f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1467f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1468f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 14699d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 14707bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 14717bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 14727bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1473a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 14747bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 14757bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 14767bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1477267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio if (STI.isTargetDarwin() || hasFP(MF)) 1478267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11; 1479267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio else 1480267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio return ARM::SP; 14817bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 14827bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 148362819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHExceptionRegister() const { 148462819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception register"); 148562819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 148662819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 148762819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 148862819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHHandlerRegister() const { 148962819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception handler register"); 149062819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 149162819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 149262819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 14937bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 14947bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1495