ARMRegisterInfo.cpp revision 3d06cf4584b44ea8c4a49778c2b61f8990692157
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 285ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng#include "llvm/CodeGen/RegisterScavenging.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 30b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 317ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 32b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 35ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng#include "llvm/Support/CommandLine.h" 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 39e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Chengstatic cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging", 40e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::Hidden, 41e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::desc("Enable register scavenging on Thumb")); 42ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng 43a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 76a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 798fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 80a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 8115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 8215f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 8315f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 84a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 86c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 88a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) { 895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng} 905ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng 91a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 100ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 101ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng unsigned Reg = CSI[i-1].getReg(); 102ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng // Add the callee-saved register as live-in. It's killed at the spill. 103ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MBB.addLiveIn(Reg); 104ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); 105ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng } 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 109a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1179d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1239d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1249d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1259d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1367bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 143ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true) 144a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 146ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true) 147a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 149ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true) 150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 153ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true) 154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1577bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1597bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1607bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1617bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1668e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 170a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1797bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1807bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1817bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr), 189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng DestReg).addReg(SrcReg); 190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 191c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); 192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 193c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg); 194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 1967bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1977bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 19840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 19940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 20040984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 20140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 20240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 20340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 20440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 20540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 20640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 20740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 20840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 20940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 21040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 211a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::MOVrr: { 218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(0).addImm(0); 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::tMOVrr: { 230a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 232bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 2338e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 23440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2358e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 236a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 239bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 2408e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 24140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2428e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 243a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 247a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 248a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 249a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0); 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 261a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 264a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 265a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0); 266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 2747bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2757bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 276c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 277c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 280a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 281a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 282a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 284ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 286a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 287a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 288a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 289a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 294970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 2950f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 2960f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 2970f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 298c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 299c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 300a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 301a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 303a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 304a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 305a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 306a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 307ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 308c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 3090f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3100f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 311b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 312c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // FIXME: avoid re-calculating this everytime. 313b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 314b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::SP); 315ad78ef215485389bb5c5698fa6f1ac670f0076d8Evan Cheng Reserved.set(ARM::PC); 316b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 317b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(FramePtr); 318b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // Some targets reserve R9. 319b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isR9Reserved()) 320b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::R9); 321b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // At PEI time, if LR is used, it will be spilled upon entry. 322b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR)) 323b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::LR); 324b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 325b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 326b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 32736230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Chengbool 328140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { 329140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng switch (Reg) { 330140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng default: break; 331140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::SP: 332140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::PC: 333140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 334140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R7: 335140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R11: 336140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 337140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 338140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng break; 339140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R9: 340140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return STI.isR9Reserved(); 341140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 342140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 343140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return false; 344140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 345140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 346140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengbool 34736230cdda48edf6c634f2dcf69f9d78ac5a17377Evan ChengARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 34836230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 349e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng return ThumbRegScavenging || !AFI->isThumbFunction(); 3501b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng} 3511b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng 352a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 353a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 354a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 355a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 356dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 357a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 358a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 359a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 36036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 361a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 362a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 363a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 364a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 365a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 366a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 367a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 368a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 369a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 370a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 371a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 372a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 373a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 374a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 375a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 376a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 377a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 378a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 379a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 380a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 381a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 382a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 383a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 3845ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(SOImmVal); 385a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 386a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 387a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 388a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 38936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 39036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 39136640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 39236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 39336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 39436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 39536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 39636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 39736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 39836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 39936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 40036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 4013d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 1; // Followed by a number of tADDi8. 40236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 40336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 40436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 40536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 40636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 40736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 40836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 40936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 41036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 41136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 41236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 4137142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize NumBytes 4147142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// immediate. 4157142f8755a07512d909d288f74a3f1ffa9c1411aEvan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 4167142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineBasicBlock::iterator &MBBI, 4177142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned DestReg, int NumBytes, 4187142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng const TargetInstrInfo &TII) { 4197142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineFunction &MF = *MBB.getParent(); 4207142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 4217142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes); 4227142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 4237142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx); 4247142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng} 4257142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 426403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 427403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 428403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 42936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 43036640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 431403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 43236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 43336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 434a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 435a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 4367142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 4377142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 43836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 43936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 440a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 441a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 442a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 443a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 44436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 44536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 44636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 44736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 44836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 44936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 45036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 4515ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12) 4525ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 45336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 454a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 455a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 456a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4578bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 4588bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4595ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) 4605ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(LdReg, false, false, true); 4618bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 4627142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII); 4637142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 46436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 46536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 46636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 4675ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng if (DestReg == ARM::SP || isSub) 4685ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(BaseReg).addReg(LdReg, false, false, true); 46936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 4705ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(LdReg).addReg(BaseReg, false, false, true); 47136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 4725ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3) 4735ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 47436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 47536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 47636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 477a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 478a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 479a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 480a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 481a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 482a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 483a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 484a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 485a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 486a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 487a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 4888e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 489a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 4905b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 49136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 49236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 493a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 495a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 496a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 4975b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 498a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 499a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 500a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 5015b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 5025b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 5035b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 5045b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 505a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 506a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 507a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 508a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 509a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 5105b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 511a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 512a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 51336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 51436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 51536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 51636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 5178e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 518a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 519a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 520a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 521a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 522a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 52336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 5248e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 52536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 52636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 52736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 528403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 52936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 53036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 53136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5328e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 53336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 53436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 53536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 53636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 53736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 53836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 5395ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(ThisVal); 54036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 5415ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg) 5425ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true); 54336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 54436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 54536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 54636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5475b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 548a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 5505b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 5515b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 552a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 5543fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 555a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 5565ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng bool isKill = BaseReg != ARM::SP; 5575ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg) 5585ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, isKill).addImm(ThisVal); 559a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 560a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 561a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 562a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 563a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 565a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 5665b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 5675b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 568a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 569a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 570a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 571a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 572a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 573a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 574a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 5755ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg) 5765ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true) 577a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 578a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 579a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 580a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 581a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 582a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, bool isThumb, const TargetInstrInfo &TII) { 583a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 584a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 585a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 586a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 587a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 588a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5897bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 5907bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 5917bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 59275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (hasFP(MF)) { 593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 594a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 595a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 596b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 597b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 598b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 599a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 600a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 601a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 602a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 603b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 604b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 605b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 607b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) { 608a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII); 609b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 610b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola assert(Old->getOpcode() == ARM::ADJCALLSTACKUP); 611a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII); 612b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 613b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 6147ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 6157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 6167bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 6177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 619a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 620a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 621a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 623a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 624a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 626a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 627a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 628a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 629a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 630a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal); 631a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 632a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 633a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 6345ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg) 6355ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true); 636a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 638c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// findScratchRegister - Find a 'free' ARM register. If register scavenger 639c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// is not being used, R12 is available. Otherwise, try for a call-clobbered 640c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// register first and then a spilled callee-saved register if that fails. 641c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengstatic 642c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengunsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 643c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng ARMFunctionInfo *AFI) { 644c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12; 645c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng if (Reg == 0) 646c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // Try a already spilled CS register. 647c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters()); 648c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 649c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng return Reg; 650c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng} 651c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 6521b051fc6a491c40cf3f926c089ad082938b653f0Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 6531b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng RegScavenger *RS) const{ 654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 65558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 65658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 65758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 66058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 661a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 662a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 663a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 665a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 666a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 668a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 669a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.getFrameInfo()->getStackSize(); 67058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 672a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 673a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 674a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 675a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 676a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 67775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 679a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 681b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 687a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 6883d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 689a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 690a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 692a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 693a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVrr)); 694a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 696a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 700a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 701a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 70258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 703a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 704a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 705a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 706a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 707a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 708a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 709a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 710a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 711a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 712a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 713a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 714a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 715a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 716a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31); 717a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 721a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 725a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 726a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 7273d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 7283d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng // Can't use tADDrSPi if it's based off the frame pointer. 7293d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumBits = 0; 7303d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Scale = 1; 7313d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (FrameReg != ARM::SP) { 7323d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Opcode = ARM::tADDi3; 7333d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDi3)); 7343d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 3; 7353d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } else { 7363d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 8; 7373d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 4; 7383d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng assert((Offset & 3) == 0 && 7393d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 7403d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } 7413d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVrr)); 745a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 746a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 747a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 748a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 750a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 7513d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Mask = (1 << NumBits) - 1; 7523d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (((Offset / Scale) & ~Mask) == 0) { 753a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 754a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 7553d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset / Scale); 756a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 757a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 758a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 759a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 760a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 7613d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale); 762a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 763a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 764a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 76588b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 766a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 767a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 768a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 769a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 770a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 772a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 773a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 774a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 7753d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Mask); 7763d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Offset = (Offset - Mask * Scale); 777a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 778a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 779a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 780a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 781a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 782a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 783a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 784a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 7855ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); 786a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 787a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 788a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 789a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 790a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 791a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 792a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 793a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 794a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 795a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 796a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 797a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 798a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 799a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 800a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 801a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 802a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 803a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 804a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 805a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 806a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 807a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 808a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 809a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 810a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 811a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 812a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 813a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 814a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 815a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 816a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 817a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 818a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 819a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 820a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 821a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 822a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 8237142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 8247142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 825a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 826a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 827a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 8288fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 829a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 830a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 831a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 83258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 833a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 8349312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 835a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 836a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 837a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 838a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 83958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 840a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 8418e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 8428e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 8438e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 8448e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 8458e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 8468e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 8478e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 8488e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 8498e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 8508e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 8518e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 85288b633165a20398d1015eec561856500fcf30d7dEvan Cheng 8535ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 8545ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 8555ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 8565ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 8575ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 8585ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 8595ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 860a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 861a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 8625ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 8635ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 8645ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 86588b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 86688b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 867a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 868a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 869a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 87088b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 871a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 872a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 873a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 874a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 875a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 876a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 877a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 87858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 879a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 880a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 881a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 882a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 8837142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 8847142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 8857142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 886403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 8877142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 8887142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 8897142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 8907142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 8917142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 892a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8935b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 8945ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 8957142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 8967142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 8977142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 8985ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 899a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 900a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 901a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 902a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 903a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 904a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 905a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 9068bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 907a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 9085b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 909a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 9107142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 9115b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 9125ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12) 9135ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R2, false, false, true); 914a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 915a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 916f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 9175ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12) 9185ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 9197142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 9207142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 921403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 9227142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 9237142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 9247142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 9257142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 9267142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 927a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 9285b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 9295ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 9307142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 9317142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 9327142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 9337142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 9348bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 9358bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 9368bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 9375ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2) 9385ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 939f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 9405ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3) 9415ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 942a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 943a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 944a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 945a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 946a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 947a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 948a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 949c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); 950140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (ScratchReg == 0) 951140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // No register is "free". Scavenge a register. 952140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II); 9531b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, 954a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 9551b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 956a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 9577bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 9587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 959140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengstatic unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 960140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 961140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int Offset = 0; 962140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 963140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int FixedOff = -FFI->getObjectOffset(i); 964140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FixedOff > Offset) Offset = FixedOff; 965140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 966140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 967140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset += FFI->getObjectSize(i); 968140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Align = FFI->getObjectAlignment(i); 969140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Adjust to alignment boundary 970140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset = (Offset+Align-1)/Align*Align; 971140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 972140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return (unsigned)Offset; 973140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 974140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 975140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengvoid 976140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 977140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RegScavenger *RS) const { 97875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 97975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 98075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 981a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 98275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 983a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 984a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 985a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 986a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 987a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 988f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 98975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 99075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 99175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 99275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 99375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 99475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 99575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 99675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 99775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 998f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 99975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 100075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 100175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 100275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 100375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 100475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 100575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 100675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 1007a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1008a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 100975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 1010a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 101175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 101275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 101375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 101475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 1015c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1016c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 1017c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 1018c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else 1019c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng CS1Spilled = true; 1020c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1021c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1022c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 102375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 102475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 102575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 102675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 102775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 102875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 102975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 103075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 103175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 103275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 103375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 103475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 103575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 103675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 103775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 1038c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1039c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 1040c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1041c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1042c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 104375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 104475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 104575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 104675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 104775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 104875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 104975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 105075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 105175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 105275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 105375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 1054a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1055a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1056a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1057a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1058a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1059d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 1060d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 1061d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 1062f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // Force LR to be spilled if the Thumb function size is > 2048. This enables 1063d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 1064f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // then the branch fix up path will undo it. 1065d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 1066d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 1067d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 1068d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1069d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1070d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 1071140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng bool ExtraCSSpill = false; 10727588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 107375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 1074a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1075a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1076a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1077a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 1078a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(ARM::LR, true); 1079f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1080a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 1081a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1082a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1083d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 1084140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ExtraCSSpill = true; 1085a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1086a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 10873548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 10883548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 10897588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 10903548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng MF.changePhyRegUsed(FramePtr, true); 10913548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 10923548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 10933548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1094c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng // If stack and double are 8-byte aligned and we are spilling an odd number 1095a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of GPRs. Spill one extra callee save GPR so we won't have to pad between 1096a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // the integer and double callee save areas. 1097a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1098a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1099f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1100f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng unsigned Reg = UnspilledCS1GPRs.front(); 1101f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng MF.changePhyRegUsed(Reg, true); 1102f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 1103140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) 1104140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ExtraCSSpill = true; 1105f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng } else if (!UnspilledCS2GPRs.empty()) { 1106f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng unsigned Reg = UnspilledCS2GPRs.front(); 1107f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng MF.changePhyRegUsed(Reg, true); 1108f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 1109140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) 1110140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ExtraCSSpill = true; 1111140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1112140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1113140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 1114140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Estimate if we might need to scavenge a register at some point in order 1115140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // to materialize a stack offset. If so, either spill one additiona 1116140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // callee-saved register or reserve a special spill slot to facilitate 1117140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // register scavenging. 1118140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) { 1119140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng MachineFrameInfo *MFI = MF.getFrameInfo(); 1120140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Size = estimateStackSize(MF, MFI); 1121140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Limit = (1 << 12) - 1; 1122140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) 1123140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) { 1124140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) 1125140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (I->getOperand(i).isFrameIndex()) { 1126140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Opcode = I->getOpcode(); 1127140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 1128140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1129140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (AddrMode == ARMII::AddrMode3) { 1130140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Limit = (1 << 8) - 1; 1131140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng goto DoneEstimating; 1132140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else if (AddrMode == ARMII::AddrMode5) { 1133140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Limit = ((1 << 8) - 1) * 4; 1134140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng goto DoneEstimating; 1135140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1136140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1137140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1138140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng DoneEstimating: 1139140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (Size >= Limit) { 1140140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // If any non-reserved CS register isn't spilled, just spill one or two 1141140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // extra. That should take care of it! 1142140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned NumExtras = TargetAlign / 4; 1143140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng SmallVector<unsigned, 2> Extras; 1144140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng while (NumExtras && !UnspilledCS1GPRs.empty()) { 1145140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS1GPRs.back(); 1146140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS1GPRs.pop_back(); 1147140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1148140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Extras.push_back(Reg); 1149140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng NumExtras--; 1150140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1151140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1152140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng while (NumExtras && !UnspilledCS2GPRs.empty()) { 1153140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS2GPRs.back(); 1154140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS2GPRs.pop_back(); 1155140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1156140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Extras.push_back(Reg); 1157140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng NumExtras--; 1158140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1159140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1160140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (Extras.size() && NumExtras == 0) { 1161140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1162140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng MF.changePhyRegUsed(Extras[i], true); 1163140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng AFI->setCSRegisterIsSpilled(Extras[i]); 1164140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1165140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else { 1166140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Reserve a slot closest to SP or frame pointer. 1167140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetRegisterClass *RC = &ARM::GPRRegClass; 1168140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1169140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RC->getAlignment())); 1170140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1171f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng } 1172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 117478268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 1175d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 1176d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng MF.changePhyRegUsed(ARM::LR, true); 1177f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1178f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setLRIsSpilledForFarJump(true); 1179d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1181a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 1183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 1184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 1185a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1191a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 119575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1196a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1197a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1198a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 119975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1200970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 120275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 120375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 12177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12187bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1219355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 122044819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1221355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1228355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1229236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 12308bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 12318bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 12328bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 12338bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 12348bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 12358bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 12368bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 12378bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 12388bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1239236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1240236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1241236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1242236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1243236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1247a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1248acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1249acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (VARegSaveSize) 1250acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII); 1251acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1252236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1253236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 1254236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1255236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1256236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1257236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1258236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1259236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1260236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1261236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1262236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1263236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1264236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1265236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1266236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1267236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1268236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1269236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1270236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1271236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1272236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1273236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1274236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1275236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1276236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1277236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1278236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1279236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1280236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1281236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1282a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1285236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1286236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1287236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1288236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1289a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1290236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1292236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Align == 8 && (GPRCS1Size & 7) != 0) 1293236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Pad CS1 to ensure proper alignment. 1294236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1295c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 1296236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1297236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1298236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII); 1299236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1300236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1301236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 13033548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 13043548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 13053548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 1306236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr) 1307236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 1308a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1309236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1310236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1311236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII); 1312a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1313236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1314236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 1315236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII); 1316a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 13177ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1318a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1319236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1320236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1321236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1322236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1323236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1324236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1325236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1326a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1327236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1328236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1329236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1330236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1331236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 1332a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1333236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 133415f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1335a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1336a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1337a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1338a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 13397ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1340a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1341a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1342a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1343a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1344a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1345a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1346a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1347a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1348a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1349a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 13508e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1351a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1352a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 13537bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 13547bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 13557bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 13567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock &MBB) const { 1357355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1358a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1359a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1360a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1361355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1362355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1363355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1364a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1365a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1366a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1367a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1368236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1369236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 13703df62bde9b3f2557cccfa1f18d25b57bf0477f60Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 13719d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 1372acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Unwind MBBI to point to first LDR / FLDD. 1373acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio const unsigned *CSRegs = getCalleeSavedRegs(); 1374acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI != MBB.begin()) { 1375acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio do 1376acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio --MBBI; 1377acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1378acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (!isCSRestore(MBBI, CSRegs)) 1379acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio ++MBBI; 1380acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1381acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1382acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of FP callee save spill area. 1383acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1384acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getGPRCalleeSavedArea2Size() + 1385acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize()); 1386acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (isThumb) { 1387acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (hasFP(MF)) { 1388acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1389acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1390acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1391236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1392acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 1393236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 1394acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::SP).addReg(FramePtr); 1395acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1396acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI->getOpcode() == ARM::tBX_RET && 1397acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio &MBB.front() != MBBI && 1398acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio prior(MBBI)->getOpcode() == ARM::tPOP) { 1399acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio MachineBasicBlock::iterator PMBBI = prior(MBBI); 1400acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII); 1401acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else 1402acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 1403acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1404acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1405acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Darwin ABI requires FP to point to the stack slot that contains the 1406acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // previous FP. 14079f8e50d4ed7dcc5ca0f137830ff1185b2afa38bfDale Johannesen if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) { 1408acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1409acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1410acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1411acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (AFI->getGPRCalleeSavedArea2Size() || 1412acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize() || 1413acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 1414acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio hasFP(MF)) 1415acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (NumBytes) 1416acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 1417acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio .addImm(NumBytes); 1418acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio else 1419acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr); 1420acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else if (NumBytes) { 1421acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, NumBytes, false, TII); 1422acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 14233548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1424acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 2. 1425acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 1426acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII); 1427236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1428acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 1. 1429acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 1430acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII); 1431236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1432acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to SP upon entry to the function. 1433acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 1434acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII); 1435acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1436a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1437236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 14389d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1439f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1440f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1441f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1442f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1443f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1444236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII); 1445f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1446f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1447f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1448f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1449f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 14509d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 14517bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 14527bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 14537bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1454a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 14557bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 14567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 14577bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1458a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11; 14597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 14607bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 146162819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHExceptionRegister() const { 146262819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception register"); 146362819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 146462819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 146562819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 146662819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHHandlerRegister() const { 146762819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception handler register"); 146862819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 146962819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 147062819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 14717bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 14727bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1473