ARMRegisterInfo.cpp revision 44bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 285ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng#include "llvm/CodeGen/RegisterScavenging.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 30b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 317ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 32b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 35ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng#include "llvm/Support/CommandLine.h" 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 39e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Chengstatic cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging", 40e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::Hidden, 41e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::desc("Enable register scavenging on Thumb")); 42ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng 43a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 76a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 798fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 80a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 8115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 8215f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 8315f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 84a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 86c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 884c6d20a096ad28aa6f812c07a48268e8a6ccb8feLauro Ramos Venancio FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng} 905ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng 91a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 100ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 101ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng unsigned Reg = CSI[i-1].getReg(); 102ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng // Add the callee-saved register as live-in. It's killed at the spill. 103ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MBB.addLiveIn(Reg); 104ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); 105ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng } 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 109a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1179d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1239d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1249d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1259d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1367bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 143ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true) 144a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 146ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true) 14744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL); 148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 149ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true) 15044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL); 151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 153ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true) 15444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL); 155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1577bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1597bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1607bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1617bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1668e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 17044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL); 171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 17344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL); 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 17744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL); 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1797bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1807bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1817bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 18844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (AFI->isThumbFunction()) 18944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg); 19044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng else 19144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg).addReg(SrcReg) 19244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addImm((int64_t)ARMCC::AL); 193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 19444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg) 19544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addImm((int64_t)ARMCC::AL); 196a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 19744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg) 19844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addImm((int64_t)ARMCC::AL); 199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 200a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 2017bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2027bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 203bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize the 204bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// specified immediate. 205bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 206bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator &MBBI, 20744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned DestReg, ARMCC::CondCodes Pred, int Val, 208bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const TargetInstrInfo &TII, bool isThumb) { 209bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineFunction &MF = *MBB.getParent(); 210bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 211bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, Val); 212bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 213bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (isThumb) 214bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx); 215bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng else 216bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx) 21744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addReg(0).addImm(0).addImm((unsigned)Pred); 218bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 219bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 220bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengvoid ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 221bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator I, 222bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned DestReg, 223bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const MachineInstr *Orig) const { 224bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (Orig->getOpcode() == ARM::MOVi2pieces) { 22544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitLoadConstPool(MBB, I, DestReg, 22644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(), 22744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng Orig->getOperand(1).getImmedValue(), 228bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng TII, false); 229bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng return; 230bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng } 231bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 232bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineInstr *MI = Orig->clone(); 233bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MI->getOperand(0).setReg(DestReg); 234bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MBB.insert(I, MI); 235bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 236bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 23740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 23840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 23940984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 24040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 24140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 24240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 24340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 24440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 24540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 24640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 24740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 24840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 24940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 250a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 2569f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::MOVr: { 25744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 26144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addReg(0).addImm(0).addImm(Pred); 262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 264a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 26544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addImm(0).addImm(Pred); 266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 2699f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::tMOVr: { 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 272bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 2738e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 27440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2758e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 279bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 2808e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 28140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2828e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 286a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 287a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 28844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 289a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 29244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addImm(0).addImm(Pred); 293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 29544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI) 29644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addImm(0).addImm(Pred); 297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 298a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 299a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 300a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 30144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 303a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 304a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 30544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addImm(0).addImm(Pred); 306a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 307a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 30844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI) 30944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addImm(0).addImm(Pred); 310a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 311a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 312a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 313a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 314a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 315a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 316a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 317a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 3187bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 3197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 320c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 321c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 322a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 323a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 324a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 325a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 326a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 327a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 328ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 329a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 330a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 331a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 332a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 333a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 334a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 335a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 336a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 337a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 338970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 3390f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3400f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 3410f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 342c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 343c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 344a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 345a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 346a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 347a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 348a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 349a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 350a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 351ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 352c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 3530f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3540f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 355b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 356c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // FIXME: avoid re-calculating this everytime. 357b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 358b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::SP); 359ad78ef215485389bb5c5698fa6f1ac670f0076d8Evan Cheng Reserved.set(ARM::PC); 360b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 361b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(FramePtr); 362b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // Some targets reserve R9. 363b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isR9Reserved()) 364b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::R9); 365b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 366b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 367b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 36836230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Chengbool 369140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { 370140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng switch (Reg) { 371140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng default: break; 372140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::SP: 373140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::PC: 374140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 375140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R7: 376140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R11: 377140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 378140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 379140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng break; 380140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R9: 381140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return STI.isR9Reserved(); 382140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 383140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 384140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return false; 385140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 386140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 387140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengbool 38836230cdda48edf6c634f2dcf69f9d78ac5a17377Evan ChengARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 38936230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 390e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng return ThumbRegScavenging || !AFI->isThumbFunction(); 3911b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng} 3921b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng 393a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 394a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 395a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 396a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 397dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 398a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 399a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 400a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 4015c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 4025c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// not required, we reserve argument space for call sites in the function 4035c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// immediately on entry to the current function. This eliminates the need for 4045c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// add/sub sp brackets around call sites. Returns true if the call frame is 4055c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// included as part of the stack frame. 4065c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Chengbool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { 4075c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 4085c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng unsigned CFSize = FFI->getMaxCallFrameSize(); 4095c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 4105c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // It's not always a good idea to include the call frame as part of the 4115c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // stack frame. ARM (especially Thumb) has small immediate offset to 4125c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // address the stack frame. So a large call frame can cause poor codegen 4135c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // and may even makes it impossible to scavenge a register. 4145c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (AFI->isThumbFunction()) { 4155c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 4165c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return false; 4175c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng } else { 4185c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 4195c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return false; 4205c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng } 4215c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return !hasFP(MF); 4225c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng} 4235c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng 42436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 425a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 426a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 427a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 428a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 429a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 43044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ARMCC::CondCodes Pred, 431a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 432a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 433a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 434a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 435a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 436a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 437a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 438a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 439a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 440a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 441a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 442a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 443a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 444a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 445a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 446a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 447a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 448a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 44944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addReg(BaseReg, false, false, true).addImm(SOImmVal) 45044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addImm((unsigned)Pred); 451a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 452a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 453a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 454a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 45536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 45636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 45736640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 45836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 45936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 46036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 46136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 46236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 46336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 46436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 46536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 46636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 4673d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 1; // Followed by a number of tADDi8. 46836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 46936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 47036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 47136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 47236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 47336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 47436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 47536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 47636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 47736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 47836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 479403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 480403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 481403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 48236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 48336640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 484403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 48536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 48636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 487a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 488a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 4897142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 4907142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 49136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 49236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 493a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 494a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 495a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 496a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 49736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 49836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 49936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 50036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 50136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 50236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 50336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 5049f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12) 5055ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 50636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 507a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 508a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 5099f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 5108bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 5119f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 5125ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) 5135ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(LdReg, false, false, true); 5148bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 51544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitLoadConstPool(MBB, MBBI, LdReg, ARMCC::AL, NumBytes, TII, true); 5167142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 51736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 51836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 51936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 5205ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng if (DestReg == ARM::SP || isSub) 5215ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(BaseReg).addReg(LdReg, false, false, true); 52236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 5235ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(LdReg).addReg(BaseReg, false, false, true); 52436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 5259f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3) 5265ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 52736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 52836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 52936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 531a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 532a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 534a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 535a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 536a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 537a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 538a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 539a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 5418e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 5435b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 54436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 54536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 547a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 548a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 5505b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 551a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 552a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 5545b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 5555b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 5565b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 5575b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 559a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 560a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 561a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 562a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 5635b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 565a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 56636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 56736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 56836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 56936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 5708e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 571a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 572a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 573a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 574a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 575a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 57636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 5778e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 57836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 57936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 58036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 581403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 58236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 58336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 58436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5858e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 58636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 58736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 58836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 58936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 59036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 59136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 5925ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(ThisVal); 59336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 5949f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg) 5955ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true); 59636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 59736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 59836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 59936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 6005b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 601a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 602a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 6035b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 6045b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 605a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 6073fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 608a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 6095ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng bool isKill = BaseReg != ARM::SP; 6105ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg) 6115ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, isKill).addImm(ThisVal); 612a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 613a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 614a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 615a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 616a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 617a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 6195b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 6205b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 621a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 623a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 624a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 626a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 627a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 6285ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg) 6295ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true) 630a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 631a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 632a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 633a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 634a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 63544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ARMCC::CondCodes Pred, int NumBytes, bool isThumb, 63644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng const TargetInstrInfo &TII) { 637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 638a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 639a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 64044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, Pred, NumBytes, TII); 641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 6437bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 6447bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 6457bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 6465c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (!hasReservedCallFrame(MF)) { 647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 649a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 650b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 651b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 652b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 653a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 655a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 656a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 657b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 658b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 659b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 660a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 66144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Opc = Old->getOpcode(); 66244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng bool isThumb = AFI->isThumbFunction(); 66344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ARMCC::CondCodes Pred = isThumb 66444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue(); 66544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 66644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, I, Pred, -Amount, isThumb, TII); 667b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 66844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 66944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, I, Pred, Amount, isThumb, TII); 670b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 671b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 6727ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 6737bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 6747bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 6757bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 676a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 677a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 678a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 679a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 687a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 6889f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); 689a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 690a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 6925ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg) 6935ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true); 694a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 696c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// findScratchRegister - Find a 'free' ARM register. If register scavenger 697c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// is not being used, R12 is available. Otherwise, try for a call-clobbered 698c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// register first and then a spilled callee-saved register if that fails. 699c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengstatic 700c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengunsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 701c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng ARMFunctionInfo *AFI) { 702c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12; 703c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng if (Reg == 0) 704c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // Try a already spilled CS register. 705c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters()); 706c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 707c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng return Reg; 708c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng} 709c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 7101b051fc6a491c40cf3f926c089ad082938b653f0Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 71197de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng int SPAdj, RegScavenger *RS) const{ 712a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 71358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 71458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 71558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 716a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 717a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 71858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 721a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 725a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 726a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 72797de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng MF.getFrameInfo()->getStackSize() + SPAdj; 72858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 729a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 730a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 731a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 732a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 733a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 734a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 73575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 73697de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng assert(SPAdj == 0 && "Unexpected"); 737a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 738a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 739a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 740b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 741a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 745a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 746a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 7473d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 748a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 750a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 751a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 7529f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVr)); 753a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 754a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 755a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 756a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 757a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 758a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 759a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 760a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 76158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 762a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 763a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 764a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 768a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 769a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 770a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 772a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 773a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 774a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 775b03eacdbf39b37a98b65b936046b22cca8215d8dEvan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 776a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 777a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 778a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 779a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 780a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 781a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 782a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 783a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 784a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 785a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 7863d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 7873d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng // Can't use tADDrSPi if it's based off the frame pointer. 7883d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumBits = 0; 7893d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Scale = 1; 7903d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (FrameReg != ARM::SP) { 7913d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Opcode = ARM::tADDi3; 7923d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDi3)); 7933d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 3; 7943d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } else { 7953d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 8; 7963d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 4; 7973d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng assert((Offset & 3) == 0 && 7983d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 7993d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } 8003d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 801a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 802a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 8039f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVr)); 804a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 805a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 806a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 807a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 808a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 809a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 8103d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Mask = (1 << NumBits) - 1; 8113d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (((Offset / Scale) & ~Mask) == 0) { 812a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 813a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 8143d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset / Scale); 815a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 816a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 817a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 818a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 819a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 8203d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale); 821a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 822a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 823a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 82488b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 825a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 826a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 827a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 828a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 829a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 830a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 831a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 832a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 833a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 8343d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Mask); 8353d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Offset = (Offset - Mask * Scale); 836a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 837a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 838a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 839a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 840a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 841a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 842a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 843a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 8445ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); 845a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 846a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 847a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 848a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 849a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 850a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 851a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 852a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 853a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 854a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 855a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 856a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 857a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 858a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 859a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 860a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 861a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 862a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 863a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 864a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 865a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 866a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 867a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 868a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 869a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 870a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 871a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 872a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 873a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 874a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 875a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 876a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 877a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 878a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 879a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 880a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 881a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 8827142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 8837142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 884a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 885a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 886a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 8878fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 888a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 889a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 890a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 89158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 892a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 8939312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 894a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 895a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 896a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 897a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 89858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 899a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 9008e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 9018e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 9028e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 9038e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 9048e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 9058e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 9068e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 9078e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 9088e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 9098e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 9108e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 91188b633165a20398d1015eec561856500fcf30d7dEvan Cheng 9125ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 9135ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 9145ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 9155ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 9165ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 9175ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 9185ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 919a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 920a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 9215ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 9225ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 9235ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 92488b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 92588b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 926a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 927a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 928a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 92988b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 930a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 931a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 932a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 933a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 934a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 935a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 936a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 93758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 938a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 939a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 940a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 941a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 9427142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 9437142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 9447142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 945403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 9467142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 94744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitLoadConstPool(MBB, II, TmpReg, ARMCC::AL, Offset, TII, true); 9487142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 9497142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 9507142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 951a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 9525b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 9535ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 9547142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 9557142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 9567142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 9575ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 958a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 959a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 960a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 961a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 962a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 963a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 964a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 9658bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 966a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 9675b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 968a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 9697142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 9705b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 9719f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 9725ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R2, false, false, true); 973a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 974a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 975f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 9769f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 9775ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 9787142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 9797142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 980403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 9817142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 98244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitLoadConstPool(MBB, II, TmpReg, ARMCC::AL, Offset, TII, true); 9837142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 9847142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 9857142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 986a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 9875b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 9885ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 9897142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 9907142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 9917142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 9927142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 9938bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 9948bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 9958bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 9969f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2) 9975ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 998f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 9999f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3) 10005ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 1001a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 1002a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 1003a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 1004a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 1005a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 1006a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 1007a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 1008c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); 1009140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (ScratchReg == 0) 1010140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // No register is "free". Scavenge a register. 101197de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); 101244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng MachineOperand *MO = MI.findFirstPredOperand(); 101344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ARMCC::CondCodes Pred = MO ? 101444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng (ARMCC::CondCodes)MO->getImmedValue() : ARMCC::AL; 101544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, Pred, 1016a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 10171b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1018a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 10197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 10207bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1021140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengstatic unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 1022140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 1023140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int Offset = 0; 1024140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 1025140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int FixedOff = -FFI->getObjectOffset(i); 1026140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FixedOff > Offset) Offset = FixedOff; 1027140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1028140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 1029140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset += FFI->getObjectSize(i); 1030140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Align = FFI->getObjectAlignment(i); 1031140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Adjust to alignment boundary 1032140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset = (Offset+Align-1)/Align*Align; 1033140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1034140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return (unsigned)Offset; 1035140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 1036140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 1037140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengvoid 1038140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1039140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RegScavenger *RS) const { 104075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 104175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 104275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 1043a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 104475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 1045a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 1046a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 1047a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 1048a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 1049a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 1050f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 105175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 105275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 105375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 105475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 105575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 105675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 105775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 105875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 105975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 1060f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 106175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 106275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 106375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 106475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 106575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 106675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 106775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 106875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 1069a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1070a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 107175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 1072a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 107375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 107475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 107575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 107675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 1077c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1078c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 1079c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 1080356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio CS1Spilled = true; 1081c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1082c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1083c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 108475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 108575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 108675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 108775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 108875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 108975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 109075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 109175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 109275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 109375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 109475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 109575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 109675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 109775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 109875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 1099c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1100c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 1101c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1102c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1103c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 110475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 110575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 110675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 110775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 110875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 110975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 111075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 111175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 111275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 111375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 111475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 1115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1120d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 1121d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 1122d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 1123f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // Force LR to be spilled if the Thumb function size is > 2048. This enables 1124d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 1125f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // then the branch fix up path will undo it. 1126d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 1127d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 1128d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 1129d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1130d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1131d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 1132140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng bool ExtraCSSpill = false; 11337588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 113475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 1135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1138a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 11396c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(ARM::LR); 1140f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 1142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1143a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1144d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 1145140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ExtraCSSpill = true; 1146a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1147a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 11483548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 11493548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 11507588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 11516c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(FramePtr); 11523548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 11533548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 11543548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1155356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // If stack and double are 8-byte aligned and we are spilling an odd number 1156356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // of GPRs. Spill one extra callee save GPR so we won't have to pad between 1157356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // the integer and double callee save areas. 1158356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1159356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1160356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1161356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1162356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned Reg = UnspilledCS1GPRs[i]; 1163356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // Don't spiil high register if the function is thumb 1164356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) { 1165356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Reg); 1166356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Reg); 1167356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!isReservedReg(MF, Reg)) 1168356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio ExtraCSSpill = true; 1169356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio break; 1170356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1171356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1172356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } else if (!UnspilledCS2GPRs.empty() && 1173356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio !AFI->isThumbFunction()) { 1174356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned Reg = UnspilledCS2GPRs.front(); 1175356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Reg); 1176356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Reg); 1177356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!isReservedReg(MF, Reg)) 1178356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio ExtraCSSpill = true; 1179356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1180356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1181356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio 1182140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Estimate if we might need to scavenge a register at some point in order 1183140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // to materialize a stack offset. If so, either spill one additiona 1184140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // callee-saved register or reserve a special spill slot to facilitate 1185140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // register scavenging. 1186140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) { 1187140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng MachineFrameInfo *MFI = MF.getFrameInfo(); 1188140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Size = estimateStackSize(MF, MFI); 1189140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Limit = (1 << 12) - 1; 1190140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) 1191140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) { 1192140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) 1193140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (I->getOperand(i).isFrameIndex()) { 1194140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Opcode = I->getOpcode(); 1195140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 1196140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1197140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (AddrMode == ARMII::AddrMode3) { 1198140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Limit = (1 << 8) - 1; 1199140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng goto DoneEstimating; 1200140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else if (AddrMode == ARMII::AddrMode5) { 12015c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng unsigned ThisLimit = ((1 << 8) - 1) * 4; 12025c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (ThisLimit < Limit) 12035c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng Limit = ThisLimit; 1204140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1205140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1206140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1207140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng DoneEstimating: 1208140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (Size >= Limit) { 1209140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // If any non-reserved CS register isn't spilled, just spill one or two 1210140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // extra. That should take care of it! 1211356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned NumExtras = TargetAlign / 4; 1212356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio SmallVector<unsigned, 2> Extras; 1213356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio while (NumExtras && !UnspilledCS1GPRs.empty()) { 1214140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS1GPRs.back(); 1215140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS1GPRs.pop_back(); 1216140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1217356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio Extras.push_back(Reg); 1218356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio NumExtras--; 1219140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1220140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1221356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio while (NumExtras && !UnspilledCS2GPRs.empty()) { 1222140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS2GPRs.back(); 1223140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS2GPRs.pop_back(); 1224140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1225356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio Extras.push_back(Reg); 1226356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio NumExtras--; 1227140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1228140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1229356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (Extras.size() && NumExtras == 0) { 1230356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1231356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Extras[i]); 1232356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Extras[i]); 1233356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1234140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else { 1235140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Reserve a slot closest to SP or frame pointer. 1236140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetRegisterClass *RC = &ARM::GPRRegClass; 1237140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1238140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RC->getAlignment())); 1239140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1240f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng } 1241a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1242a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 124378268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 1244d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 12456c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(ARM::LR); 1246f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1247f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setLRIsSpilledForFarJump(true); 1248d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1249a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 1252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 1253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 1254a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1261a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 126475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1265a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 126875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1269970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 127175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 127275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1274a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1280a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1281a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1282a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 12867bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12877bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1288355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 128944819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1290355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1296355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1297236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 12988bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 12998bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 13008bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 13018bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 13028bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 13038bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 13048bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 13058bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 13068bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1307236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1308236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1309236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1310236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1311236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1312a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1313a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1314a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1315a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1316acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1317acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (VARegSaveSize) 131844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, -VARegSaveSize, isThumb, TII); 1319acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1320236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1321236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 132244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, -NumBytes, isThumb, TII); 1323236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1324236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1325236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1326236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1327236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1328236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1329236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1330236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1331236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1332236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1333236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1334236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1335236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1336236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1337236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1338236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1339236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1340236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1341236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1342236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1343236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1344236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1345236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1346236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1347236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1348236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1349236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1350a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1351a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1352a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1353236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1354236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1355236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1356236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1357a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1358236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1359a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1360236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1361236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 136244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, -GPRCS1Size, isThumb, TII); 1363236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1364236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1365236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1366a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 13673548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 13683548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 136944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 137044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng MachineInstrBuilder MIB = 137144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr) 1372236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 137344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (!isThumb) MIB.addImm(ARMCC::AL); 137444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng } 1375a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1376236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1377236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 137844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, -GPRCS2Size, false, TII); 1379a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1380236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1381236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 138244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, -DPRCSSize, false, TII); 1383a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 13847ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1385a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1386236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1387236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1388236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1389236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1390236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1391236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1392236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1393a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1394236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1395236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1396236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1397236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1398236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 139944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, -NumBytes, isThumb, TII); 1400236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 140115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1402e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio if(STI.isTargetELF() && hasFP(MF)) { 1403e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1404e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio AFI->getFramePtrSpillOffset()); 1405e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio } 1406e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio 1407a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1409a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1410a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 14117ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1412a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1413a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1414a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1415a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1416a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1417a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1418a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1419a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1420a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1421a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 14228e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1423a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 14257bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 14267bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 14277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 1428bed2946a96ecb15b0b636fa74cb26ce61b1c648eAnton Korobeynikov MachineBasicBlock &MBB) const { 1429355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1430a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1431a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1432a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1433355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1434355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1435355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1436a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1437a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1438a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1439a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1440236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1441236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 144244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, isThumb, TII); 14439d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 1444acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Unwind MBBI to point to first LDR / FLDD. 1445acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio const unsigned *CSRegs = getCalleeSavedRegs(); 1446acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI != MBB.begin()) { 1447acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio do 1448acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio --MBBI; 1449acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1450acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (!isCSRestore(MBBI, CSRegs)) 1451acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio ++MBBI; 1452acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1453acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1454acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of FP callee save spill area. 1455acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1456acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getGPRCalleeSavedArea2Size() + 1457acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize()); 1458acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (isThumb) { 1459acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (hasFP(MF)) { 1460acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1461acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1462acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1463236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1464acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 1465236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 14669f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); 1467acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1468acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI->getOpcode() == ARM::tBX_RET && 1469acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio &MBB.front() != MBBI && 1470acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio prior(MBBI)->getOpcode() == ARM::tPOP) { 1471acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio MachineBasicBlock::iterator PMBBI = prior(MBBI); 147244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, PMBBI, ARMCC::AL, NumBytes, isThumb, TII); 1473acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else 147444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, isThumb, TII); 1475acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1476acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1477acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Darwin ABI requires FP to point to the stack slot that contains the 1478acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // previous FP. 14799f8e50d4ed7dcc5ca0f137830ff1185b2afa38bfDale Johannesen if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) { 1480acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1481acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1482acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1483acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (AFI->getGPRCalleeSavedArea2Size() || 1484acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize() || 1485acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 1486acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio hasFP(MF)) 1487acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (NumBytes) 1488acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 148944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addImm(NumBytes).addImm((unsigned)ARMCC::AL); 1490acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio else 149144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr) 149244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addImm((unsigned)ARMCC::AL); 1493acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else if (NumBytes) { 149444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, false, TII); 1495acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 14963548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1497acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 2. 1498acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 149944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getDPRCalleeSavedAreaSize(), 150044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1501236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1502acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 1. 1503acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 150444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getGPRCalleeSavedArea2Size(), 150544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1506236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1507acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to SP upon entry to the function. 1508acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 150944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getGPRCalleeSavedArea1Size(), 151044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1511acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1512a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1513236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 15149d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1515f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1516f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1517f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1518f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1519f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 152044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitSPUpdate(MBB, MBBI, ARMCC::AL, VARegSaveSize, isThumb, TII); 1521f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1522f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1523f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1524f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1525f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 15269d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 15277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 15287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 15297bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 15317bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 15327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 15337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1534267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio if (STI.isTargetDarwin() || hasFP(MF)) 15354c6d20a096ad28aa6f812c07a48268e8a6ccb8feLauro Ramos Venancio return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11; 1536267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio else 1537267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio return ARM::SP; 15387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 15397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 154062819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHExceptionRegister() const { 154162819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception register"); 154262819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 154362819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 154462819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 154562819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHHandlerRegister() const { 154662819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception handler register"); 154762819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 154862819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 154962819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 15507bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 15517bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1552