ARMRegisterInfo.cpp revision 58421d7d0847bbb5f4cc95c647726d55c45582c0
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 167bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineInstrBuilder.h" 187bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFunction.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 207bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/Type.h" 227bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 237bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include <iostream> 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 257bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 267bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaARMRegisterInfo::ARMRegisterInfo() 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) { 287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 297bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 307bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 317bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola // On the order of operands here: think "[FI + 0] = SrcReg". 357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola assert (RC == ARM::IntRegsRegisterClass); 367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola BuildMI(MBB, I, ARM::str, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg); 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 407bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 437bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola assert (RC == ARM::IntRegsRegisterClass); 447bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola BuildMI(MBB, I, ARM::ldr, 2, DestReg).addFrameIndex(FI).addImm(0); 457bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 487bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I, 497bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, unsigned SrcReg, 507bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 517bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola assert (RC == ARM::IntRegsRegisterClass); 52dc124a234a02ea6fc1061a51ade1bb7b817ddb61Rafael Espindola BuildMI(MBB, I, ARM::movrr, 1, DestReg).addReg(SrcReg); 537bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 547bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 557bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI, 567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned OpNum, 577bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola int FI) const { 587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola return NULL; 597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 607bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 610f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst unsigned* ARMRegisterInfo::getCalleeSaveRegs() const { 620f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng static const unsigned CalleeSaveRegs[] = { 0 }; 630f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng return CalleeSaveRegs; 640f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 650f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 660f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 670f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan ChengARMRegisterInfo::getCalleeSaveRegClasses() const { 680f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 }; 690f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng return CalleeSaveRegClasses; 700f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 710f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 727bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 737bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 747bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 757bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 767bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 777bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 787bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid 797bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 8058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 8158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 8258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 8358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 8458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola assert (MI.getOpcode() == ARM::movrr); 8558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 8658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola unsigned FrameIdx = 1; 8758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 8858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex(); 8958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 9058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 9158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 9258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola unsigned StackSize = MF.getFrameInfo()->getStackSize(); 9358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 9458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola Offset += StackSize; 9558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 9658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola // Insert a set of r12 with the full address 9758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola // r12 = r13 + offset 9858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock *MBB2 = MI.getParent(); 9958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset); 10058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 10158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola // Replace the FrameIndex with r12 10258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12); 1037bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1047bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1057bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1067bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaprocessFunctionBeforeFrameFinalized(MachineFunction &MF) const {} 1077bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1087bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1097bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 1127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock &MBB) const { 1137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1167bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola return ARM::R14; 1177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1187bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1207bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola return ARM::R13; 1217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1227bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1237bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 1247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 125