ARMRegisterInfo.cpp revision 5ef9226f30d0615558cdfc6a2b76c7a914a8e32f
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 285ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng#include "llvm/CodeGen/RegisterScavenging.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 30b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 317ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 32b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 35ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng#include "llvm/Support/CommandLine.h" 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 39ead75905813e175898677cb8c4e4cc919ad2782dEvan Chengstatic cl::opt<bool> EnableScavenging("enable-arm-reg-scavenging", cl::Hidden, 40ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng cl::desc("Enable register scavenging on ARM")); 41ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng 42a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 43a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 76a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 788fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 79a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 8015f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 8115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 8215f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 83a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 84a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 85c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 86a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) { 885ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng RS = new RegScavenger(); 895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng} 905ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng 915ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan ChengARMRegisterInfo::~ARMRegisterInfo() { 925ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng delete RS; 935ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng} 945ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng 955ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan ChengRegScavenger *ARMRegisterInfo::getRegScavenger() const { 965ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng return EnableScavenging ? RS : NULL; 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 105a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 108ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 109ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng unsigned Reg = CSI[i-1].getReg(); 110ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng // Add the callee-saved register as live-in. It's killed at the spill. 111ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MBB.addLiveIn(Reg); 112ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); 113ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng } 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 117a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 123a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 124a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1259d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1319d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1329d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1339d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 134a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 138a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1437bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1447bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1457bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 147a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 151ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true) 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 154ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true) 155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 157ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true) 158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 161ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true) 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1647bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1657bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1667bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1677bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1687bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1697bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 170a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1748e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 181a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1877bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1887bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1897bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 191a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 196a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr), 197a8e2989ece6dc46df59b0768184028257f913843Evan Cheng DestReg).addReg(SrcReg); 198a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 199c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); 200a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 201c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg); 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 2047bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2057bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 20640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 20740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 20840984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 20940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 21040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 21140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 21240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 21340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 21440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 21540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 21640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 21740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 21840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 219a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::MOVrr: { 226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(0).addImm(0); 230a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 236a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::tMOVrr: { 238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 239a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 240bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 2418e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 24240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2438e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 247bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 2488e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 24940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2508e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 261a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0); 263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 264a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 265a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0); 274a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 280a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 281a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 2827bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2837bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 284c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 285c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 286a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 287a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 288a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 289a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 292ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 298a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 299a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 300a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 301a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 302970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 3030f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3040f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 3050f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 306c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 307c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 308a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 309a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 310a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 311a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 312a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 313a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 314a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 315ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 316c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 3170f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3180f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 319b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 320b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 321b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::SP); 322b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 323b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(FramePtr); 324b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // Some targets reserve R9. 325b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isR9Reserved()) 326b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::R9); 327b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // At PEI time, if LR is used, it will be spilled upon entry. 328b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR)) 329b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::LR); 330b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 331b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 332b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 333a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 334a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 335a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 336a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 337dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 338a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 339a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 340a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 34136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 342a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 343a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 344a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 345a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 346a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 347a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 348a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 349a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 350a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 351a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 352a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 353a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 354a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 355a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 356a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 357a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 358a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 359a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 360a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 361a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 362a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 363a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 364a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 3655ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(SOImmVal); 366a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 367a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 368a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 369a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 37036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 37136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 37236640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 37336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 37436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 37536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 37636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 37736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 37836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 37936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 38036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 38136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 38236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Scale = 1; 38336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 38436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 38536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 38636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 38736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 38836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 38936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 39036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 39136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 39236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 39336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 3947142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize NumBytes 3957142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// immediate. 3967142f8755a07512d909d288f74a3f1ffa9c1411aEvan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 3977142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineBasicBlock::iterator &MBBI, 3987142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned DestReg, int NumBytes, 3997142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng const TargetInstrInfo &TII) { 4007142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineFunction &MF = *MBB.getParent(); 4017142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 4027142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes); 4037142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 4047142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx); 4057142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng} 4067142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 407403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 408403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 409403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 41036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 41136640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 412403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 41336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 41436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 415a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 416a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 4177142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 4187142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 41936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 42036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 421a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 422a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 423a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 424a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 42536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 42636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 42736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 42836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 42936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 43036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 43136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 4325ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12) 4335ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 43436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 435a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 436a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 437a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4388bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 4398bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4405ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) 4415ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(LdReg, false, false, true); 4428bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 4437142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII); 4447142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 44536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 44636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 44736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 4485ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng if (DestReg == ARM::SP || isSub) 4495ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(BaseReg).addReg(LdReg, false, false, true); 45036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 4515ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(LdReg).addReg(BaseReg, false, false, true); 45236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 4535ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3) 4545ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 45536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 45636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 45736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 458a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 459a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 460a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 461a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 462a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 463a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 464a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 465a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 466a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 467a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 468a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 4698e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 470a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 4715b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 47236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 47336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 474a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 475a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 476a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 477a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 4785b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 479a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 480a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 481a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 4825b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 4835b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 4845b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 4855b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 486a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 487a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 488a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 489a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 490a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 4915b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 492a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 493a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 49436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 49536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 49636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 49736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 4988e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 499a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 500a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 501a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 502a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 503a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 50436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 5058e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 50636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 50736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 50836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 509403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 51036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 51136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 51236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5138e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 51436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 51536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 51636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 51736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 51836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 51936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 5205ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(ThisVal); 52136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 5225ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg) 5235ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true); 52436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 52536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 52636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 52736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5285b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 529a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 5315b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 5325b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 534a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 5353fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 536a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 5375ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng bool isKill = BaseReg != ARM::SP; 5385ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg) 5395ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, isKill).addImm(ThisVal); 540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 541a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 5475b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 5485b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 550a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 551a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 552a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 554a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 555a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 5565ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg) 5575ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true) 558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 559a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 560a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 561a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 562a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 563a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, bool isThumb, const TargetInstrInfo &TII) { 564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 565a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 566a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 567a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 568a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 569a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5707bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 5717bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 5727bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 57375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (hasFP(MF)) { 574a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 575a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 576a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 577b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 578b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 579b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 580a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 582a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 583a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 584b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 585b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 586b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 587a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 588b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) { 589a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII); 590b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 591b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola assert(Old->getOpcode() == ARM::ADJCALLSTACKUP); 592a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII); 593b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 594b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 5957ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 5967bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 5977bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 5987bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 599a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 600a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 601a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 602a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 603a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 604a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 605a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 607a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 608a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 609a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 610a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 611a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal); 612a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 613a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 614a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 6155ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg) 6165ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true); 617a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 619a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 620a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 62158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 62258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 62358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 624a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 62658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 627a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 628a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 629a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 630a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 631a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 632a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 633a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 634a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 635a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.getFrameInfo()->getStackSize(); 63658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 638a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 639a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 64375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 644a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 645a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 647b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 649a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 650a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 651a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 653a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 655a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 656a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 657a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVrr)); 660a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 661a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 662a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 663a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 665a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 666a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 66858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 669a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 670a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 672a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 673a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 674a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 675a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 676a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 677a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 679a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31); 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 687a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 688a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 689a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 690a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 692a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 693a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((Offset & 3) == 0 && 69486eb5153594b523e0b201735e14c92785d7ba601Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 696a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVrr)); 698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 700a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 701a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 702a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 703a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 704a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (((Offset >> 2) & ~255U) == 0) { 705a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 706a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 707a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset >> 2); 708a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 709a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 710a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 711a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 712a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 713a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, 8, 1); 714a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 715a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 716a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 71788b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 718a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 719a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 720a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 721a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 725a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 726a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 727a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(255); 728a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng Offset = (Offset - 255 * 4); 729a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 730a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 731a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 732a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 733a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 734a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 735a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 736a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 7375ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); 738a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 739a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 740a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 741a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 745a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 746a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 747a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 748a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 750a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 751a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 752a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 753a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 754a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 755a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 756a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 757a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 758a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 759a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 760a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 761a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 762a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 763a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 764a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 768a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 769a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 770a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 772a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 773a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 774a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 7757142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 7767142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 777a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 778a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 779a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 7808fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 781a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 782a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 783a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 78458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 785a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 7869312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 787a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 788a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 789a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 790a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 79158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 792a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 7938e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 7948e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 7958e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 7968e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 7978e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 7988e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 7998e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 8008e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 8018e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 8028e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 8038e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 80488b633165a20398d1015eec561856500fcf30d7dEvan Cheng 8055ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 8065ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 8075ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 8085ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 8095ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 8105ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 8115ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 812a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 813a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 8145ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 8155ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 8165ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 81788b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 81888b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 819a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 820a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 821a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 82288b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 823a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 824a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 825a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 826a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 827a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 828a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 829a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 83058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 831a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 832a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 833a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 834a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 8357142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 8367142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 8377142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 838403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 8397142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 8407142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 8417142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 8427142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 8437142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 844a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8455b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 8465ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 8477142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 8487142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 8497142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 8505ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 851a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 852a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 853a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 854a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 855a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 856a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 857a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 8588bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 859a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 8605b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 861a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 8627142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 8635b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 8645ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12) 8655ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R2, false, false, true); 866a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 867a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 8688bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn()) 8695ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12) 8705ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 8717142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 8727142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 873403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 8747142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 8757142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 8767142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 8777142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 8787142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 879a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8805b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 8815ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 8827142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 8837142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 8847142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 8857142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 8868bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 8878bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 8888bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 8895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2) 8905ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 8918bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn()) 8925ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3) 8935ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 894a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 895a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 896a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 897a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 898a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 899a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 900a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 901a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg, 902a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 9035ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(ARM::R12, false, false, true); 904a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 9057bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 9067bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 9077bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 908a8e2989ece6dc46df59b0768184028257f913843Evan ChengprocessFunctionBeforeCalleeSavedScan(MachineFunction &MF) const { 90975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 91075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 91175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 912a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 91375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 914a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 915a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 916a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 917a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 918a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 91975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 92075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 92175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 92275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 92375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 92475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 92575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 92675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 92775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 92875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 92975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 93075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 93175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 93275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 93375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 93475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 93575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 936a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 937a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 93875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 939a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 94075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 94175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 94275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 94375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 944c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 945c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 946c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 947c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else 948c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng CS1Spilled = true; 949c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 950c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 951c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 95275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 95375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 95475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 95575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 95675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 95775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 95875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 95975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 96075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 96175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 96275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 96375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 96475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 96575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 96675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 967c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 968c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 969c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 970c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 971c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 97275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 97375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 97475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 97575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 97675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 97775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 97875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 97975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 98075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 98175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 98275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 983a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 984a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 985a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 986a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 987a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 98878268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 989d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 990d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 991d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 992d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // Force LR spill if the Thumb function size is > 2048. This enables the 993d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 994d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // the branch fix up path will undo it. 995d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 996d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 997d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 998d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 999d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1000d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 10017588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 100275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 1003a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1004a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1005a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1006a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 1007a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(ARM::LR, true); 1008a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 1009a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1010a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1011d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 1012a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1013a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 10143548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 10153548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 10167588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 10173548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng MF.changePhyRegUsed(FramePtr, true); 10183548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 10193548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 10203548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1021c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng // If stack and double are 8-byte aligned and we are spilling an odd number 1022a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of GPRs. Spill one extra callee save GPR so we won't have to pad between 1023a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // the integer and double callee save areas. 1024a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1025a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1026a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (CS1Spilled && !UnspilledCS1GPRs.empty()) 1027a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS1GPRs.front(), true); 1028c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else if (!UnspilledCS2GPRs.empty()) 1029a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true); 1030a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1031a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 103278268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 1033d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 1034d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng MF.changePhyRegUsed(ARM::LR, true); 1035d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng AFI->setLRIsForceSpilled(true); 1036d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1037a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1038a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1039a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 1040a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 1041a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 1042a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1043a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1044a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1045a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1046a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1047a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1048a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1049a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1050a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1051a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 105275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1053a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1054a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1055a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 105675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1057970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1058a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 105975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 106075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1061a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1062a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1063a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1064a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1065a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1066a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1067a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1068a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1069a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1070a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1071a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1072a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1073a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 10747bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 10757bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1076355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 107744819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1078355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1079a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1080a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1081a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1082a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1083a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1084a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1085355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1086236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 10878bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 10888bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 10898bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 10908bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 10918bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 10928bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 10938bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 10948bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 10958bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1096236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1097236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1098236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1099236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1100236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1105acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1106acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (VARegSaveSize) 1107acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII); 1108acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1109236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1110236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 1111236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1112236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1113236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1114236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1115236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1116236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1117236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1118236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1119236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1120236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1121236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1122236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1123236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1124236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1125236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1126236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1127236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1128236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1129236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1130236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1131236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1132236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1133236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1134236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1135236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1136236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1137236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1138236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1142236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1143236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1144236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1145236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1146a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1147236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1149236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Align == 8 && (GPRCS1Size & 7) != 0) 1150236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Pad CS1 to ensure proper alignment. 1151236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1152c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 1153236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1154236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1155236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII); 1156236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1157236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1158236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 11603548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 11613548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 11623548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 1163236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr) 1164236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 1165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1166236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1167236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1168236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII); 1169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1170236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1171236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 1172236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII); 1173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 11747ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1176236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1177236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1178236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1179236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1180236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1181236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1182236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1184236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1185236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1186236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1187236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1188236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 1189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1190236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 119115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 11967ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1197a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1198a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1200a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1204a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 12078e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 12107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 12137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock &MBB) const { 1214355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1218355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1219355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1220355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1225236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1226236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 12273df62bde9b3f2557cccfa1f18d25b57bf0477f60Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 12289d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 1229acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Unwind MBBI to point to first LDR / FLDD. 1230acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio const unsigned *CSRegs = getCalleeSavedRegs(); 1231acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI != MBB.begin()) { 1232acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio do 1233acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio --MBBI; 1234acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1235acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (!isCSRestore(MBBI, CSRegs)) 1236acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio ++MBBI; 1237acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1238acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1239acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of FP callee save spill area. 1240acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1241acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getGPRCalleeSavedArea2Size() + 1242acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize()); 1243acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (isThumb) { 1244acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (hasFP(MF)) { 1245acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1246acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1247acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1248236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1249acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 1250236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 1251acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::SP).addReg(FramePtr); 1252acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1253acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI->getOpcode() == ARM::tBX_RET && 1254acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio &MBB.front() != MBBI && 1255acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio prior(MBBI)->getOpcode() == ARM::tPOP) { 1256acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio MachineBasicBlock::iterator PMBBI = prior(MBBI); 1257acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII); 1258acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else 1259acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 1260acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1261acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1262acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Darwin ABI requires FP to point to the stack slot that contains the 1263acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // previous FP. 1264acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (STI.isTargetDarwin() || hasFP(MF)) { 1265acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1266acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1267acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1268acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (AFI->getGPRCalleeSavedArea2Size() || 1269acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize() || 1270acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 1271acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio hasFP(MF)) 1272acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (NumBytes) 1273acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 1274acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio .addImm(NumBytes); 1275acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio else 1276acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr); 1277acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else if (NumBytes) { 1278acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, NumBytes, false, TII); 1279acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 12803548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1281acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 2. 1282acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 1283acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII); 1284236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1285acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 1. 1286acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 1287acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII); 1288236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1289acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to SP upon entry to the function. 1290acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 1291acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII); 1292acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1294236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 12959d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1296f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1297f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1298f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1299f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1300f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1301236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII); 1302f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1303f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1304f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1305f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1306f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 13079d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 13087bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 13097bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 13107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1311a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 13127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 13137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 13147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1315a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11; 13167bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 13177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 131862819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHExceptionRegister() const { 131962819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception register"); 132062819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 132162819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 132262819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 132362819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHHandlerRegister() const { 132462819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception handler register"); 132562819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 132662819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 132762819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 13287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 13297bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1330