ARMRegisterInfo.cpp revision 66f0f640820b61cf9db814b6d187bae9faf7279c
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 285ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng#include "llvm/CodeGen/RegisterScavenging.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 30b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 317ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 32b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 35ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng#include "llvm/Support/CommandLine.h" 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 39e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Chengstatic cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging", 40e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::Hidden, 41e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::desc("Enable register scavenging on Thumb")); 42ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng 43a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 76a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 798fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 80a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 8115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 8215f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 8315f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 84a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 86c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 884c6d20a096ad28aa6f812c07a48268e8a6ccb8feLauro Ramos Venancio FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng} 905ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng 91a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 100ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 101ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng unsigned Reg = CSI[i-1].getReg(); 102ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng // Add the callee-saved register as live-in. It's killed at the spill. 103ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MBB.addLiveIn(Reg); 104ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); 105ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng } 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 109a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1179d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1239d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1249d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1259d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 13566f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengstatic inline 13666f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengconst MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 13766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 13866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 13966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 14066f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengstatic inline 14166f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengconst MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 14266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return MIB.addReg(0); 14366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 14466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 14566f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengstatic const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB, 14666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineOperand &MO) { 14766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (MO.isRegister()) 14866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); 14966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng else if (MO.isImmediate()) 15066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = MIB.addImm(MO.getImm()); 15166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng else if (MO.isFrameIndex()) 15266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = MIB.addFrameIndex(MO.getFrameIndex()); 15366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng else 15466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng assert(0 && "Unknown operand for ARMInstrAddOperand!"); 15566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 15666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return MIB; 15766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 15866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 1597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1607bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1617bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1627bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 167ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true) 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 17066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::STR)) 17166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg, false, false, true) 17266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addReg(0).addImm(0)); 17366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else if (RC == ARM::DPRRegisterClass) { 17466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FSTD)) 17566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg, false, false, true) 17666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 17766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else { 17866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 17966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FSTS)) 18066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg, false, false, true) 18166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 18266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 18366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 18466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 18566f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengvoid ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 18666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng SmallVector<MachineOperand,4> Addr, 18766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng const TargetRegisterClass *RC, 18866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng SmallVector<MachineInstr*, 4> &NewMIs) const { 18966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng unsigned Opc = 0; 19066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (RC == ARM::GPRRegisterClass) { 19166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 19266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (AFI->isThumbFunction()) { 19366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR; 19466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = 19566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, true); 19666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 19766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 19866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 19966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 20066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 20166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::STR; 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 20366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FSTD; 204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 20666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FSTS; 207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 20866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 20966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = 21066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, true); 21166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 21266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 21366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(MIB); 21466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 21566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 2167bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 2187bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 2197bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 2207bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 2217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 2268e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 22966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 23066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addReg(0).addImm(0)); 231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 23266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 23366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 23666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 23766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 2397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2407bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 24166f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengvoid ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 24266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng SmallVector<MachineOperand,4> Addr, 24366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng const TargetRegisterClass *RC, 24466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng SmallVector<MachineInstr*, 4> &NewMIs) const { 24566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng unsigned Opc = 0; 24666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (RC == ARM::GPRRegisterClass) { 24766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 24866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (AFI->isThumbFunction()) { 24966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR; 25066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); 25166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 25266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 25366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 25466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 25566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 25666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::LDR; 25766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else if (RC == ARM::DPRRegisterClass) { 25866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FLDD; 25966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else { 26066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 26166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FLDS; 26266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 26366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 26466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); 26566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 26666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 26766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(MIB); 26866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 26966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 27066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 27166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 2727bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 274a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 2759efce638d307b2c71bd7f0258d47501661434c27Evan Cheng const TargetRegisterClass *DestRC, 2769efce638d307b2c71bd7f0258d47501661434c27Evan Cheng const TargetRegisterClass *SrcRC) const { 2779efce638d307b2c71bd7f0258d47501661434c27Evan Cheng if (DestRC != SrcRC) { 2789efce638d307b2c71bd7f0258d47501661434c27Evan Cheng cerr << "Not yet supported!"; 2799efce638d307b2c71bd7f0258d47501661434c27Evan Cheng abort(); 2809efce638d307b2c71bd7f0258d47501661434c27Evan Cheng } 2819efce638d307b2c71bd7f0258d47501661434c27Evan Cheng 2829efce638d307b2c71bd7f0258d47501661434c27Evan Cheng if (DestRC == ARM::GPRRegisterClass) { 283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 28544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (AFI->isThumbFunction()) 28644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg); 28744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng else 28866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg) 28966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg))); 2909efce638d307b2c71bd7f0258d47501661434c27Evan Cheng } else if (DestRC == ARM::SPRRegisterClass) 29166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg) 29266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg)); 2939efce638d307b2c71bd7f0258d47501661434c27Evan Cheng else if (DestRC == ARM::DPRRegisterClass) 29466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg) 29566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg)); 296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 2987bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2997bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 300bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize the 301bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// specified immediate. 302bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 303bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator &MBBI, 3043b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned DestReg, int Val, 3053b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 306bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const TargetInstrInfo &TII, bool isThumb) { 307bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineFunction &MF = *MBB.getParent(); 308bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 309bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, Val); 310bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 311bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (isThumb) 312bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx); 313bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng else 314bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx) 3153b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg); 316bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 317bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 318bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengvoid ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 319bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator I, 320bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned DestReg, 321bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const MachineInstr *Orig) const { 322bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (Orig->getOpcode() == ARM::MOVi2pieces) { 32344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitLoadConstPool(MBB, I, DestReg, 32444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng Orig->getOperand(1).getImmedValue(), 3253b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(), 3263b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng Orig->getOperand(3).getReg(), 327bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng TII, false); 328bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng return; 329bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng } 330bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 331bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineInstr *MI = Orig->clone(); 332bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MI->getOperand(0).setReg(DestReg); 333bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MBB.insert(I, MI); 334bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 335bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 33640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 33740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 33840984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 33940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 34040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 34140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 34240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 34340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 34440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 34540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 34640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 34740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 34840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 349a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 350a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 351a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 352a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 353a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 354a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 3559f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::MOVr: { 35613ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng if (MI->getOperand(4).getReg() == ARM::CPSR) 35713ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng // If it is updating CPSR, then it cannot be foled. 35813ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng break; 35944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 3603b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 361a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 362a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 363a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 3643b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 365a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 366a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 367a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 3683b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 369a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 370a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 371a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 3729f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::tMOVr: { 373a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 374a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 375bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 3768e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 37740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 3788e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 379a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 380a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 381a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 382bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 3838e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 38440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 3858e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 386a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 387a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 388a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 389a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 390a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 39144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 3923b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 393a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 394a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 395a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 3963b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 397a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 398a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 39944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI) 4003b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 401a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 402a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 403a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 404a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 40544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 4063b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 407a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 409a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 4103b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 411a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 412a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 41344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI) 4143b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 415a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 416a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 417a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 418a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 419a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 420a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 421a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 422a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 4237bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 4247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 42564d80e3387f328d21cd9cc06464b5de7861e3f27Evan Chengconst unsigned* 42664d80e3387f328d21cd9cc06464b5de7861e3f27Evan ChengARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 427c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 428a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 429a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 430a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 431a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 432a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 433a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 434ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 435a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 436a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 437a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 438a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 439a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 440a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 441a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 442a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 443a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 444970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 4450f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 4460f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 4470f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 4482365f51ed03afe6993bae962fdc2e5a956a64cd5Anton KorobeynikovARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 449c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 450a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 451a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 452a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 453a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 454a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 455a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 456a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 457ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 458c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 4590f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 4600f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 461b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 462c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // FIXME: avoid re-calculating this everytime. 463b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 464b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::SP); 465ad78ef215485389bb5c5698fa6f1ac670f0076d8Evan Cheng Reserved.set(ARM::PC); 466b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 467b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(FramePtr); 468b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // Some targets reserve R9. 469b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isR9Reserved()) 470b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::R9); 471b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 472b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 473b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 47436230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Chengbool 475140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { 476140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng switch (Reg) { 477140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng default: break; 478140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::SP: 479140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::PC: 480140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 481140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R7: 482140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R11: 483140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 484140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 485140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng break; 486140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R9: 487140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return STI.isR9Reserved(); 488140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 489140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 490140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return false; 491140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 492140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 493140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengbool 49436230cdda48edf6c634f2dcf69f9d78ac5a17377Evan ChengARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 49536230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 496e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng return ThumbRegScavenging || !AFI->isThumbFunction(); 4971b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng} 4981b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng 499a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 500a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 501a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 502a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 503dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 504a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 505a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 506a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5075c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 5085c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// not required, we reserve argument space for call sites in the function 5095c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// immediately on entry to the current function. This eliminates the need for 5105c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// add/sub sp brackets around call sites. Returns true if the call frame is 5115c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// included as part of the stack frame. 5125c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Chengbool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { 5135c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 5145c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng unsigned CFSize = FFI->getMaxCallFrameSize(); 5155c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 5165c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // It's not always a good idea to include the call frame as part of the 5175c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // stack frame. ARM (especially Thumb) has small immediate offset to 5185c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // address the stack frame. So a large call frame can cause poor codegen 5195c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // and may even makes it impossible to scavenge a register. 5205c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (AFI->isThumbFunction()) { 5215c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 5225c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return false; 5235c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng } else { 5245c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 5255c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return false; 5265c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng } 5274558b807a2076e199bcb019f5edc9eabbc5922c1Evan Cheng return !MF.getFrameInfo()->hasVarSizedObjects(); 5285c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng} 5295c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng 53036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 531a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 532a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 533a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 534a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 5353b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 5363b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 5373b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng const TargetInstrInfo &TII) { 538a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 539a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 541a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 547a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 548a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 550a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 551a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 552a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 554a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 55544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addReg(BaseReg, false, false, true).addImm(SOImmVal) 55613ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 557a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 559a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 560a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 56136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 56236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 56336640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 56436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 56536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 56636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 56736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 56836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 56936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 57036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 57136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 57236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 5733d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 1; // Followed by a number of tADDi8. 57436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 57536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 57636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 57736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 57836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 57936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 58036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 58136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 58236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 58336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 58436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 585403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 586403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 587403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 58836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 58936640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 590403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 59136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 59236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 593a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 594a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 5957142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 5967142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 59736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 59836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 599a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 600a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 601a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 602a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 60336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 60436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 60536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 60636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 60736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 60836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 60936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 6109f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12) 6115ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 61236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 613a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 614a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 6159f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 6168bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 6179f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 6185ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) 6195ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(LdReg, false, false, true); 6208bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 6213b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true); 6227142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 62336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 62436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 62536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 6265ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng if (DestReg == ARM::SP || isSub) 6275ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(BaseReg).addReg(LdReg, false, false, true); 62836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 6295ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(LdReg).addReg(BaseReg, false, false, true); 63036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 6319f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3) 6325ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 63336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 63436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 63536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 636a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 637a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 638a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 639a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 643a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 644a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 645a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 6478e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 6495b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 65036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 65136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 653a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 655a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 6565b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 657a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 6605b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 6615b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 6625b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 6635b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 665a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 666a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 668a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 6695b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 670a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 67236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 67336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 67436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 67536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 6768e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 677a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 679a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 68236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 6838e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 68436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 68536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 68636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 687403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 68836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 68936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 69036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 6918e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 69236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 69336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 69436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 69536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 69636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 69736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 6985ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(ThisVal); 69936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 7009f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg) 7015ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true); 70236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 70336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 70436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 70536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 7065b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 707a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 708a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 7095b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 7105b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 711a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 712a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 7133fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 714a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 7155ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng bool isKill = BaseReg != ARM::SP; 7165ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg) 7175ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, isKill).addImm(ThisVal); 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 721a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 7255b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 7265b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 727a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 728a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 729a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 730a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 731a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 732a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 733a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 7345ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg) 7355ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true) 736a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 737a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 738a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 739a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 740a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 7413b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, 7423b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng bool isThumb, const TargetInstrInfo &TII) { 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 745a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 7463b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, 7473b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng Pred, PredReg, TII); 748a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 7507bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 7517bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 7527bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 7535c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (!hasReservedCallFrame(MF)) { 754a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 755a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 756a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 757b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 758b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 759b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 760a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 761a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 762a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 763a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 764b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 765b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 766b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 76844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Opc = Old->getOpcode(); 76944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng bool isThumb = AFI->isThumbFunction(); 77044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ARMCC::CondCodes Pred = isThumb 77144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue(); 7723b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg(); 77344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 7743b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII); 775b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 77644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 7773b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII); 778b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 779b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 7807ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 7817bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 7827bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 7837bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 784a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 785a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 786a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 787a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 788a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 789a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 790a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 791a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 792a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 793a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 794a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 795a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 7969f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); 797a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 798a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 799a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 8005ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg) 8015ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true); 802a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 803a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 804c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// findScratchRegister - Find a 'free' ARM register. If register scavenger 805c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// is not being used, R12 is available. Otherwise, try for a call-clobbered 806c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// register first and then a spilled callee-saved register if that fails. 807c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengstatic 808c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengunsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 809c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng ARMFunctionInfo *AFI) { 810c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12; 811c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng if (Reg == 0) 812c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // Try a already spilled CS register. 813c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters()); 814c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 815c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng return Reg; 816c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng} 817c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 8181b051fc6a491c40cf3f926c089ad082938b653f0Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 81997de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng int SPAdj, RegScavenger *RS) const{ 820a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 82158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 82258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 82358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 824a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 825a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 82658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 827a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 828a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 829a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 830a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 831a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 832a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 833a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 834a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 83597de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng MF.getFrameInfo()->getStackSize() + SPAdj; 83658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 837a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 838a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 839a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 840a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 841a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 842a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 84375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 84497de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng assert(SPAdj == 0 && "Unexpected"); 845a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 846a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 847a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 848b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 849a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 850a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 851a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 852a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 853a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 854a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 8553d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 856a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 857a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 858a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 859a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 8609f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVr)); 861a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 862a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 863a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 864a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 865a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 866a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 867a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 868a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 86958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 870a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 871a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 872a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 873a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 874a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 875a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 876a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 877a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 878a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 879a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 880a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 881a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 882a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 883b03eacdbf39b37a98b65b936046b22cca8215d8dEvan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 884a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 885a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 886a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 887a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 888a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 889a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 890a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 891a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 892a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 893a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 8943d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 8953d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng // Can't use tADDrSPi if it's based off the frame pointer. 8963d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumBits = 0; 8973d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Scale = 1; 8983d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (FrameReg != ARM::SP) { 8993d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Opcode = ARM::tADDi3; 9003d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDi3)); 9013d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 3; 9023d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } else { 9033d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 8; 9043d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 4; 9053d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng assert((Offset & 3) == 0 && 9063d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 9073d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } 9083d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 909a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 910a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 9119f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVr)); 912a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 913a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 914a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 915a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 916a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 917a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 9183d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Mask = (1 << NumBits) - 1; 9193d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (((Offset / Scale) & ~Mask) == 0) { 920a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 921a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 9223d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset / Scale); 923a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 924a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 925a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 926a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 927a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 9283d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale); 929a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 930a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 931a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 93288b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 933a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 934a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 935a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 936a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 937a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 938a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 939a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 940a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 941a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 9423d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Mask); 9433d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Offset = (Offset - Mask * Scale); 944a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 945a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 946a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 947a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 948a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 949a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 950a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 951a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 9525ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); 953a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 954a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 955a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 956a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 957a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 958a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 959a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 960a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 961a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 962a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 963a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 964a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 965a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 966a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 967a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 968a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 969a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 970a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 971a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 972a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 973a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 974a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 975a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 976a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 977a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 978a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 979a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 980a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 981a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 982a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 983a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 984a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 985a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 986a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 987a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 988a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 989a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 9907142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 9917142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 992a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 993a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 994a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 9958fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 996a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 997a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 998a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 99958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 1000a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 10019312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 1002a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 1003a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 1004a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 1005a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 100658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 1007a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 10088e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 10098e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 10108e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 10118e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 10128e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 10138e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 10148e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 10158e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 10168e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 10178e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 10188e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 101988b633165a20398d1015eec561856500fcf30d7dEvan Cheng 10205ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 10215ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 10225ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 10235ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 10245ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 10255ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 10265ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 1027a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 1028a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 10295ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 10305ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 10315ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 103288b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 103388b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 1034a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 1035a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 1036a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 103788b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 1038a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1039a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1040a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1041a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 1042a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 1043a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 1044a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 104558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 1046a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 1047a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 1048a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 1049a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 10507142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 10517142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 10527142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 1053403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 10547142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 10553b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true); 10567142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 10577142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 10587142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 1059a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 10605b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 10615ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 10627142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 10637142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 10647142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 10655ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 1066a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 1067a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 1068a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 1069a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 1070a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 1071a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 1072a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 10738bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 1074a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 10755b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 1076a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 10777142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 10785b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 10799f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 10805ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R2, false, false, true); 1081a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 1082a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1083f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 10849f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 10855ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 10867142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 10877142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 1088403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 10897142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 10903b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true); 10917142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 10927142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 10937142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 1094a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 10955b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 10965ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 10977142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 10987142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 10997142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 11007142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 11018bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 11028bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 11038bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 11049f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2) 11055ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 1106f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 11079f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3) 11085ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 1109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 1110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 1111a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 1112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 1113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 1114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 1115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 1116c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); 1117140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (ScratchReg == 0) 1118140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // No register is "free". Scavenge a register. 111997de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); 112062ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng int PIdx = MI.findFirstPredOperandIdx(); 112162ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng ARMCC::CondCodes Pred = (PIdx == -1) 112262ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue(); 11233b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 11243b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, 11253b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng isSub ? -Offset : Offset, Pred, PredReg, TII); 11261b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1127a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 11287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11297bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1130140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengstatic unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 1131140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 1132140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int Offset = 0; 1133140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 1134140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int FixedOff = -FFI->getObjectOffset(i); 1135140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FixedOff > Offset) Offset = FixedOff; 1136140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1137140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 1138140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset += FFI->getObjectSize(i); 1139140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Align = FFI->getObjectAlignment(i); 1140140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Adjust to alignment boundary 1141140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset = (Offset+Align-1)/Align*Align; 1142140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1143140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return (unsigned)Offset; 1144140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 1145140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 1146140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengvoid 1147140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1148140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RegScavenger *RS) const { 114975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 115075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 115175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 1152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 115375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 1154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 1155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 1156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 1157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 1158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 1159f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 116075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 116175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 116275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 116375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 116475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 116575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 116675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 116775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 116875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 1169f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 117075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 117175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 117275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 117375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 117475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 117575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 117675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 117775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 1178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 118075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 1181a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 118275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 118375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 118475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 118575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 1186c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1187c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 1188c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 1189356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio CS1Spilled = true; 1190c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1191c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1192c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 119375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 119475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 119575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 119675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 119775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 119875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 119975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 120075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 120175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 120275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 120375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 120475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 120575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 120675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 120775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 1208c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1209c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 1210c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1211c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1212c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 121375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 121475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 121575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 121675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 121775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 121875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 121975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 122075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 122175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 122275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 122375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 1224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1229d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 1230d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 1231d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 1232f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // Force LR to be spilled if the Thumb function size is > 2048. This enables 1233d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 1234f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // then the branch fix up path will undo it. 1235d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 1236d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 1237d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 1238d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1239d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1240d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 1241140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng bool ExtraCSSpill = false; 12427588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 124375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 1244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1247a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 12486c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(ARM::LR); 1249f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 1251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1253d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 1254140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ExtraCSSpill = true; 1255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 12573548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 12583548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 12597588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 12606c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(FramePtr); 12613548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 12623548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 12633548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1264356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // If stack and double are 8-byte aligned and we are spilling an odd number 1265356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // of GPRs. Spill one extra callee save GPR so we won't have to pad between 1266356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // the integer and double callee save areas. 1267356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1268356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1269356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1270356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1271356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned Reg = UnspilledCS1GPRs[i]; 1272356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // Don't spiil high register if the function is thumb 1273356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) { 1274356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Reg); 1275356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Reg); 1276356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!isReservedReg(MF, Reg)) 1277356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio ExtraCSSpill = true; 1278356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio break; 1279356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1280356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1281356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } else if (!UnspilledCS2GPRs.empty() && 1282356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio !AFI->isThumbFunction()) { 1283356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned Reg = UnspilledCS2GPRs.front(); 1284356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Reg); 1285356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Reg); 1286356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!isReservedReg(MF, Reg)) 1287356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio ExtraCSSpill = true; 1288356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1289356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1290356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio 1291140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Estimate if we might need to scavenge a register at some point in order 1292140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // to materialize a stack offset. If so, either spill one additiona 1293140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // callee-saved register or reserve a special spill slot to facilitate 1294140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // register scavenging. 1295140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) { 1296140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng MachineFrameInfo *MFI = MF.getFrameInfo(); 1297140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Size = estimateStackSize(MF, MFI); 1298140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Limit = (1 << 12) - 1; 1299140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) 1300140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) { 1301140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) 1302140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (I->getOperand(i).isFrameIndex()) { 1303140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Opcode = I->getOpcode(); 1304140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 1305140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1306140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (AddrMode == ARMII::AddrMode3) { 1307140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Limit = (1 << 8) - 1; 1308140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng goto DoneEstimating; 1309140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else if (AddrMode == ARMII::AddrMode5) { 13105c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng unsigned ThisLimit = ((1 << 8) - 1) * 4; 13115c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (ThisLimit < Limit) 13125c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng Limit = ThisLimit; 1313140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1314140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1315140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1316140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng DoneEstimating: 1317140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (Size >= Limit) { 1318140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // If any non-reserved CS register isn't spilled, just spill one or two 1319140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // extra. That should take care of it! 1320356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned NumExtras = TargetAlign / 4; 1321356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio SmallVector<unsigned, 2> Extras; 1322356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio while (NumExtras && !UnspilledCS1GPRs.empty()) { 1323140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS1GPRs.back(); 1324140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS1GPRs.pop_back(); 1325140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1326356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio Extras.push_back(Reg); 1327356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio NumExtras--; 1328140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1329140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1330356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio while (NumExtras && !UnspilledCS2GPRs.empty()) { 1331140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS2GPRs.back(); 1332140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS2GPRs.pop_back(); 1333140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1334356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio Extras.push_back(Reg); 1335356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio NumExtras--; 1336140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1337140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1338356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (Extras.size() && NumExtras == 0) { 1339356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1340356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Extras[i]); 1341356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Extras[i]); 1342356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1343140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else { 1344140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Reserve a slot closest to SP or frame pointer. 1345140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetRegisterClass *RC = &ARM::GPRRegClass; 1346140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1347140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RC->getAlignment())); 1348140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1349f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng } 1350a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1351a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 135278268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 1353d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 13546c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(ARM::LR); 1355f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1356f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setLRIsSpilledForFarJump(true); 1357d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1358a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1359a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1360a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 1361a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 1362a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 1363a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1364a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1365a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1366a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1367a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1368a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1369a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1370a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1371a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1372a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 137375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1374a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1375a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1376a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 137775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1378970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1379a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 138075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 138175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1382a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1383a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1384a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1385a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1386a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1387a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1388a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1389a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1390a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1391a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1392a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1393a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1394a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 13957bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 13967bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1397355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 139844819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1399355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1400a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1401a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1402a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1403a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1404a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1405355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1406236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 14078bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 14088bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 14098bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 14108bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 14118bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 14128bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 14138bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 14148bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 14158bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1416236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1417236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1418236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1419236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1420236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1421a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1422a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1423a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1425acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1426acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (VARegSaveSize) 14273b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII); 1428acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1429236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1430236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 14313b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII); 1432236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1433236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1434236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1435236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1436236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1437236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1438236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1439236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1440236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1441236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1442236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1443236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1444236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1445236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1446236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1447236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1448236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1449236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1450236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1451236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1452236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1453236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1454236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1455236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1456236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1457236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1458236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1459a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1460a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1461a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1462236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1463236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1464236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1465236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1466a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1467236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1468a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1469236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1470236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 14713b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII); 1472236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1473236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1474236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1475a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 14763548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 14773548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 147844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 147944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng MachineInstrBuilder MIB = 148044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr) 1481236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 148266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (!isThumb) AddDefaultCC(AddDefaultPred(MIB)); 148344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng } 1484a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1485236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1486236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 14873b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII); 1488a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1489236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1490236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 14913b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII); 1492a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 14937ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1495236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1496236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1497236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1498236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1499236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1500236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1501236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1502a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1503236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1504236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1505236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1506236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1507236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 15083b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII); 1509236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 151015f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1511e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio if(STI.isTargetELF() && hasFP(MF)) { 1512e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1513e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio AFI->getFramePtrSpillOffset()); 1514e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio } 1515e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio 1516a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1517a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1518a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1519a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 15207ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1521a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1522a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1523a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1524a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1525a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1526a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1527a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1528a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1529a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 15318e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1532a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 15347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 15357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 15367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 1537bed2946a96ecb15b0b636fa74cb26ce61b1c648eAnton Korobeynikov MachineBasicBlock &MBB) const { 1538355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1539a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1541a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1542355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1543355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1544355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1547a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1548a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1549236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1550236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 15513b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 15529d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 1553acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Unwind MBBI to point to first LDR / FLDD. 1554acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio const unsigned *CSRegs = getCalleeSavedRegs(); 1555acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI != MBB.begin()) { 1556acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio do 1557acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio --MBBI; 1558acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1559acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (!isCSRestore(MBBI, CSRegs)) 1560acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio ++MBBI; 1561acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1562acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1563acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of FP callee save spill area. 1564acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1565acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getGPRCalleeSavedArea2Size() + 1566acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize()); 1567acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (isThumb) { 1568acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (hasFP(MF)) { 1569acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1570acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1571acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1572236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1573acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 1574236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 15759f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); 1576acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1577acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI->getOpcode() == ARM::tBX_RET && 1578acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio &MBB.front() != MBBI && 1579acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio prior(MBBI)->getOpcode() == ARM::tPOP) { 1580acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio MachineBasicBlock::iterator PMBBI = prior(MBBI); 15813b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 1582acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else 15833b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 1584acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1585acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1586acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Darwin ABI requires FP to point to the stack slot that contains the 1587acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // previous FP. 15889f8e50d4ed7dcc5ca0f137830ff1185b2afa38bfDale Johannesen if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) { 1589acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1590acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1591acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1592acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (AFI->getGPRCalleeSavedArea2Size() || 1593acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize() || 1594acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 1595acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio hasFP(MF)) 1596acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (NumBytes) 1597acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 159813ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm(NumBytes) 159913ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1600acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio else 160144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr) 160213ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1603acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else if (NumBytes) { 16043b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII); 1605acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 16063548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1607acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 2. 1608acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 16093b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0, 161044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1611236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1612acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 1. 1613acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 16143b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0, 161544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1616236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1617acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to SP upon entry to the function. 1618acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 16193b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0, 162044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1621acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1623236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 16249d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1625f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1626f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1627f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1628f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1629f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 16303b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII); 1631f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1632f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1633f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1634f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1635f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 16369d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 16377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 16387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 16397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 16417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 16427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 16437bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1644267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio if (STI.isTargetDarwin() || hasFP(MF)) 16454c6d20a096ad28aa6f812c07a48268e8a6ccb8feLauro Ramos Venancio return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11; 1646267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio else 1647267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio return ARM::SP; 16487bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 16497bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 165062819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHExceptionRegister() const { 165162819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception register"); 165262819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 165362819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 165462819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 165562819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHHandlerRegister() const { 165662819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception handler register"); 165762819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 165862819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 165962819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 16607bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 16617bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1662