ARMRegisterInfo.cpp revision 7588ad478aa95a7eb109034f0496f6d5a9769103
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 28b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 307ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 31a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 34a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <iostream> 357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 37a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 38a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 39a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 40a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 41a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 43a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng std::cerr << "Unknown ARM register!\n"; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 7515f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 7615f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 7715f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 78a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 79a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 80c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 81a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 82a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) { 83a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 84a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 85a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 86a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 88a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 89a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 90a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 91a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MIB.addReg(CSI[i-1].getReg()); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 105a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1207bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1227bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1237bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 125a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::tSTRspi)).addReg(SrcReg) 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg) 133a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 134a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg) 136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 138a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg) 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1437bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1447bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1457bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::tLDRspi), DestReg) 153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1657bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1667bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1677bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 170a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr), 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng DestReg).addReg(SrcReg); 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 177c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 179c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg); 180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 181a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 1827bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1837bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 184a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::MOVrr: { 191a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(0).addImm(0); 195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 196a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 197a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 198a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 200a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::tMOVrr: { 203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::tSTRspi)).addReg(SrcReg).addFrameIndex(FI) 206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::tLDRspi), DstReg).addFrameIndex(FI) 210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0); 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 230a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0); 233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 236a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 239a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 240a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 2417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 243c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 244c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 247a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 248a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 249a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 251ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 261970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 2620f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 2630f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 2640f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 265c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 266c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 274ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 275c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 2760f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 2770f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 280a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 281a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 282dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 28636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 287a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 288a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 289a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 298a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 299a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 300a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 301a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 303a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 304a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 305a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 306a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 307a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 308a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 309a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 310a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(BaseReg).addImm(SOImmVal); 311a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 312a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 313a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 314a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 315a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 316a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 317a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isLowRegister(unsigned Reg) { 318a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 319a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Reg) { 320a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case R1: case R2: case R3: 321a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case R5: case R6: case R7: 322a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 323a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 324a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 325a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 326a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 327a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 32836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 32936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 33036640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 33136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 33236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 33336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 33436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 33536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 33636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 33736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 33836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 33936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 34036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Scale = 1; 34136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 34236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 34336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 34436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 34536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 34636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 34736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 34836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 34936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 35036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 35136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 35236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusConstPool - Emits a series of instructions to materialize 35336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Load the immediate from a 35436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 35536640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 35636640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengvoid emitThumbRegPlusConstPool(MachineBasicBlock &MBB, 35736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 35836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 35936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int NumBytes, const TargetInstrInfo &TII) { 36036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineFunction &MF = *MBB.getParent(); 36136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 36236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isHigh = !isLowRegister(DestReg) || !isLowRegister(BaseReg); 36336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 36436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 36536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // if either base or dest register is a high register. 36636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumBytes < 0 && !isHigh) { 36736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 36836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 36936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 37036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes); 37136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 37236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 37336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 37436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 37536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 37636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3); 37736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 37836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Load the constant. 37936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), LdReg).addConstantPoolIndex(Idx); 38036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 38136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 38236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 38336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 38436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(BaseReg).addReg(LdReg); 38536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 38636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(LdReg).addReg(BaseReg); 38736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 38836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12); 38936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 39036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 39136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 392a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 393a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 394a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 395a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 396a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 397a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 398a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 399a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 400a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 401a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 402a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 40336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool DstNeBase = false; 404a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 4055b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 40636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 40736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 409a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 410a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 411a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 4125b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 413a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 414a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 415a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 4165b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 4175b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 4185b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 4195b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 420a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 421a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 422a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 423a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 4255b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 426a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 427a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 42836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 42936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 43036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 43136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 43236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng DstNeBase = true; 433a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 434a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 435a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 436a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 437a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 43836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 43936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 4 : 3; 44036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 44136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 44236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 44336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng emitThumbRegPlusConstPool(MBB, MBBI, DestReg, BaseReg, NumBytes, TII); 44436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 44536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 44636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 44736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DstNeBase) { 44836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 44936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 45036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 45136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 45236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 45336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 45436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng .addReg(BaseReg).addImm(ThisVal); 45536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 45636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg); 45736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 45836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 45936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 46036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 4615b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 462a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 463a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 4645b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 4655b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 466a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 467a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 4683fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 469a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 470a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal); 471a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 472a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 473a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 474a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 475a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 476a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 477a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 4785b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 4795b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 480a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 481a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 482a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 483a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 484a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 485a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 486a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 487a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg) 488a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 489a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 490a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 491a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 492a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 493a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, bool isThumb, const TargetInstrInfo &TII) { 494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 495a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 496a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 497a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 498a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 499a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5007bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 5017bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 5027bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 50375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (hasFP(MF)) { 504a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 505a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 506a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 507b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 508b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 509b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 510a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 511a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 512a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 513a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 514b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 515b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 516b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 517a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 518b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) { 519a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII); 520b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 521b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola assert(Old->getOpcode() == ARM::ADJCALLSTACKUP); 522a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII); 523b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 524b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 5257ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 5267bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 5277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 5287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 529a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 531a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 532a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 534a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 535a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 536a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 537a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 538a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 539a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 541a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal); 542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg).addReg(DestReg); 546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 547a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 548a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 55058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 55158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 55258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 554a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 55558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 556a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 557a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 559a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 560a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 561a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 562a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 563a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.getFrameInfo()->getStackSize(); 56558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 566a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 567a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 568a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 569a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 570a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 571a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 57275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 573a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 574a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 575a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 576b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 577a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 578a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 579a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 580a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 582a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 583a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 584a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 585a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 586a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 587a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 588a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVrr)); 589a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 590a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 592a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 594a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 595a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 596a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 59758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 598a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 599a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 600a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 601a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 602a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 603a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 604a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 605a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 607a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 608a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 609a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 610a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 611a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31); 612a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 613a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 614a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 615a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 616a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 617a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 619a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 620a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 621a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((Offset & 3) == 0 && 62386eb5153594b523e0b201735e14c92785d7ba601Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 624a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset >>= 2; 625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 626a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 627a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVrr)); 628a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 629a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 630a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 631a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 632a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 633a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 634a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((Offset & ~255U) == 0) { 635a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 636a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset); 638a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 639a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 643a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 644a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 645a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(255); 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = (Offset - 255) << 2; 649a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 650a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 651a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 653a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 655a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset <<= 2; 656a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 657a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false); 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 660a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 661a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 662a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 663a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 665a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 666a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 668a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 669a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 670a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 672a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 673a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 674a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 675a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 676a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 677a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 679a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 687a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 688a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 689a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 690a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 692a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 693a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 694a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 696a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 700a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 701a8e2989ece6dc46df59b0768184028257f913843Evan Cheng std::cerr << "Unsupported addressing mode!\n"; 702a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 703a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 704a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 70558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 706a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 707a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((Scale == 1 || (Offset & (Scale-1)) == 0) && 708a8e2989ece6dc46df59b0768184028257f913843Evan Cheng "Can't encode this offset!"); 709a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset < 0) { 710a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 711a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 712a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 71358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 714a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 715a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = Offset / Scale; 716a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Mask = (1 << NumBits) - 1; 717a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 721a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 72558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 72636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immediate. 7275b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (AddrMode == ARMII::AddrModeTs) { 7285b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use a 7295b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // different base register. 7305b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng NumBits = 5; 7315b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Mask = (1 << NumBits) - 1; 7325b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng } 7335b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng 734a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset = ImmedOffset & Mask; 735a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 736a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 737a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 738a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~(Mask*Scale); 739a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 740a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 741a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 74558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 746a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 747a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 748a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 750a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, 751a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 7525b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 753a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 7545b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 755a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 756a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 757a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 758a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 759a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 760a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 761a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 762a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // str r12, r2 763a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 7645b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 7665b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2); 768a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 769a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 770a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, 771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 7725b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 7735b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 7745b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 7755b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) 776a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12); 777a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 778a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 779a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 780a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 781a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 782a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 783a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 784a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg, 785a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 786a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(ARM::R12, false); 787a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 7887bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 7897bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 7907bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 791a8e2989ece6dc46df59b0768184028257f913843Evan ChengprocessFunctionBeforeCalleeSavedScan(MachineFunction &MF) const { 79275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 79375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 79475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 795a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 79675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 797a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 798a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 799a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 800a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 801a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 80275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 80375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 80475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 80575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 80675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 80775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 80875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 80975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 81075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 81175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 81275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 81375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 81475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 81575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 81675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 81775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 81875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 819a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 820a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 82175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 822a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 82375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 82475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 82575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 82675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 827c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 828c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 829c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 830c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else 831c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng CS1Spilled = true; 832c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 833c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 834c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 83575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 83675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 83775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 83875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 83975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 84075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 84175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 84275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 84375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 84475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 84575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 84675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 84775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 84875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 84975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 850c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 851c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 852c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 853c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 854c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 85575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 85675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 85775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 85875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 85975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 86075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 86175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 86275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 86375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 86475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 86575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 866a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 867a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 868a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 869a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 870a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 87178268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 872d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 873d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 874d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 875d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // Force LR spill if the Thumb function size is > 2048. This enables the 876d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 877d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // the branch fix up path will undo it. 878d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 879d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 880d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 881d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 882d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 883d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 8847588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 88575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 886a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 887a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 888a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 889a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 890a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(ARM::LR, true); 891a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 892a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 893a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 894d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 895a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 896a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 8973548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 8983548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 8997588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 9003548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng MF.changePhyRegUsed(FramePtr, true); 9013548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 9023548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 9033548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 904c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng // If stack and double are 8-byte aligned and we are spilling an odd number 905a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of GPRs. Spill one extra callee save GPR so we won't have to pad between 906a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // the integer and double callee save areas. 907a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 908a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TargetAlign == 8 && (NumGPRSpills & 1)) { 909a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (CS1Spilled && !UnspilledCS1GPRs.empty()) 910a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS1GPRs.front(), true); 911c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else if (!UnspilledCS2GPRs.empty()) 912a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true); 913a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 914a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 91578268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 916d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 917d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng MF.changePhyRegUsed(ARM::LR, true); 918d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng AFI->setLRIsForceSpilled(true); 919d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 920a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 921a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 922a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 923a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 924a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 925a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 926a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 927a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 928a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 929a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 930a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 931a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 932a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 933a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 934a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 93575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 936a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 937a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 938a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 93975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 940970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 941a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 94275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 94375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 944a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 945a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 946a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 947a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 948a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 949a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 950a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 951a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 952a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 953a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 954a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 955a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 956a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 9577bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 9587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 959355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 96044819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 961355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 962a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 963a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 964a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 965a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 966a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 967a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 968355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 969236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 970236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 971236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 972236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 973236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 974236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 975a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 976a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 977a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 978a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 979236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 980236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 981236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 982236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 983236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 984236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 985236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (VARegSaveSize) 986236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII); 987236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 988236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 989236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 990236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 991236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 992236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 993236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 994236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 995236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 996236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 997236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 998236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 999236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1000236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1001236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1002236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1003236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1004236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1005236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1006236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1007236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1008236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1009236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1010236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1011236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1012a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1013a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1014a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1015236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1016236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1017236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1018236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1019a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1020236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1021a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1022236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Align == 8 && (GPRCS1Size & 7) != 0) 1023236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Pad CS1 to ensure proper alignment. 1024236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1025c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 1026236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1027236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1028236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII); 1029236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1030236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1031236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1032a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 10333548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 10343548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 10353548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 1036236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr) 1037236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 1038a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1039236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1040236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1041236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII); 1042a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1043236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1044236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 1045236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII); 1046a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 10477ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1048a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1049236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1050236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1051236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1052236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1053236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1054236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1055236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1056a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1057236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1058236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1059236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1060236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1061236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 1062a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1063236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 106415f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1065a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1066a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1067a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1068a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 10697ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1070a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1071a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1072a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1073a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1074a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1075a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1076a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1077a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1078a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1079a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 1080a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::tLDRspi) && 1081a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1082a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 10837bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 10847bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 10857bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 10867bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock &MBB) const { 1087355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1088a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1089a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1090a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1091355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1092355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1093355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1094a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1095a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1096a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1097a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1098236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1099236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 11003df62bde9b3f2557cccfa1f18d25b57bf0477f60Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 1101236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1102236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 110315f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1104236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Unwind MBBI to point to first LDR / FLDD. 1105236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 1106236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (MBBI != MBB.begin()) { 1107236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng do 1108236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng --MBBI; 1109236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1110236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isCSRestore(MBBI, CSRegs)) 1111236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1112236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1114236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of FP callee save spill area. 1115236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1116236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getGPRCalleeSavedArea2Size() + 1117236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaSize()); 1118236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) 1119236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 1120236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else { 11213548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 11223548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 11233548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 1124236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1125236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Reset SP based on frame pointer only if the stack frame extends beyond 1126236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // frame pointer stack slot. 1127236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (AFI->getGPRCalleeSavedArea2Size() || 1128236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaSize() || 1129236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaOffset()) 1130236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1131236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 1132236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addImm(NumBytes); 1133236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 1134236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr); 1135236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (NumBytes) { 1136236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, false, TII); 1137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 11383548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1139236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of integer callee save spill area 2. 1140236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 1141236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII); 1142236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1143236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of integer callee save spill area 1. 1144236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 1145236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII); 1146236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1147236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to SP upon entry to the function. 1148236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 1149236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII); 1150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1151236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1152236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (VARegSaveSize) 1153236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII); 11547bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11557bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 11567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 11587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 11607bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11; 11627bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11637bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 11647bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 11657bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1166