ARMRegisterInfo.cpp revision 75e18c403e4046057cb99accb3afc7cdf6fadd61
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//
37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//                     The LLVM Compiler Infrastructure
47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//
57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and
67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source
77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details.
87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//
97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===//
107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//
117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class.
127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//
137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===//
147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h"
16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h"
17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h"
18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h"
197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h"
20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h"
217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineInstrBuilder.h"
227bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFunction.h"
237bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h"
247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h"
25b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h"
26b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h"
277ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h"
28a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/Type.h"
29a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h"
307bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h"
31a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm>
32a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <iostream>
337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm;
347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
35a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  using namespace ARM;
37a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  switch (RegEnum) {
38a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R0:  case S0:  case D0:  return 0;
39a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R1:  case S1:  case D1:  return 1;
40a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R2:  case S2:  case D2:  return 2;
41a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R3:  case S3:  case D3:  return 3;
42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R4:  case S4:  case D4:  return 4;
43a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R5:  case S5:  case D5:  return 5;
44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R6:  case S6:  case D6:  return 6;
45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R7:  case S7:  case D7:  return 7;
46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R8:  case S8:  case D8:  return 8;
47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R9:  case S9:  case D9:  return 9;
48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R10: case S10: case D10: return 10;
49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R11: case S11: case D11: return 11;
50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R12: case S12: case D12: return 12;
51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case SP:  case S13: case D13: return 13;
52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case LR:  case S14: case D14: return 14;
53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case PC:  case S15: case D15: return 15;
54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S16: return 16;
55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S17: return 17;
56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S18: return 18;
57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S19: return 19;
58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S20: return 20;
59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S21: return 21;
60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S22: return 22;
61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S23: return 23;
62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S24: return 24;
63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S25: return 25;
64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S26: return 26;
65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S27: return 27;
66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S28: return 28;
67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S29: return 29;
68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S30: return 30;
69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case S31: return 31;
70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  default:
71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    std::cerr << "Unknown ARM register!\n";
72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    abort();
7315f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola  }
7415f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola}
7515f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola
76a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                 const ARMSubtarget &sti)
78c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
79a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    TII(tii), STI(sti),
80a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
81a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
82a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
83a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
84a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                                MachineBasicBlock::iterator MI,
85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                const std::vector<CalleeSavedInfo> &CSI) const {
86a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  MachineFunction &MF = *MBB.getParent();
87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
88a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (!AFI->isThumbFunction() || CSI.empty())
89a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    return false;
90a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
91a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  for (unsigned i = CSI.size(); i != 0; --i)
93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    MIB.addReg(CSI[i-1].getReg());
94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  return true;
95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
97a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                                 MachineBasicBlock::iterator MI,
99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                const std::vector<CalleeSavedInfo> &CSI) const {
100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  MachineFunction &MF = *MBB.getParent();
101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (!AFI->isThumbFunction() || CSI.empty())
103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    return false;
104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
105a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP));
106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  MBB.insert(MI, PopMI);
107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  for (unsigned i = CSI.size(); i != 0; --i) {
108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned Reg = CSI[i-1].getReg();
109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (Reg == ARM::LR) {
110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      Reg = ARM::PC;
111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MBB.erase(MI);
113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    PopMI->addRegOperand(Reg, true);
115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  return true;
1177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola}
1187bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
1197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::
1207bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola                    unsigned SrcReg, int FI,
1227bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola                    const TargetRegisterClass *RC) const {
123a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (RC == ARM::GPRRegisterClass) {
124a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    MachineFunction &MF = *MBB.getParent();
125a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (AFI->isThumbFunction())
127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      BuildMI(MBB, I, TII.get(ARM::tSTRspi)).addReg(SrcReg)
128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        .addFrameIndex(FI).addImm(0);
129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    else
130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg)
131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          .addFrameIndex(FI).addReg(0).addImm(0);
132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  } else if (RC == ARM::DPRRegisterClass) {
133a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg)
134a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    .addFrameIndex(FI).addImm(0);
135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  } else {
136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg)
138a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      .addFrameIndex(FI).addImm(0);
139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
1407bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola}
1417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
1427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::
1437bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1447bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola                     unsigned DestReg, int FI,
1457bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola                     const TargetRegisterClass *RC) const {
146a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (RC == ARM::GPRRegisterClass) {
147a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    MachineFunction &MF = *MBB.getParent();
148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (AFI->isThumbFunction())
150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      BuildMI(MBB, I, TII.get(ARM::tLDRspi), DestReg)
151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        .addFrameIndex(FI).addImm(0);
152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    else
153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      .addFrameIndex(FI).addReg(0).addImm(0);
155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  } else if (RC == ARM::DPRRegisterClass) {
156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      .addFrameIndex(FI).addImm(0);
158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  } else {
159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      .addFrameIndex(FI).addImm(0);
162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
1637bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola}
1647bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
1657bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                   MachineBasicBlock::iterator I,
167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                   unsigned DestReg, unsigned SrcReg,
168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                   const TargetRegisterClass *RC) const {
169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (RC == ARM::GPRRegisterClass) {
170a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    MachineFunction &MF = *MBB.getParent();
171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr),
173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng            DestReg).addReg(SrcReg);
174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  } else if (RC == ARM::SPRRegisterClass)
175c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng    BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  else if (RC == ARM::DPRRegisterClass)
177c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng    BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  else
179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    abort();
1807bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola}
1817bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
182a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                                 unsigned OpNum, int FI) const {
184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned Opc = MI->getOpcode();
185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  MachineInstr *NewMI = NULL;
186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  switch (Opc) {
187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  default: break;
188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case ARM::MOVrr: {
189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (OpNum == 0) { // move -> store
190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned SrcReg = MI->getOperand(1).getReg();
191a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        .addReg(0).addImm(0);
193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    } else {          // move -> load
194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned DstReg = MI->getOperand(0).getReg();
195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
196a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        .addImm(0);
197a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
198a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    break;
199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
200a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case ARM::tMOVrr: {
201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (OpNum == 0) { // move -> store
202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned SrcReg = MI->getOperand(1).getReg();
203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NewMI = BuildMI(TII.get(ARM::tSTRspi)).addReg(SrcReg).addFrameIndex(FI)
204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        .addImm(0);
205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    } else {          // move -> load
206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned DstReg = MI->getOperand(0).getReg();
207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NewMI = BuildMI(TII.get(ARM::tLDRspi), DstReg).addFrameIndex(FI)
208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        .addImm(0);
209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    break;
211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case ARM::FCPYS: {
213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (OpNum == 0) { // move -> store
214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned SrcReg = MI->getOperand(1).getReg();
215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        .addImm(0);
217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    } else {          // move -> load
218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned DstReg = MI->getOperand(0).getReg();
219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0);
220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    break;
222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case ARM::FCPYD: {
224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (OpNum == 0) { // move -> store
225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned SrcReg = MI->getOperand(1).getReg();
226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        .addImm(0);
228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    } else {          // move -> load
229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned DstReg = MI->getOperand(0).getReg();
230a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0);
231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    break;
233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
236a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (NewMI)
237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    NewMI->copyKillDeadInfo(MI);
238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  return NewMI;
2397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola}
2407bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
241c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
242c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng  static const unsigned CalleeSavedRegs[] = {
243a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
247a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
248a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    0
249ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola  };
250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  static const unsigned DarwinCalleeSavedRegs[] = {
252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARM::R11, ARM::R10, ARM::R9, ARM::R8,
254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    0
258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  };
259970a419633ba41cac44ae636543f192ea632fe00Evan Cheng  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
2600f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng}
2610f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng
2620f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const *
263c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const {
264c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
265a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    0
272ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola  };
273c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng  return CalleeSavedRegClasses;
2740f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng}
2750f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng
276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame
277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register.  This is true if the function has variable sized allocas
278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled.
279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng///
280a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool hasFP(const MachineFunction &MF) {
281a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
282a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitARMRegPlusImmediate - Emit a series of instructions to materialize
285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code.
286a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic
287a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB,
288a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                             MachineBasicBlock::iterator &MBBI,
289a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                             unsigned DestReg, unsigned BaseReg,
290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                             int NumBytes, const TargetInstrInfo &TII) {
291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  bool isSub = NumBytes < 0;
292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (isSub) NumBytes = -NumBytes;
293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  while (NumBytes) {
295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    assert(ThisVal && "Didn't extract field correctly");
298a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
299a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // We will handle these bits from offset, clear them.
300a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    NumBytes &= ~ThisVal;
301a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Get the properly encoded SOImmVal field.
303a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
304a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    assert(SOImmVal != -1 && "Bit extraction didn't work?");
305a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
306a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Build the new ADD / SUB.
307a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
308a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      .addReg(BaseReg).addImm(SOImmVal);
309a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    BaseReg = DestReg;
310a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
311a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
312a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
313a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7.
314a8e2989ece6dc46df59b0768184028257f913843Evan Cheng///
315a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isLowRegister(unsigned Reg) {
316a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  using namespace ARM;
317a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  switch (Reg) {
318a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R0:  case R1:  case R2:  case R3:
319a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  case R4:  case R5:  case R6:  case R7:
320a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    return true;
321a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  default:
322a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    return false;
323a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
324a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
325a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
326a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbRegPlusImmediate - Emit a series of instructions to materialize
327a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code.
328a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic
329a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
330a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                               MachineBasicBlock::iterator &MBBI,
331a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                               unsigned DestReg, unsigned BaseReg,
332a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                               int NumBytes, const TargetInstrInfo &TII) {
333a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  bool isSub = NumBytes < 0;
334a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned Bytes = (unsigned)NumBytes;
335a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (isSub) Bytes = -NumBytes;
336a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  bool isMul4 = (Bytes & 3) == 0;
337a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  bool isTwoAddr = false;
338a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned NumBits = 1;
339a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned Opc = 0;
340a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned ExtraOpc = 0;
341a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
342a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (DestReg == BaseReg && BaseReg == ARM::SP) {
343a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
344a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Bytes >>= 2;  // Implicitly multiplied by 4.
345a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    NumBits = 7;
346a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
347a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    isTwoAddr = true;
348a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  } else if (!isSub && BaseReg == ARM::SP) {
349a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (!isMul4) {
350a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      Bytes &= ~3;
351a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      ExtraOpc = ARM::tADDi3;
352a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
353a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Bytes >>= 2;  // Implicitly multiplied by 4.
354a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    NumBits = 8;
355a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Opc = ARM::tADDrSPi;
356a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  } else {
357a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (DestReg != BaseReg) {
358a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
359a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
360a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        unsigned Chunk = (1 << 3) - 1;
361a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
362a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        Bytes -= ThisVal;
363a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
364a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          .addReg(BaseReg).addImm(ThisVal);
365a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      } else {
366a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg);
367a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      }
368a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      BaseReg = DestReg;
369a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
370a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    NumBits = 8;
371a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
372a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    isTwoAddr = true;
373a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
374a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
375a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned Chunk = (1 << NumBits) - 1;
376a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  while (Bytes) {
377a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
378a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Bytes -= ThisVal;
379a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Build the new tADD / tSUB.
380a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (isTwoAddr)
381a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addImm(ThisVal);
382a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    else {
383a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal);
384a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      BaseReg = DestReg;
385a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
386a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (Opc == ARM::tADDrSPi) {
387a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        // r4 = add sp, imm
388a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        // r4 = add r4, imm
389a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        // ...
390a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        NumBits = 8;
391a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
392a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        isTwoAddr = true;
393a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      }
394a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
395a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
396a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
397a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (ExtraOpc)
398a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg)
399a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      .addImm(((unsigned)NumBytes) & 3);
400a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
401a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
402a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic
403a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
404a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                  int NumBytes, bool isThumb, const TargetInstrInfo &TII) {
405a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (isThumb)
406a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
407a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  else
408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
409a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
410a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
4117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::
4127bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
4137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola                              MachineBasicBlock::iterator I) const {
41475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  if (hasFP(MF)) {
415a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // If we have alloca, convert as follows:
416a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
417a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // ADJCALLSTACKUP   -> add, sp, sp, amount
418b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola    MachineInstr *Old = I;
419b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola    unsigned Amount = Old->getOperand(0).getImmedValue();
420b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola    if (Amount != 0) {
421a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
422a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // We need to keep the stack aligned properly.  To do this, we round the
423a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // amount of space needed for the outgoing arguments up to the next
424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // alignment boundary.
425b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
426b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola      Amount = (Amount+Align-1)/Align*Align;
427b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola
428a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Replace the pseudo instruction with a new instruction...
429b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola      if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
430a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII);
431b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola      } else {
432b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola        assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
433a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII);
434b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola      }
435b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola    }
4367ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola  }
4377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola  MBB.erase(I);
4387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola}
4397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
440a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a
441a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant.
442a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB,
443a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                              MachineBasicBlock::iterator &MBBI,
444a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                              unsigned DestReg, int Imm,
445a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                              const TargetInstrInfo &TII) {
446a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  bool isSub = Imm < 0;
447a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (isSub) Imm = -Imm;
448a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
449a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  int Chunk = (1 << 8) - 1;
450a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  int ThisVal = (Imm > Chunk) ? Chunk : Imm;
451a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  Imm -= ThisVal;
452a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal);
453a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (Imm > 0)
454a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
455a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (isSub)
456a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg).addReg(DestReg);
457a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
458a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
459a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
460a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned i = 0;
46158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola  MachineInstr &MI = *II;
46258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola  MachineBasicBlock &MBB = *MI.getParent();
46358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola  MachineFunction &MF = *MBB.getParent();
464a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
465a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  bool isThumb = AFI->isThumbFunction();
46658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola
467a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  while (!MI.getOperand(i).isFrameIndex()) {
468a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ++i;
469a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
470a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
471a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
472a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned FrameReg = ARM::SP;
473a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  int FrameIndex = MI.getOperand(i).getFrameIndex();
474a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
475a8e2989ece6dc46df59b0768184028257f913843Evan Cheng               MF.getFrameInfo()->getStackSize();
47658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola
477a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
478a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Offset -= AFI->getGPRCalleeSavedArea1Offset();
479a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
480a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Offset -= AFI->getGPRCalleeSavedArea2Offset();
481a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
482a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Offset -= AFI->getDPRCalleeSavedAreaOffset();
48375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  else if (hasFP(MF)) {
484a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // There is alloca()'s in this function, must reference off the frame
485a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // pointer instead.
486a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    FrameReg = getFrameRegister(MF);
487a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Offset -= AFI->getFramePtrSpillOffset();
488a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
489a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
490a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned Opcode = MI.getOpcode();
491a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  const TargetInstrDescriptor &Desc = TII.get(Opcode);
492a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
493a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  bool isSub = false;
494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
495a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (Opcode == ARM::ADDri) {
496a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Offset += MI.getOperand(i+1).getImm();
497a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (Offset == 0) {
498a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Turn it into a move.
499a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.setInstrDescriptor(TII.get(ARM::MOVrr));
500a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i).ChangeToRegister(FrameReg, false);
501a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.RemoveOperand(i+1);
502a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      return;
503a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    } else if (Offset < 0) {
504a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      Offset = -Offset;
505a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      isSub = true;
506a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.setInstrDescriptor(TII.get(ARM::SUBri));
507a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
50858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola
509a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Common case: small offset, fits into instruction.
510a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    int ImmedOffset = ARM_AM::getSOImmVal(Offset);
511a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (ImmedOffset != -1) {
512a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Replace the FrameIndex with sp / fp
513a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i).ChangeToRegister(FrameReg, false);
514a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
515a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      return;
516a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
517a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
518a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Otherwise, we fallback to common code below to form the imm offset with
519a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // a sequence of ADDri instructions.  First though, pull as much of the imm
520a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // into this ADDri as possible.
521a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
522a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31);
523a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
524a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // We will handle these bits from offset, clear them.
525a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Offset &= ~ThisImmVal;
526a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
527a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Get the properly encoded SOImmVal field.
528a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
529a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
531a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  } else if (Opcode == ARM::tADDrSPi) {
532a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Offset += MI.getOperand(i+1).getImm();
533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    assert((Offset & 3) == 0 &&
534a8e2989ece6dc46df59b0768184028257f913843Evan Cheng           "add/sub sp, #imm immediate must be multiple of 4!");
535a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Offset >>= 2;
536a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (Offset == 0) {
537a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Turn it into a move.
538a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.setInstrDescriptor(TII.get(ARM::tMOVrr));
539a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i).ChangeToRegister(FrameReg, false);
540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.RemoveOperand(i+1);
541a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      return;
542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Common case: small offset, fits into instruction.
545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if ((Offset & ~255U) == 0) {
546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Replace the FrameIndex with sp / fp
547a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i).ChangeToRegister(FrameReg, false);
548a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i+1).ChangeToImmediate(Offset);
549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      return;
550a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
551a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
552a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned DestReg = MI.getOperand(0).getReg();
553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (Offset > 0) {
554a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Translate r0 = add sp, imm to
555a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // r0 = add sp, 255*4
556a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // r0 = add r0, (imm - 255*4)
557a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i).ChangeToRegister(FrameReg, false);
558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i+1).ChangeToImmediate(255);
559a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      Offset = (Offset - 255) << 2;
560a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MachineBasicBlock::iterator NII = next(II);
561a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII);
562a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    } else {
563a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Translate r0 = add sp, -imm to
564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // r0 = -imm (this is then translated into a series of instructons)
565a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // r0 = add r0, sp
566a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      Offset <<= 2;
567a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitThumbConstant(MBB, II, DestReg, Offset, TII);
568a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
569a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i).ChangeToRegister(DestReg, false);
570a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
571a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
572a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    return;
573a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  } else {
574a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned ImmIdx = 0;
575a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    int InstrOffs = 0;
576a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned NumBits = 0;
577a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned Scale = 1;
578a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    switch (AddrMode) {
579a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    case ARMII::AddrMode2: {
580a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      ImmIdx = i+2;
581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
582a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
583a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        InstrOffs *= -1;
584a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NumBits = 12;
585a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      break;
586a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
587a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    case ARMII::AddrMode3: {
588a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      ImmIdx = i+2;
589a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
590a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        InstrOffs *= -1;
592a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NumBits = 8;
593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      break;
594a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
595a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    case ARMII::AddrMode5: {
596a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      ImmIdx = i+1;
597a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
598a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
599a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        InstrOffs *= -1;
600a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NumBits = 8;
601a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      Scale = 4;
602a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      break;
603a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
604a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    case ARMII::AddrModeTs: {
605a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      ImmIdx = i+1;
606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      InstrOffs = MI.getOperand(ImmIdx).getImm();
607a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NumBits = 8;
608a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      Scale = 4;
609a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      break;
610a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
611a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    default:
612a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      std::cerr << "Unsupported addressing mode!\n";
613a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      abort();
614a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      break;
615a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
61658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola
617a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Offset += InstrOffs * Scale;
618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    assert((Scale == 1 || (Offset & (Scale-1)) == 0) &&
619a8e2989ece6dc46df59b0768184028257f913843Evan Cheng           "Can't encode this offset!");
620a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (Offset < 0) {
621a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      Offset = -Offset;
622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      isSub = true;
623a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
62458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola
625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    MachineOperand &ImmOp = MI.getOperand(ImmIdx);
626a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    int ImmedOffset = Offset / Scale;
627a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned Mask = (1 << NumBits) - 1;
628a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if ((unsigned)Offset <= Mask * Scale) {
629a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Replace the FrameIndex with sp
630a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i).ChangeToRegister(FrameReg, false);
631a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (isSub)
632a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        ImmedOffset |= 1 << NumBits;
633a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      ImmOp.ChangeToImmediate(ImmedOffset);
634a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      return;
635a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
63658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola
637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Otherwise, it didn't fit.  Pull in what we can to simplify the immediate.
638a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ImmedOffset = ImmedOffset & Mask;
639a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (isSub)
640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      ImmedOffset |= 1 << NumBits;
641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ImmOp.ChangeToImmediate(ImmedOffset);
642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    Offset &= ~(Mask*Scale);
643a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
644a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
645a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  // If we get here, the immediate doesn't fit into the instruction.  We folded
646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  // as much as possible above, handle the rest, providing a register that is
647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  // SP+LargeImm.
648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  assert(Offset && "This code isn't needed if offset already handled!");
64958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola
650a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  if (isThumb) {
651a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (TII.isLoad(Opcode)) {
652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Use the destination register to materialize sp + offset.
653a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned TmpReg = MI.getOperand(0).getReg();
654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg,
655a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                isSub ? -Offset : Offset, TII);
656a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i).ChangeToRegister(TmpReg, false);
657a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    } else if (TII.isStore(Opcode)) {
658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // FIXME! This is horrific!!! We need register scavenging.
659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Our temporary workaround has marked r3 unavailable. Of course, r3 is
660a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // also a ABI register so it's possible that is is the register that is
661a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // being storing here. If that's the case, we do the following:
662a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // r12 = r2
663a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Use r2 to materialize sp + offset
664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // str r12, r2
665a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // r2 = r12
666a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned DestReg = MI.getOperand(0).getReg();
667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned TmpReg = ARM::R3;
668a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (DestReg == ARM::R3) {
669a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2);
670a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        TmpReg = ARM::R2;
671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      }
672a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg,
673a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                isSub ? -Offset : Offset, TII);
674a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MI.getOperand(i).ChangeToRegister(DestReg, false);
675a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (DestReg == ARM::R3)
676a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12);
677a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    } else
678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      assert(false && "Unexpected opcode!");
679a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola  } else {
680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Insert a set of r12 with the full address: r12 = sp + offset
681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // If the offset we have is too large to fit into the instruction, we need
682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // to form it with a series of ADDri's.  Do this by taking 8-bit chunks
683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // out of 'Offset'.
684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg,
685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                            isSub ? -Offset : Offset, TII);
686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    MI.getOperand(i).ChangeToRegister(ARM::R12, false);
687a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola  }
6887bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola}
6897bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
6907bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::
691a8e2989ece6dc46df59b0768184028257f913843Evan ChengprocessFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
69275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  // This tells PEI to spill the FP as if it is any other callee-save register
69375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  // to take advantage the eliminateFrameIndex machinery. This also ensures it
69475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  // to combine multiple loads / stores.
69675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  bool CanEliminateFrame = true;
697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  bool CS1Spilled = false;
698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  bool LRSpilled = false;
699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned NumGPRSpills = 0;
700a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  SmallVector<unsigned, 4> UnspilledCS1GPRs;
701a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  SmallVector<unsigned, 4> UnspilledCS2GPRs;
70275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng
70375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  // Don't spill FP if the frame can be eliminated. This is determined
70475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  // by scanning the callee-save registers to see if any is used.
70575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  const unsigned *CSRegs = getCalleeSavedRegs();
70675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
70775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  for (unsigned i = 0; CSRegs[i]; ++i) {
70875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng    unsigned Reg = CSRegs[i];
70975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng    bool Spilled = false;
71075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng    if (MF.isPhysRegUsed(Reg)) {
71175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng      Spilled = true;
71275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng      CanEliminateFrame = false;
71375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng    } else {
71475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng      // Check alias registers too.
71575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
71675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        if (MF.isPhysRegUsed(*Aliases)) {
71775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng          Spilled = true;
71875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng          CanEliminateFrame = false;
719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        }
720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      }
72175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng    }
722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
72375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng    if (CSRegClasses[i] == &ARM::GPRRegClass) {
72475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng      if (Spilled) {
72575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        NumGPRSpills++;
72675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng
72775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
72875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        switch (Reg) {
72975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        case ARM::LR:
73075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng          LRSpilled = true;
73175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng          // Fallthrough
73275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        case ARM::R4:
73375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        case ARM::R5:
73475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        case ARM::R6:
73575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        case ARM::R7:
73675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng          CS1Spilled = true;
73775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng          break;
73875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        default:
73975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng          break;
74075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        }
74175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng      } else {
74275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        switch (Reg) {
74375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        case ARM::R4:
74475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        case ARM::R5:
74575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        case ARM::R6:
74675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        case ARM::R7:
74775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        case ARM::LR:
74875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng          UnspilledCS1GPRs.push_back(Reg);
74975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng          break;
75075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng        default:
75175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng          UnspilledCS2GPRs.push_back(Reg);
75275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng          break;
753a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        }
754a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      }
755a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
756a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
757a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
75875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  if (!CanEliminateFrame) {
759a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
76075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng    AFI->setHasStackFrame(true);
761a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
762a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
763a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
764a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (!LRSpilled && CS1Spilled) {
765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      MF.changePhyRegUsed(ARM::LR, true);
766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NumGPRSpills++;
767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
768a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
769a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
770a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // If stack and double are 8-byte aligned and we are spilling a odd number
772a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
773a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // the integer and double callee save areas.
774a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
775a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
776a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (CS1Spilled && !UnspilledCS1GPRs.empty())
777a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        MF.changePhyRegUsed(UnspilledCS1GPRs.front(), true);
778a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      else
779a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true);
780a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
781a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    MF.changePhyRegUsed(FramePtr, true);
782a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
783a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
784a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
785a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for
786a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2,
787a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care).
788a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
789a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                   MachineBasicBlock::iterator &MBBI,
790a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                   int Opc, unsigned Area,
791a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                                   const ARMSubtarget &STI) {
792a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  while (MBBI != MBB.end() &&
793a8e2989ece6dc46df59b0768184028257f913843Evan Cheng         MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
794a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (Area != 0) {
795a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      bool Done = false;
796a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned Category = 0;
797a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      switch (MBBI->getOperand(0).getReg()) {
79875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
799a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      case ARM::LR:
800a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        Category = 1;
801a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        break;
80275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
803970a419633ba41cac44ae636543f192ea632fe00Evan Cheng        Category = STI.isTargetDarwin() ? 2 : 1;
804a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        break;
80575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
80675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
807a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        Category = 3;
808a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        break;
809a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      default:
810a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        Done = true;
811a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        break;
812a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      }
813a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (Done || Category != Area)
814a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        break;
815a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
816a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
817a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    ++MBBI;
818a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
819a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
8207bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
8217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
822355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola  MachineBasicBlock &MBB = MF.front();
82344819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola  MachineBasicBlock::iterator MBBI = MBB.begin();
824355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola  MachineFrameInfo  *MFI = MF.getFrameInfo();
825a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
826a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  bool isThumb = AFI->isThumbFunction();
827a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
828a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
829a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned NumBytes = MFI->getStackSize();
830a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
831355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola
832a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  // Determine the sizes of each callee-save spill areas and record which frame
833a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  // belongs to which callee-save spill areas.
834a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
835a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  int FramePtrSpillFI = 0;
83675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  if (AFI->hasStackFrame()) {
837a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (VARegSaveSize)
838a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII);
839a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
840a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
841a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      unsigned Reg = CSI[i].getReg();
842a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      int FI = CSI[i].getFrameIdx();
843a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      switch (Reg) {
844a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      case ARM::R4:
845a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      case ARM::R5:
846a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      case ARM::R6:
847a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      case ARM::R7:
848a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      case ARM::LR:
849a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        if (Reg == FramePtr)
850a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          FramePtrSpillFI = FI;
851a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        AFI->addGPRCalleeSavedArea1Frame(FI);
852a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        GPRCS1Size += 4;
853a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        break;
854a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      case ARM::R8:
855a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      case ARM::R9:
856a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      case ARM::R10:
857a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      case ARM::R11:
858a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        if (Reg == FramePtr)
859a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          FramePtrSpillFI = FI;
860970a419633ba41cac44ae636543f192ea632fe00Evan Cheng        if (STI.isTargetDarwin()) {
861a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          AFI->addGPRCalleeSavedArea2Frame(FI);
862a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          GPRCS2Size += 4;
863a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        } else {
864a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          AFI->addGPRCalleeSavedArea1Frame(FI);
865a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          GPRCS1Size += 4;
866a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        }
867a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        break;
868a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      default:
869a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        AFI->addDPRCalleeSavedAreaFrame(FI);
870a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        DPRCSSize += 8;
871a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      }
872a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
873a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
874a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (!isThumb) {
875a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Build the new SUBri to adjust SP for integer callee-save spill area 1.
876a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII);
877a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
878a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    } else {
879a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
880a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        ++MBBI;
881a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
882a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
883a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Point FP to the stack slot that contains the previous FP.
884a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr)
885a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      .addFrameIndex(FramePtrSpillFI).addImm(0);
886a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
887a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (!isThumb) {
888a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Build the new SUBri to adjust SP for integer callee-save spill area 2.
889a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII);
890a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
891a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Build the new SUBri to adjust SP for FP callee-save spill area.
892a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
893a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII);
894a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
895a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
8967ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola
897a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  // If necessary, add one more SUBri to account for the call frame
898a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  // and/or local storage, alloca area.
89975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  if (MFI->hasCalls() && !hasFP(MF))
9001a009468175a6e123cc3f1e847c10e3e126a44dbRafael Espindola    // We reserve argument space for call sites in the function immediately on
9011a009468175a6e123cc3f1e847c10e3e126a44dbRafael Espindola    // entry to the current function.  This eliminates the need for add/sub
9021a009468175a6e123cc3f1e847c10e3e126a44dbRafael Espindola    // brackets around call sites.
90375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng    NumBytes += MFI->getMaxCallFrameSize();
9041b5076887e32f9a16a1f65f3ce9abf11c31abcd7Rafael Espindola
905a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  // Round the size to a multiple of the alignment.
906a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  NumBytes = (NumBytes+Align-1)/Align*Align;
9071a009468175a6e123cc3f1e847c10e3e126a44dbRafael Espindola  MFI->setStackSize(NumBytes);
9081a009468175a6e123cc3f1e847c10e3e126a44dbRafael Espindola
909a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  // Determine starting offsets of spill areas.
91075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  if (AFI->hasStackFrame()) {
911a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
912a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
913a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
914a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
915a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
916a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
917a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
918a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
919a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    NumBytes = DPRCSOffset;
920a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (NumBytes) {
921a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Insert it after all the callee-save spills.
922a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (!isThumb)
923a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
924a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
925a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
926a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  } else
927a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
92815f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola
929a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
930a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
931a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
932a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
9337ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola
934a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
935a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  for (unsigned i = 0; CSRegs[i]; ++i)
936a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (Reg == CSRegs[i])
937a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      return true;
938a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  return false;
939a8e2989ece6dc46df59b0768184028257f913843Evan Cheng}
940a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
941a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
942a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  return ((MI->getOpcode() == ARM::FLDD ||
943a8e2989ece6dc46df59b0768184028257f913843Evan Cheng           MI->getOpcode() == ARM::LDR  ||
944a8e2989ece6dc46df59b0768184028257f913843Evan Cheng           MI->getOpcode() == ARM::tLDRspi) &&
945a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          MI->getOperand(1).isFrameIndex() &&
946a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
9477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola}
9487bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
9497bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
9507bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola				   MachineBasicBlock &MBB) const {
951355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola  MachineBasicBlock::iterator MBBI = prior(MBB.end());
952a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  assert((MBBI->getOpcode() == ARM::BX_RET ||
953a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          MBBI->getOpcode() == ARM::tBX_RET ||
954a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          MBBI->getOpcode() == ARM::tPOP_RET) &&
955355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola         "Can only insert epilog into returning blocks");
956355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola
957355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola  MachineFrameInfo *MFI = MF.getFrameInfo();
958a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
959a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  bool isThumb = AFI->isThumbFunction();
960a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
961a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  int NumBytes = (int)MFI->getStackSize();
96275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng  if (AFI->hasStackFrame()) {
963a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Unwind MBBI to point to first LDR / FLDD.
964a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    const unsigned *CSRegs = getCalleeSavedRegs();
965a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (MBBI != MBB.begin()) {
966a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      do
967a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        --MBBI;
968a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
969a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (!isCSRestore(MBBI, CSRegs))
970a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        ++MBBI;
971a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
972355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola
973a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    // Move SP to start of FP callee save spill area.
974a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
975a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                 AFI->getGPRCalleeSavedArea2Size() +
976a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                 AFI->getDPRCalleeSavedAreaSize());
977a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (isThumb)
978a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
979a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    else {
980a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
981a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Reset SP based on frame pointer only if the stack frame extends beyond
982a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // frame pointer stack slot.
983a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      if (AFI->getGPRCalleeSavedArea2Size() ||
984a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          AFI->getDPRCalleeSavedAreaSize()  ||
985a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          AFI->getDPRCalleeSavedAreaOffset())
986a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        if (NumBytes)
987a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
988a8e2989ece6dc46df59b0768184028257f913843Evan Cheng            .addImm(NumBytes);
989a8e2989ece6dc46df59b0768184028257f913843Evan Cheng        else
990a8e2989ece6dc46df59b0768184028257f913843Evan Cheng          BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tMOVrr : ARM::MOVrr),
991a8e2989ece6dc46df59b0768184028257f913843Evan Cheng                  ARM::SP).addReg(FramePtr);
9927ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola
993a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Move SP to start of integer callee save spill area 2.
994a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
995a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII);
99615f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola
997a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Move SP to start of integer callee save spill area 1.
998a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
999a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII);
1000a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
1001a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      // Move SP to SP upon entry to the function.
1002a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1003a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII);
1004a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    }
1005a8e2989ece6dc46df59b0768184028257f913843Evan Cheng
1006a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    if (VARegSaveSize)
1007a8e2989ece6dc46df59b0768184028257f913843Evan Cheng      emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII);
1008a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  } else if (NumBytes != 0) {
1009a8e2989ece6dc46df59b0768184028257f913843Evan Cheng    emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
1010a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  }
10117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola}
10127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
10137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const {
1014a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  return ARM::LR;
10157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola}
10167bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
10177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1018a8e2989ece6dc46df59b0768184028257f913843Evan Cheng  return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11;
10197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola}
10207bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
10217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc"
10227bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola
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