ARMRegisterInfo.cpp revision 9312313a56ca3d4d904e8f7e9b4fe152a293eae1
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 28b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 307ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 31a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 34a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <iostream> 357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 37a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 38a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 39a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 40a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 41a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 43a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng std::cerr << "Unknown ARM register!\n"; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 7515f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 7615f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 7715f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 78a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 79a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 80c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 81a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 82a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) { 83a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 84a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 85a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 86a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 88a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 89a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 90a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 91a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MIB.addReg(CSI[i-1].getReg()); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 105a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1079d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1139d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1149d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1159d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1237bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1257bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1267bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 133a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::tSTRspi)).addReg(SrcReg) 134a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg) 137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 138a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg) 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 143a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg) 144a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1487bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1497bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1507bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1517bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::tLDRspi), DestReg) 157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1697bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1707bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1717bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr), 179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng DestReg).addReg(SrcReg); 180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 181c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); 182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 183c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg); 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 1867bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1877bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 188a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 191a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::MOVrr: { 195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 196a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 197a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 198a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(0).addImm(0); 199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 200a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::tMOVrr: { 207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::tSTRspi)).addReg(SrcReg).addFrameIndex(FI) 210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::tLDRspi), DstReg).addFrameIndex(FI) 214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0); 226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 230a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 236a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0); 237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 239a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 240a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 241a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 242a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 243a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 2457bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 247c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 248c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 249a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 255ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 261a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 264a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 265970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 2660f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 2670f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 2680f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 269c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 270c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 274a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 278ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 279c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 2800f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 2810f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 282a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 286dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 287a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 288a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 289a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 29036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 292a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 293a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 298a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 299a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 300a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 301a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 303a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 304a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 305a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 306a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 307a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 308a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 309a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 310a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 311a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 312a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 313a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 314a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(BaseReg).addImm(SOImmVal); 315a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 316a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 317a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 318a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 319a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 320a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 321a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isLowRegister(unsigned Reg) { 322a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 323a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Reg) { 324a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case R1: case R2: case R3: 325a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case R5: case R6: case R7: 326a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 327a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 328a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 329a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 330a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 331a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 33236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 33336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 33436640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 33536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 33636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 33736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 33836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 33936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 34036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 34136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 34236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 34336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 34436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Scale = 1; 34536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 34636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 34736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 34836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 34936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 35036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 35136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 35236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 35336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 35436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 35536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 35636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusConstPool - Emits a series of instructions to materialize 35736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Load the immediate from a 35836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 35936640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 36036640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengvoid emitThumbRegPlusConstPool(MachineBasicBlock &MBB, 36136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 36236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 36336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int NumBytes, const TargetInstrInfo &TII) { 36436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineFunction &MF = *MBB.getParent(); 36536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 36636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isHigh = !isLowRegister(DestReg) || !isLowRegister(BaseReg); 36736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 36836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 36936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // if either base or dest register is a high register. 37036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumBytes < 0 && !isHigh) { 37136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 37236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 37336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 37436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes); 37536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 37636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 37736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 37836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 37936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 38036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3); 38136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 38236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Load the constant. 38336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), LdReg).addConstantPoolIndex(Idx); 38436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 38536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 38636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 38736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 38836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(BaseReg).addReg(LdReg); 38936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 39036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(LdReg).addReg(BaseReg); 39136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 39236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12); 39336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 39436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 39536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 396a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 397a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 398a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 399a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 400a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 401a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 402a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 403a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 404a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 405a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 406a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 40736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool DstNeBase = false; 408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 4095b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 41036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 41136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 412a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 413a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 414a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 415a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 4165b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 417a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 418a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 419a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 4205b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 4215b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 4225b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 4235b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 425a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 426a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 427a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 428a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 4295b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 430a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 431a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 43236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 43336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 43436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 43536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 43636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng DstNeBase = true; 437a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 438a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 439a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 440a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 441a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 44236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 44336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 4 : 3; 44436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 44536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 44636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 44736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng emitThumbRegPlusConstPool(MBB, MBBI, DestReg, BaseReg, NumBytes, TII); 44836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 44936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 45036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 45136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DstNeBase) { 45236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 45336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 45436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 45536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 45636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 45736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 45836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng .addReg(BaseReg).addImm(ThisVal); 45936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 46036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg); 46136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 46236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 46336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 46436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 4655b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 466a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 467a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 4685b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 4695b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 470a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 471a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 4723fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 473a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 474a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal); 475a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 476a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 477a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 478a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 479a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 480a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 481a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 4825b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 4835b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 484a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 485a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 486a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 487a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 488a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 489a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 490a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 491a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg) 492a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 493a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 495a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 496a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 497a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, bool isThumb, const TargetInstrInfo &TII) { 498a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 499a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 500a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 501a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 502a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 503a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5047bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 5057bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 5067bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 50775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (hasFP(MF)) { 508a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 509a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 510a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 511b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 512b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 513b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 514a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 515a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 516a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 517a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 518b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 519b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 520b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 521a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 522b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) { 523a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII); 524b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 525b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola assert(Old->getOpcode() == ARM::ADJCALLSTACKUP); 526a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII); 527b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 528b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 5297ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 5307bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 5317bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 5327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 534a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 535a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 536a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 537a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 538a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 539a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 541a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal); 546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 547a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 548a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg).addReg(DestReg); 550a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 551a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 552a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 55458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 55558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 55658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 557a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 55958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 560a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 561a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 562a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 563a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 565a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 566a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 567a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 568a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.getFrameInfo()->getStackSize(); 56958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 570a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 571a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 572a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 573a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 574a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 575a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 57675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 577a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 578a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 579a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 580b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 582a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 583a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 584a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 585a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 586a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 587a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 588a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 589a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 590a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 592a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVrr)); 593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 594a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 595a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 596a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 597a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 598a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 599a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 600a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 60158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 602a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 603a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 604a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 605a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 607a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 608a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 609a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 610a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 611a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 612a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 613a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 614a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 615a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31); 616a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 617a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 619a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 620a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 621a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 623a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 624a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 626a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((Offset & 3) == 0 && 62786eb5153594b523e0b201735e14c92785d7ba601Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 628a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset >>= 2; 629a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 630a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 631a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVrr)); 632a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 633a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 634a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 635a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 636a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 638a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((Offset & ~255U) == 0) { 639a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset); 642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 643a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 644a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 645a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 649a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 650a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 651a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(255); 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = (Offset - 255) << 2; 653a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 655a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 656a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 657a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset <<= 2; 660a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 661a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 662a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false); 663a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 665a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 666a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 668a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 669a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 670a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 672a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 673a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 674a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 675a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 676a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 677a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 679a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 687a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 688a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 689a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 690a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 692a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 693a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 694a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 696a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 700a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 701a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 702a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 703a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 704a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 705a8e2989ece6dc46df59b0768184028257f913843Evan Cheng std::cerr << "Unsupported addressing mode!\n"; 706a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 707a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 708a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 70958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 710a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 7119312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 712a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset < 0) { 713a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 714a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 715a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 71658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 717a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = Offset / Scale; 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Mask = (1 << NumBits) - 1; 720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 721a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 725a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 726a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 727a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 72858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 72936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immediate. 7305b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (AddrMode == ARMII::AddrModeTs) { 7315b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use a 7325b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // different base register. 7335b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng NumBits = 5; 7345b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Mask = (1 << NumBits) - 1; 7355b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng } 7365b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng 737a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset = ImmedOffset & Mask; 738a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 739a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 740a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 741a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~(Mask*Scale); 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 745a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 746a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 747a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 74858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 750a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 751a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 752a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 753a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, 754a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 7555b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 756a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 7575b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 758a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 759a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 760a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 761a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 762a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 763a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 764a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // str r12, r2 766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 7675b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 768a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 7695b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 770a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2); 771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 772a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 773a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, 774a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 7755b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 7765b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 7775b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 7785b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) 779a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12); 780a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 781a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 782a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 783a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 784a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 785a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 786a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 787a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg, 788a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 789a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(ARM::R12, false); 790a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 7917bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 7927bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 7937bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 794a8e2989ece6dc46df59b0768184028257f913843Evan ChengprocessFunctionBeforeCalleeSavedScan(MachineFunction &MF) const { 79575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 79675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 79775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 798a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 79975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 800a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 801a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 802a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 803a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 804a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 80575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 80675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 80775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 80875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 80975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 81075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 81175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 81275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 81375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 81475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 81575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 81675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 81775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 81875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 81975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 82075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 82175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 822a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 823a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 82475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 825a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 82675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 82775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 82875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 82975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 830c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 831c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 832c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 833c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else 834c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng CS1Spilled = true; 835c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 836c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 837c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 83875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 83975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 84075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 84175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 84275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 84375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 84475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 84575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 84675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 84775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 84875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 84975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 85075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 85175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 85275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 853c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 854c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 855c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 856c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 857c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 85875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 85975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 86075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 86175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 86275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 86375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 86475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 86575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 86675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 86775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 86875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 869a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 870a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 871a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 872a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 873a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 87478268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 875d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 876d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 877d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 878d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // Force LR spill if the Thumb function size is > 2048. This enables the 879d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 880d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // the branch fix up path will undo it. 881d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 882d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 883d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 884d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 885d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 886d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 8877588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 88875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 889a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 890a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 891a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 892a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 893a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(ARM::LR, true); 894a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 895a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 896a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 897d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 898a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 899a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 9003548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 9013548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 9027588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 9033548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng MF.changePhyRegUsed(FramePtr, true); 9043548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 9053548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 9063548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 907c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng // If stack and double are 8-byte aligned and we are spilling an odd number 908a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of GPRs. Spill one extra callee save GPR so we won't have to pad between 909a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // the integer and double callee save areas. 910a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 911a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TargetAlign == 8 && (NumGPRSpills & 1)) { 912a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (CS1Spilled && !UnspilledCS1GPRs.empty()) 913a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS1GPRs.front(), true); 914c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else if (!UnspilledCS2GPRs.empty()) 915a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true); 916a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 917a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 91878268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 919d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 920d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng MF.changePhyRegUsed(ARM::LR, true); 921d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng AFI->setLRIsForceSpilled(true); 922d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 923a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 924a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 925a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 926a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 927a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 928a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 929a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 930a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 931a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 932a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 933a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 934a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 935a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 936a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 937a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 93875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 939a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 940a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 941a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 94275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 943970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 944a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 94575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 94675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 947a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 948a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 949a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 950a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 951a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 952a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 953a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 954a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 955a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 956a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 957a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 958a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 959a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 9607bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 9617bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 962355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 96344819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 964355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 965a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 966a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 967a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 968a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 969a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 970a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 971355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 972236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 973236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 974236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 975236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 976236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 977236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 978a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 979a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 980a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 981a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 982236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 983236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 984236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 985236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 986236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 987236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 988236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (VARegSaveSize) 989236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII); 990236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 991236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 992236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 993236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 994236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 995236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 996236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 997236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 998236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 999236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1000236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1001236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1002236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1003236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1004236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1005236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1006236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1007236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1008236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1009236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1010236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1011236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1012236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1013236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1014236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1015a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1016a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1017a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1018236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1019236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1020236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1021236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1022a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1023236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1024a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1025236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Align == 8 && (GPRCS1Size & 7) != 0) 1026236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Pad CS1 to ensure proper alignment. 1027236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1028c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 1029236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1030236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1031236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII); 1032236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1033236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1034236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1035a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 10363548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 10373548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 10383548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 1039236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr) 1040236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 1041a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1042236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1043236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1044236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII); 1045a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1046236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1047236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 1048236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII); 1049a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 10507ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1051a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1052236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1053236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1054236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1055236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1056236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1057236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1058236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1059a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1060236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1061236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1062236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1063236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1064236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 1065a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1066236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 106715f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1068a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1069a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1070a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1071a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 10727ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1073a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1074a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1075a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1076a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1077a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1078a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1079a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1080a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1081a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1082a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 1083a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::tLDRspi) && 1084a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1085a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 10867bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 10877bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 10887bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 10897bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock &MBB) const { 1090355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1091a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1092a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1093a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1094355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1095355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1096355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1097a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1098a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1099a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1101236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1102236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 11033df62bde9b3f2557cccfa1f18d25b57bf0477f60Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 1104236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1105236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 110615f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1107236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Unwind MBBI to point to first LDR / FLDD. 1108236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 1109236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (MBBI != MBB.begin()) { 1110236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng do 1111236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng --MBBI; 1112236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1113236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isCSRestore(MBBI, CSRegs)) 1114236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1115236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1117236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of FP callee save spill area. 1118236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1119236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getGPRCalleeSavedArea2Size() + 1120236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaSize()); 11219d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isThumb) { 11229d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (MBBI->getOpcode() == ARM::tBX_RET && 11239d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng &MBB.front() != MBBI && 11249d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng prior(MBBI)->getOpcode() == ARM::tPOP) { 11259d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng MachineBasicBlock::iterator PMBBI = prior(MBBI); 11269d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII); 11279d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else 11289d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 11299d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 11303548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 11313548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 11323548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 1133236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1134236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Reset SP based on frame pointer only if the stack frame extends beyond 1135236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // frame pointer stack slot. 1136236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (AFI->getGPRCalleeSavedArea2Size() || 1137236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaSize() || 1138236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaOffset()) 1139236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1140236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 1141236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addImm(NumBytes); 1142236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 1143236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr); 1144236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (NumBytes) { 1145236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, false, TII); 1146a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 11473548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1148236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of integer callee save spill area 2. 1149236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 1150236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII); 1151236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1152236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of integer callee save spill area 1. 1153236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 1154236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII); 1155236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1156236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to SP upon entry to the function. 1157236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 1158236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII); 1159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1160236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 11619d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 11629d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 11639d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 11649d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1165236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII); 11669d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 11679d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng MBB.erase(MBBI); 11689d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 11697bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11707bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 11717bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 11737bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11747bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 11757bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11; 11777bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11787bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 11797bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 11807bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1181