ARMRegisterInfo.cpp revision 9f8e50d4ed7dcc5ca0f137830ff1185b2afa38bf
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 285ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng#include "llvm/CodeGen/RegisterScavenging.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 30b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 317ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 32b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 35ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng#include "llvm/Support/CommandLine.h" 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 39ead75905813e175898677cb8c4e4cc919ad2782dEvan Chengstatic cl::opt<bool> EnableScavenging("enable-arm-reg-scavenging", cl::Hidden, 40ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng cl::desc("Enable register scavenging on ARM")); 41ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng 42a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 43a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 76a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 788fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 79a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 8015f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 8115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 8215f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 83a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 84a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 85c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 86a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) { 881b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng RS = (EnableScavenging) ? new RegScavenger() : NULL; 895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng} 905ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng 915ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan ChengARMRegisterInfo::~ARMRegisterInfo() { 925ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng delete RS; 935ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng} 945ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng 95a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 104ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 105ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng unsigned Reg = CSI[i-1].getReg(); 106ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng // Add the callee-saved register as live-in. It's killed at the spill. 107ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MBB.addLiveIn(Reg); 108ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); 109ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng } 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 113a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1219d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 123a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 124a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 125a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1279d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1289d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1299d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 133a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 134a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1407bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 143a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 144a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 146a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 147ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true) 148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 150ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true) 151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 153ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true) 154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 157ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true) 158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1607bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1617bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1627bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1637bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1647bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1657bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1708e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 181a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1837bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1847bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1857bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 191a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr), 193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng DestReg).addReg(SrcReg); 194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 195c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); 196a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 197c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg); 198a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 2007bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2017bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 20240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 20340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 20440984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 20540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 20640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 20740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 20840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 20940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 21040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 21140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 21240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 21340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 21440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 215a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::MOVrr: { 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(0).addImm(0); 226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 230a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::tMOVrr: { 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 236bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 2378e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 23840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2398e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 240a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 241a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 242a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 243bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 2448e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 24540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2468e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 247a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 248a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 249a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0); 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 261a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 264a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 265a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0); 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 274a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 2787bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2797bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 280c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 281c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 282a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 286a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 287a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 288ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 289a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 298970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 2990f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3000f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 3010f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 302c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 303c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 304a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 305a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 306a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 307a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 308a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 309a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 310a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 311ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 312c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 3130f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3140f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 315b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 316c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // FIXME: avoid re-calculating this everytime. 317b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 318b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::SP); 319ad78ef215485389bb5c5698fa6f1ac670f0076d8Evan Cheng Reserved.set(ARM::PC); 320b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 321b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(FramePtr); 322b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // Some targets reserve R9. 323b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isR9Reserved()) 324b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::R9); 325b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // At PEI time, if LR is used, it will be spilled upon entry. 326b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR)) 327b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::LR); 328b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 329b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 330b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 33136230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Chengbool 33236230cdda48edf6c634f2dcf69f9d78ac5a17377Evan ChengARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 33336230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 33436230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng return EnableScavenging && !AFI->isThumbFunction(); 3351b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng} 3361b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng 337a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 338a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 339a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 340a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 341dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 342a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 343a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 344a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 34536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 346a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 347a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 348a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 349a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 350a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 351a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 352a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 353a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 354a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 355a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 356a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 357a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 358a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 359a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 360a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 361a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 362a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 363a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 364a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 365a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 366a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 367a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 368a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 3695ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(SOImmVal); 370a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 371a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 372a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 373a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 37436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 37536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 37636640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 37736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 37836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 37936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 38036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 38136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 38236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 38336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 38436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 38536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 38636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Scale = 1; 38736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 38836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 38936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 39036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 39136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 39236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 39336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 39436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 39536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 39636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 39736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 3987142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize NumBytes 3997142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// immediate. 4007142f8755a07512d909d288f74a3f1ffa9c1411aEvan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 4017142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineBasicBlock::iterator &MBBI, 4027142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned DestReg, int NumBytes, 4037142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng const TargetInstrInfo &TII) { 4047142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineFunction &MF = *MBB.getParent(); 4057142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 4067142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes); 4077142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 4087142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx); 4097142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng} 4107142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 411403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 412403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 413403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 41436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 41536640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 416403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 41736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 41836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 419a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 420a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 4217142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 4227142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 42336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 42436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 425a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 426a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 427a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 428a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 42936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 43036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 43136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 43236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 43336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 43436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 43536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 4365ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12) 4375ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 43836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 439a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 440a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 441a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4428bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 4438bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4445ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) 4455ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(LdReg, false, false, true); 4468bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 4477142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII); 4487142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 44936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 45036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 45136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 4525ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng if (DestReg == ARM::SP || isSub) 4535ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(BaseReg).addReg(LdReg, false, false, true); 45436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 4555ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(LdReg).addReg(BaseReg, false, false, true); 45636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 4575ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3) 4585ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 45936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 46036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 46136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 462a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 463a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 464a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 465a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 466a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 467a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 468a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 469a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 470a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 471a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 472a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 4738e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 474a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 4755b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 47636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 47736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 478a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 479a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 480a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 481a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 4825b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 483a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 484a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 485a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 4865b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 4875b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 4885b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 4895b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 490a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 491a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 492a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 493a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 4955b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 496a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 497a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 49836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 49936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 50036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 50136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 5028e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 503a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 504a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 505a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 506a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 507a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 50836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 5098e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 51036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 51136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 51236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 513403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 51436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 51536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 51636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5178e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 51836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 51936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 52036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 52136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 52236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 52336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 5245ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(ThisVal); 52536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 5265ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg) 5275ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true); 52836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 52936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 53036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 53136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5325b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 534a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 5355b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 5365b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 537a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 538a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 5393fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 5415ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng bool isKill = BaseReg != ARM::SP; 5425ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg) 5435ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, isKill).addImm(ThisVal); 544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 547a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 548a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 550a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 5515b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 5525b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 554a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 555a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 556a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 557a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 559a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 5605ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg) 5615ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true) 562a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 563a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 565a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 566a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 567a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, bool isThumb, const TargetInstrInfo &TII) { 568a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 569a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 570a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 571a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 572a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 573a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5747bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 5757bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 5767bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 57775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (hasFP(MF)) { 578a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 579a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 580a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 581b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 582b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 583b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 584a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 585a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 586a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 587a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 588b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 589b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 590b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 592b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) { 593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII); 594b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 595b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola assert(Old->getOpcode() == ARM::ADJCALLSTACKUP); 596a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII); 597b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 598b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 5997ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 6007bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 6017bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 6027bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 603a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 604a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 605a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 607a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 608a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 609a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 610a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 611a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 612a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 613a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 614a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 615a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal); 616a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 617a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 6195ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg) 6205ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true); 621a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 623c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// findScratchRegister - Find a 'free' ARM register. If register scavenger 624c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// is not being used, R12 is available. Otherwise, try for a call-clobbered 625c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// register first and then a spilled callee-saved register if that fails. 626c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengstatic 627c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengunsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 628c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng ARMFunctionInfo *AFI) { 629c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12; 630c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng if (Reg == 0) 631c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // Try a already spilled CS register. 632c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters()); 633c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 634c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng return Reg; 635c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng} 636c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 6371b051fc6a491c40cf3f926c089ad082938b653f0Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 6381b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng RegScavenger *RS) const{ 639a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 64058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 64158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 64258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 643a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 644a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 64558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 649a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 650a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 651a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 653a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.getFrameInfo()->getStackSize(); 65558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 656a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 657a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 660a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 661a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 66275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 663a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 665a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 666b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 668a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 669a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 670a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 672a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 673a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 674a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 675a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 676a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 677a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVrr)); 679a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 68758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 688a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 689a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 690a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 692a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 693a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 694a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 696a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 700a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 701a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31); 702a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 703a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 704a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 705a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 706a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 707a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 708a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 709a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 710a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 711a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 712a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((Offset & 3) == 0 && 71386eb5153594b523e0b201735e14c92785d7ba601Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 714a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 715a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 716a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVrr)); 717a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 721a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 723a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (((Offset >> 2) & ~255U) == 0) { 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 725a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 726a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset >> 2); 727a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 728a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 729a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 730a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 731a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 732a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, 8, 1); 733a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 734a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 735a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 73688b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 737a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 738a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 739a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 740a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 741a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 745a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 746a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(255); 747a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng Offset = (Offset - 255 * 4); 748a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 750a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 751a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 752a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 753a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 754a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 755a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 7565ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); 757a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 758a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 759a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 760a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 761a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 762a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 763a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 764a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 768a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 769a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 770a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 772a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 773a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 774a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 775a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 776a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 777a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 778a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 779a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 780a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 781a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 782a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 783a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 784a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 785a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 786a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 787a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 788a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 789a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 790a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 791a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 792a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 793a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 7947142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 7957142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 796a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 797a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 798a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 7998fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 800a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 801a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 802a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 80358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 804a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 8059312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 806a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 807a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 808a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 809a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 81058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 811a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 8128e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 8138e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 8148e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 8158e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 8168e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 8178e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 8188e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 8198e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 8208e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 8218e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 8228e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 82388b633165a20398d1015eec561856500fcf30d7dEvan Cheng 8245ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 8255ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 8265ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 8275ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 8285ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 8295ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 8305ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 831a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 832a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 8335ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 8345ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 8355ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 83688b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 83788b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 838a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 839a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 840a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 84188b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 842a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 843a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 844a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 845a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 846a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 847a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 848a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 84958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 850a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 851a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 852a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 853a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 8547142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 8557142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 8567142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 857403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 8587142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 8597142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 8607142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 8617142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 8627142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 863a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8645b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 8655ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 8667142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 8677142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 8687142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 8695ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 870a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 871a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 872a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 873a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 874a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 875a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 876a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 8778bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 878a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 8795b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 880a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 8817142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 8825b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 8835ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12) 8845ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R2, false, false, true); 885a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 886a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 887f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 8885ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12) 8895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 8907142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 8917142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 892403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 8937142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 8947142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 8957142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 8967142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 8977142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 898a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8995b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 9005ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 9017142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 9027142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 9037142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 9047142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 9058bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 9068bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 9078bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 9085ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2) 9095ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 910f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 9115ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3) 9125ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 913a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 914a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 915a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 916a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 917a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 918a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 919a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 920c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); 921c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng assert(ScratchReg && "Unable to find a free register!"); 9221b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, 923a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 9241b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 925a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 9267bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 9277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 9287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 929a8e2989ece6dc46df59b0768184028257f913843Evan ChengprocessFunctionBeforeCalleeSavedScan(MachineFunction &MF) const { 93075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 93175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 93275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 933a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 93475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 935a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 936a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 937a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 938a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 939a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 940f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 94175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 94275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 94375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 94475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 94575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 94675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 94775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 94875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 94975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 950f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 95175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 95275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 95375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 95475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 95575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 95675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 95775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 95875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 959a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 960a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 96175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 962a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 96375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 96475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 96575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 96675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 967c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 968c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 969c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 970c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else 971c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng CS1Spilled = true; 972c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 973c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 974c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 97575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 97675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 97775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 97875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 97975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 98075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 98175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 98275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 98375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 98475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 98575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 98675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 98775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 98875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 98975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 990c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 991c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 992c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 993c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 994c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 99575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 99675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 99775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 99875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 99975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 100075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 100175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 100275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 100375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 100475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 100575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 1006a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1007a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1008a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1009a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1010a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1011d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 1012d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 1013d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 1014f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // Force LR to be spilled if the Thumb function size is > 2048. This enables 1015d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 1016f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // then the branch fix up path will undo it. 1017d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 1018d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 1019d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 1020d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1021d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1022d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 10237588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 102475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 1025a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1026a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1027a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1028a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 1029a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(ARM::LR, true); 1030f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1031a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 1032a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1033a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1034d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 1035a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1036a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 10373548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 10383548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 10397588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 10403548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng MF.changePhyRegUsed(FramePtr, true); 10413548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 10423548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 10433548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1044c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng // If stack and double are 8-byte aligned and we are spilling an odd number 1045a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of GPRs. Spill one extra callee save GPR so we won't have to pad between 1046a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // the integer and double callee save areas. 1047a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1048a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1049f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1050f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng unsigned Reg = UnspilledCS1GPRs.front(); 1051f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng MF.changePhyRegUsed(Reg, true); 1052f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 1053f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng } else if (!UnspilledCS2GPRs.empty()) { 1054f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng unsigned Reg = UnspilledCS2GPRs.front(); 1055f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng MF.changePhyRegUsed(Reg, true); 1056f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 1057f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng } 1058a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1059a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 106078268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 1061d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 1062d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng MF.changePhyRegUsed(ARM::LR, true); 1063f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1064f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setLRIsSpilledForFarJump(true); 1065d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1066a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1067a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1068a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 1069a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 1070a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 1071a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1072a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1073a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1074a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1075a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1076a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1077a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1078a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1079a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1080a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 108175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1082a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1083a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1084a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 108575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1086970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1087a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 108875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 108975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1090a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1091a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1092a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1093a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1094a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1095a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1096a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1097a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1098a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1099a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 11037bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 11047bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1105355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 110644819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1107355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1114355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1115236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 11168bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 11178bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 11188bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 11198bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 11208bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 11218bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 11228bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 11238bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 11248bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1125236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1126236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1127236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1128236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1129236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1133a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1134acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1135acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (VARegSaveSize) 1136acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII); 1137acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1138236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1139236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 1140236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1141236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1142236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1143236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1144236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1145236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1146236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1147236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1148236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1149236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1150236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1151236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1152236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1153236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1154236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1155236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1156236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1157236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1158236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1159236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1160236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1161236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1162236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1163236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1164236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1165236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1166236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1167236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1170a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1171236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1172236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1173236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1174236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1176236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1178236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Align == 8 && (GPRCS1Size & 7) != 0) 1179236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Pad CS1 to ensure proper alignment. 1180236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1181c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 1182236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1183236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1184236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII); 1185236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1186236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1187236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 11893548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 11903548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 11913548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 1192236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr) 1193236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 1194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1195236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1196236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1197236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII); 1198a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1199236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1200236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 1201236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII); 1202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 12037ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1205236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1206236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1207236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1208236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1209236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1210236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1211236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1213236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1214236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1215236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1216236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1217236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 1218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1219236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 122015f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 12257ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1226a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1230a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1233a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 12368e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 12397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12407bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 12427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock &MBB) const { 1243355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1247355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1248355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1249355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1254236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1255236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 12563df62bde9b3f2557cccfa1f18d25b57bf0477f60Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 12579d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 1258acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Unwind MBBI to point to first LDR / FLDD. 1259acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio const unsigned *CSRegs = getCalleeSavedRegs(); 1260acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI != MBB.begin()) { 1261acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio do 1262acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio --MBBI; 1263acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1264acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (!isCSRestore(MBBI, CSRegs)) 1265acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio ++MBBI; 1266acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1267acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1268acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of FP callee save spill area. 1269acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1270acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getGPRCalleeSavedArea2Size() + 1271acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize()); 1272acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (isThumb) { 1273acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (hasFP(MF)) { 1274acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1275acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1276acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1277236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1278acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 1279236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 1280acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::SP).addReg(FramePtr); 1281acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1282acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI->getOpcode() == ARM::tBX_RET && 1283acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio &MBB.front() != MBBI && 1284acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio prior(MBBI)->getOpcode() == ARM::tPOP) { 1285acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio MachineBasicBlock::iterator PMBBI = prior(MBBI); 1286acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII); 1287acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else 1288acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 1289acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1290acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1291acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Darwin ABI requires FP to point to the stack slot that contains the 1292acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // previous FP. 12939f8e50d4ed7dcc5ca0f137830ff1185b2afa38bfDale Johannesen if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) { 1294acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1295acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1296acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1297acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (AFI->getGPRCalleeSavedArea2Size() || 1298acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize() || 1299acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 1300acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio hasFP(MF)) 1301acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (NumBytes) 1302acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 1303acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio .addImm(NumBytes); 1304acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio else 1305acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr); 1306acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else if (NumBytes) { 1307acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, NumBytes, false, TII); 1308acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 13093548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1310acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 2. 1311acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 1312acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII); 1313236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1314acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 1. 1315acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 1316acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII); 1317236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1318acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to SP upon entry to the function. 1319acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 1320acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII); 1321acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1322a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1323236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 13249d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1325f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1326f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1327f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1328f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1329f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1330236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII); 1331f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1332f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1333f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1334f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1335f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 13369d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 13377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 13387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 13397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1340a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 13417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 13427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 13437bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1344a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11; 13457bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 13467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 134762819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHExceptionRegister() const { 134862819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception register"); 134962819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 135062819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 135162819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 135262819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHHandlerRegister() const { 135362819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception handler register"); 135462819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 135562819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 135662819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 13577bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 13587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1359