ARMRegisterInfo.cpp revision a01faf4a7ac34b2b89c93d62d3159a5c9c421149
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 28b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 307ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 31a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 34a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <iostream> 357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 37a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 38a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 39a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 40a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 41a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 43a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng std::cerr << "Unknown ARM register!\n"; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 7515f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 7615f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 7715f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 78a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 79a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 80c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 81a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 82a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) { 83a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 84a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 85a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 86a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 88a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 89a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 90a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 91a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MIB.addReg(CSI[i-1].getReg()); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 105a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1079d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1139d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1149d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1159d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1237bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1257bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1267bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1338e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg) 134a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg) 137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 138a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg) 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 143a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg) 144a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1487bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1497bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1507bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1517bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1568e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1697bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1707bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1717bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr), 179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng DestReg).addReg(SrcReg); 180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 181c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); 182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 183c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg); 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 1867bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1877bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 18840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 18940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 19040984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 19140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 19240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 19340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 19440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 19540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 19640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 19740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 19840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 19940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 20040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 201a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::MOVrr: { 208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(0).addImm(0); 212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::tMOVrr: { 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 22240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng if (!isLowRegister(SrcReg)) 2238e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 22440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2258e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 22940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng if (!isLowRegister(DstReg)) 2308e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 23140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2328e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 236a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 239a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 240a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 241a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 242a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 243a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0); 245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 247a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 248a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 249a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0); 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 261a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 2647bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2657bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 266c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 267c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 274ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 280a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 281a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 282a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 284970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 2850f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 2860f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 2870f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 288c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 289c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 297ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 298c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 2990f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3000f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 301a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 303a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 304a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 305dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 306a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 307a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 308a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 30936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 310a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 311a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 312a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 313a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 314a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 315a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 316a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 317a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 318a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 319a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 320a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 321a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 322a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 323a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 324a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 325a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 326a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 327a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 328a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 329a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 330a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 331a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 332a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 333a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(BaseReg).addImm(SOImmVal); 334a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 335a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 336a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 337a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 33836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 33936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 34036640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 34136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 34236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 34336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 34436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 34536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 34636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 34736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 34836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 34936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 35036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Scale = 1; 35136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 35236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 35336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 35436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 35536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 35636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 35736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 35836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 35936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 36036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 36136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 36236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusConstPool - Emits a series of instructions to materialize 36336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Load the immediate from a 36436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 36536640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 36636640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengvoid emitThumbRegPlusConstPool(MachineBasicBlock &MBB, 36736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 36836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 369a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 370a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 37136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineFunction &MF = *MBB.getParent(); 37236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 37336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isHigh = !isLowRegister(DestReg) || !isLowRegister(BaseReg); 37436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 37536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 376a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 377a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 378a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 379a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 38036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 38136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 38236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 38336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 38436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 38536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 38636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 38736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3); 38836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 389a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 390a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 391a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 392a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng else { 393a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Load the constant. 394a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes); 395a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 396a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), LdReg).addConstantPoolIndex(Idx); 397a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng } 39836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 39936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 40036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 40136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 40236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(BaseReg).addReg(LdReg); 40388b633165a20398d1015eec561856500fcf30d7dEvan Cheng else if (isSub) 40488b633165a20398d1015eec561856500fcf30d7dEvan Cheng MIB.addReg(BaseReg).addReg(LdReg); 40536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 40636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(LdReg).addReg(BaseReg); 40736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 40836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12); 40936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 41036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 41136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 412a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 413a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 414a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 415a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 416a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 417a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 418a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 419a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 420a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 421a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 422a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 4238e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 4255b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 42636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 42736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 428a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 429a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 430a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 431a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 4325b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 433a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 434a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 435a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 4365b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 4375b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 4385b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 4395b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 440a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 441a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 442a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 443a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 444a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 4455b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 446a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 447a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 44836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 44936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 45036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 45136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 4528e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 453a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 454a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 455a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 456a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 457a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 45836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 4598e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 46036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 46136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 46236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 463a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusConstPool(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 46436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 46536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 46636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 4678e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 46836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 46936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 47036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 47136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 47236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 47336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 47436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng .addReg(BaseReg).addImm(ThisVal); 47536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 47636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg); 47736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 47836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 47936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 48036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 4815b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 482a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 483a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 4845b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 4855b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 486a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 487a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 4883fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 489a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 490a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal); 491a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 492a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 493a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 495a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 496a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 497a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 4985b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 4995b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 500a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 501a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 502a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 503a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 504a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 505a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 506a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 507a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg) 508a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 509a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 510a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 511a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 512a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 513a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, bool isThumb, const TargetInstrInfo &TII) { 514a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 515a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 516a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 517a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 518a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 519a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5207bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 5217bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 5227bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 52375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (hasFP(MF)) { 524a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 525a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 526a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 527b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 528b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 529b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 531a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 532a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 534b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 535b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 536b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 537a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 538b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) { 539a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII); 540b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 541b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola assert(Old->getOpcode() == ARM::ADJCALLSTACKUP); 542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII); 543b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 544b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 5457ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 5467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 5477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 5487bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 550a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 551a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 552a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 554a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 555a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 556a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 557a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 559a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 560a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 561a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal); 562a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 563a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 565a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg).addReg(DestReg); 566a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 567a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 568a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 569a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 57058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 57158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 57258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 573a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 574a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 57558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 576a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 577a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 578a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 579a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 580a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 582a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 583a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 584a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.getFrameInfo()->getStackSize(); 58558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 586a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 587a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 588a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 589a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 590a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 59275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 594a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 595a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 596b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 597a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 598a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 599a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 600a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 601a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 602a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 603a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 604a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 605a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 607a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 608a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVrr)); 609a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 610a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 611a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 612a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 613a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 614a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 615a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 616a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 61758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 619a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 620a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 621a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 623a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 624a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 626a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 627a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 628a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 629a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 630a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 631a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31); 632a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 633a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 634a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 635a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 636a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 638a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 639a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((Offset & 3) == 0 && 64386eb5153594b523e0b201735e14c92785d7ba601Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 644a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 645a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVrr)); 647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 649a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 650a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 651a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 653a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (((Offset >> 2) & ~255U) == 0) { 654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 655a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 656a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset >> 2); 657a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 660a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 661a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 662a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, 8, 1); 663a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 664a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 665a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 66688b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 667a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 668a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 669a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 670a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 672a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 673a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 674a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 675a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 676a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(255); 677a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng Offset = (Offset - 255 * 4); 678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 679a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false); 687a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 688a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 689a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 690a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 692a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 693a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 694a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 696a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 700a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 701a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 702a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 703a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 704a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 705a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 706a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 707a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 708a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 709a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 710a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 711a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 712a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 713a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 714a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 715a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 716a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 717a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 721a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 724a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng NumBits = isSub ? 3 : ((FrameReg == ARM::SP) ? 8 : 5); 725a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng Scale = isSub ? 1 : 4; 726a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 727a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 728a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 729a8e2989ece6dc46df59b0768184028257f913843Evan Cheng std::cerr << "Unsupported addressing mode!\n"; 730a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 731a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 732a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 73358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 734a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 7359312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 736a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 737a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 738a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 739a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 74058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 741a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 7428e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 7438e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 7448e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 7458e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 7468e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 7478e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 7488e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 7498e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 7508e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 7518e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 7528e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 75388b633165a20398d1015eec561856500fcf30d7dEvan Cheng 754a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 755a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 756a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 757a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (AddrMode == ARMII::AddrModeTs || !isThumSpillRestore) { 758a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (AddrMode == ARMII::AddrModeTs) { 759a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 760a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // a different base register. 761a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng NumBits = 5; 762a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng Mask = (1 << NumBits) - 1; 763a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng } 76488b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 76588b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 768a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 76988b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 770a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 772a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 773a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 774a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 775a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 776a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 77758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 778a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 779a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 780a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 781a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 7828e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (Opcode == ARM::tRestore) 783a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg, Offset, false, TII); 7848e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng else 785a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 7865b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 787a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 7885b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 789a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 790a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 791a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 792a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 793a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 794a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 795a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 796a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // str r12, r2 797a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 7985b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 799a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 8005b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 801a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2); 802a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 803a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 8048e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (Opcode == ARM::tSpill) 805a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg, Offset, false, TII); 8068e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng else 807a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8085b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 8095b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 8105b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 8115b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) 812a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12); 813a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 814a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 815a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 816a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 817a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 818a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 819a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 820a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg, 821a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 822a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(ARM::R12, false); 823a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 8247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 8257bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 8267bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 827a8e2989ece6dc46df59b0768184028257f913843Evan ChengprocessFunctionBeforeCalleeSavedScan(MachineFunction &MF) const { 82875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 82975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 83075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 831a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 83275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 833a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 834a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 835a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 836a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 837a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 83875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 83975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 84075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 84175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 84275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 84375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 84475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 84575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 84675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 84775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 84875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 84975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 85075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 85175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 85275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 85375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 85475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 855a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 856a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 85775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 858a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 85975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 86075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 86175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 86275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 863c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 864c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 865c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 866c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else 867c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng CS1Spilled = true; 868c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 869c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 870c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 87175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 87275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 87375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 87475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 87575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 87675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 87775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 87875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 87975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 88075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 88175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 88275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 88375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 88475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 88575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 886c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 887c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 888c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 889c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 890c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 89175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 89275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 89375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 89475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 89575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 89675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 89775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 89875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 89975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 90075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 90175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 902a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 903a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 904a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 905a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 906a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 90778268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 908d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 909d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 910d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 911d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // Force LR spill if the Thumb function size is > 2048. This enables the 912d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 913d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // the branch fix up path will undo it. 914d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 915d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 916d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 917d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 918d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 919d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 9207588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 92175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 922a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 923a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 924a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 925a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 926a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(ARM::LR, true); 927a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 928a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 929a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 930d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 931a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 932a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 9333548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 9343548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 9357588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 9363548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng MF.changePhyRegUsed(FramePtr, true); 9373548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 9383548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 9393548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 940c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng // If stack and double are 8-byte aligned and we are spilling an odd number 941a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of GPRs. Spill one extra callee save GPR so we won't have to pad between 942a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // the integer and double callee save areas. 943a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 944a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TargetAlign == 8 && (NumGPRSpills & 1)) { 945a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (CS1Spilled && !UnspilledCS1GPRs.empty()) 946a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS1GPRs.front(), true); 947c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else if (!UnspilledCS2GPRs.empty()) 948a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true); 949a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 950a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 95178268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 952d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 953d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng MF.changePhyRegUsed(ARM::LR, true); 954d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng AFI->setLRIsForceSpilled(true); 955d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 956a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 957a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 958a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 959a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 960a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 961a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 962a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 963a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 964a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 965a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 966a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 967a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 968a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 969a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 970a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 97175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 972a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 973a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 974a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 97575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 976970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 977a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 97875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 97975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 980a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 981a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 982a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 983a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 984a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 985a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 986a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 987a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 988a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 989a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 990a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 991a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 992a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 9937bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 9947bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 995355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 99644819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 997355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 998a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 999a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1000a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1001a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1002a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1003a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1004355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1005236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 1006236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1007236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1008236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1009236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1010236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1011a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1012a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1013a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1014a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1015236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1016236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 1017236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1018236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1019236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1020236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1021236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (VARegSaveSize) 1022236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII); 1023236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1024236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1025236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1026236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1027236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1028236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1029236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1030236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1031236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1032236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1033236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1034236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1035236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1036236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1037236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1038236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1039236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1040236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1041236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1042236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1043236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1044236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1045236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1046236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1047236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1048a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1049a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1050a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1051236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1052236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1053236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1054236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1055a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1056236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1057a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1058236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Align == 8 && (GPRCS1Size & 7) != 0) 1059236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Pad CS1 to ensure proper alignment. 1060236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1061c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 1062236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1063236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1064236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII); 1065236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1066236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1067236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1068a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 10693548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 10703548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 10713548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 1072236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr) 1073236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 1074a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1075236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1076236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1077236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII); 1078a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1079236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1080236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 1081236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII); 1082a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 10837ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1084a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1085236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1086236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1087236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1088236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1089236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1090236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1091236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1092a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1093236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1094236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1095236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1096236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1097236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 1098a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1099236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 110015f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 11057ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1106a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1113a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 11168e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 11197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11207bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 11217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 11227bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock &MBB) const { 1123355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1124a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1125a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1127355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1128355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1129355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1133a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1134236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1135236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 11363df62bde9b3f2557cccfa1f18d25b57bf0477f60Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 1137236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1138236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 113915f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1140236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Unwind MBBI to point to first LDR / FLDD. 1141236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 1142236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (MBBI != MBB.begin()) { 1143236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng do 1144236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng --MBBI; 1145236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1146236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isCSRestore(MBBI, CSRegs)) 1147236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1148236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1150236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of FP callee save spill area. 1151236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1152236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getGPRCalleeSavedArea2Size() + 1153236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaSize()); 11549d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isThumb) { 11559d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (MBBI->getOpcode() == ARM::tBX_RET && 11569d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng &MBB.front() != MBBI && 11579d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng prior(MBBI)->getOpcode() == ARM::tPOP) { 11589d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng MachineBasicBlock::iterator PMBBI = prior(MBBI); 11599d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII); 11609d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else 11619d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 11629d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 11633548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 11643548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 11653548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 1166236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1167236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Reset SP based on frame pointer only if the stack frame extends beyond 11684642ca6589d3002861963744a157169f15d1ee90Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1169236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (AFI->getGPRCalleeSavedArea2Size() || 1170236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaSize() || 11714642ca6589d3002861963744a157169f15d1ee90Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 11724642ca6589d3002861963744a157169f15d1ee90Lauro Ramos Venancio hasFP(MF)) 1173236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1174236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 1175236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addImm(NumBytes); 1176236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 1177236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr); 1178236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (NumBytes) { 1179236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, false, TII); 1180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 11813548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1182236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of integer callee save spill area 2. 1183236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 1184236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII); 1185236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1186236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of integer callee save spill area 1. 1187236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 1188236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII); 1189236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1190236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to SP upon entry to the function. 1191236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 1192236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII); 1193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1194236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 11959d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1196f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1197f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1198f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1199f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1200f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1201236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII); 1202f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1203f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1204f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1205f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1206f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 12079d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 12087bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12097bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 12127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11; 12167bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12187bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 12197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1220