ARMRegisterInfo.cpp revision acdfa445ac370cbf392234e9176c98f46bb3f672
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 28b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 307ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 31b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 32a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 34ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng#include "llvm/Support/CommandLine.h" 35a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 38ead75905813e175898677cb8c4e4cc919ad2782dEvan Chengstatic cl::opt<bool> EnableScavenging("enable-arm-reg-scavenging", cl::Hidden, 39ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng cl::desc("Enable register scavenging on ARM")); 40ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng 41a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 43a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 76a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 778fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 7915f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 8015f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 8115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 82a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 83a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 84c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 86a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) { 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 88a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 89a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 90a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 91a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 98ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 99ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng unsigned Reg = CSI[i-1].getReg(); 100ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng // Add the callee-saved register as live-in. It's killed at the spill. 101ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MBB.addLiveIn(Reg); 102ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); 103ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng } 104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 105a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 107a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1159d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1219d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1229d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1239d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 124a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 125a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1317bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1347bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 138a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 141ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true) 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 143a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 144ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true) 145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 146a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 147ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true) 148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 151ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true) 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1547bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1557bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1577bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1648e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 170a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1777bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1787bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1797bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 181a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr), 187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng DestReg).addReg(SrcReg); 188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 189c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); 190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 191c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg); 192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 1947bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1957bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 19640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 19740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 19840984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 19940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 20040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 20140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 20240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 20340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 20440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 20540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 20640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 20740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 20840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 209a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::MOVrr: { 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(0).addImm(0); 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::tMOVrr: { 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 230bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 2318e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 23240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2338e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 236a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 237bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 2388e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 23940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2408e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 241a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 242a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 243a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 247a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 248a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 249a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0); 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 261a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0); 264a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 265a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 2727bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2737bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 274c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 275c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 280a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 281a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 282ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 286a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 287a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 288a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 289a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 292970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 2930f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 2940f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 2950f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 296c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 297c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 298a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 299a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 300a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 301a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 303a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 304a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 305ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 306c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 3070f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3080f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 309b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 310b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 311b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::SP); 312b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 313b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(FramePtr); 314b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // Some targets reserve R9. 315b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isR9Reserved()) 316b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::R9); 317b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // At PEI time, if LR is used, it will be spilled upon entry. 318b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR)) 319b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::LR); 320b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 321b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 322b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 323a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 324a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 325a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 326a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 327dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 328a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 329a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 330a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 331ead75905813e175898677cb8c4e4cc919ad2782dEvan Chengbool ARMRegisterInfo::requiresRegisterScavenging() const { 332ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng return EnableScavenging; 333ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng} 334ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng 33536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 336a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 337a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 338a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 339a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 340a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 341a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 342a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 343a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 344a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 345a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 346a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 347a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 348a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 349a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 350a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 351a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 352a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 353a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 354a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 355a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 356a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 357a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 358a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 359a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(BaseReg).addImm(SOImmVal); 360a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 361a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 362a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 363a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 36436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 36536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 36636640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 36736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 36836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 36936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 37036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 37136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 37236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 37336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 37436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 37536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 37636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Scale = 1; 37736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 37836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 37936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 38036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 38136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 38236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 38336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 38436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 38536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 38636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 38736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 3887142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize NumBytes 3897142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// immediate. 3907142f8755a07512d909d288f74a3f1ffa9c1411aEvan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 3917142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineBasicBlock::iterator &MBBI, 3927142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned DestReg, int NumBytes, 3937142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng const TargetInstrInfo &TII) { 3947142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineFunction &MF = *MBB.getParent(); 3957142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 3967142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes); 3977142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 3987142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx); 3997142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng} 4007142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 401403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 402403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 403403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 40436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 40536640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 406403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 40736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 40836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 409a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 410a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 4117142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 4127142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 41336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 41436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 415a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 416a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 417a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 418a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 41936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 42036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 42136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 42236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 42336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 42436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 42536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 42636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3); 42736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 428a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 429a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 430a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4318bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 4328bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4338bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg).addReg(LdReg); 4348bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 4357142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII); 4367142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 43736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 43836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 43936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 44036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 44136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(BaseReg).addReg(LdReg); 44288b633165a20398d1015eec561856500fcf30d7dEvan Cheng else if (isSub) 44388b633165a20398d1015eec561856500fcf30d7dEvan Cheng MIB.addReg(BaseReg).addReg(LdReg); 44436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 44536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(LdReg).addReg(BaseReg); 44636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 44736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12); 44836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 44936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 45036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 451a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 452a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 453a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 454a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 455a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 456a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 457a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 458a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 459a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 460a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 461a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 4628e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 463a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 4645b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 46536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 46636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 467a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 468a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 469a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 470a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 4715b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 472a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 473a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 474a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 4755b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 4765b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 4775b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 4785b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 479a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 480a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 481a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 482a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 483a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 4845b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 485a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 486a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 48736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 48836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 48936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 49036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 4918e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 492a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 493a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 495a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 496a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 49736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 4988e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 49936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 50036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 50136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 502403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 50336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 50436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 50536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5068e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 50736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 50836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 50936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 51036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 51136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 51236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 51336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng .addReg(BaseReg).addImm(ThisVal); 51436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 51536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg); 51636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 51736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 51836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 51936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5205b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 521a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 522a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 5235b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 5245b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 525a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 526a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 5273fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 528a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 529a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal); 530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 531a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 532a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 534a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 535a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 536a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 5375b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 5385b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 539a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 541a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg) 547a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 548a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 550a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 551a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 552a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, bool isThumb, const TargetInstrInfo &TII) { 553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 554a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 555a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 556a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 557a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 5607bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 5617bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 56275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (hasFP(MF)) { 563a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 565a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 566b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 567b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 568b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 569a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 570a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 571a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 572a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 573b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 574b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 575b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 576a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 577b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) { 578a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII); 579b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 580b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola assert(Old->getOpcode() == ARM::ADJCALLSTACKUP); 581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII); 582b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 583b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 5847ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 5857bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 5867bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 5877bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 588a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 589a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 590a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 592a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 594a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 595a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 596a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 597a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 598a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 599a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 600a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal); 601a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 602a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 603a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 604a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg).addReg(DestReg); 605a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 607a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 608a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 60958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 61058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 61158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 612a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 613a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 61458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 615a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 616a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 617a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 619a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 620a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 621a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 623a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.getFrameInfo()->getStackSize(); 62458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 626a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 627a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 628a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 629a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 630a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 63175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 632a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 633a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 634a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 635b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 636a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 638a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 639a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 643a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 644a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 645a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVrr)); 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 649a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 650a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 651a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 653a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 655a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 65658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 657a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 660a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 661a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 662a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 663a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 665a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 666a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 668a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 669a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 670a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31); 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 672a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 673a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 674a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 675a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 676a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 677a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 679a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((Offset & 3) == 0 && 68286eb5153594b523e0b201735e14c92785d7ba601Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVrr)); 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 687a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 688a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 689a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 690a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 692a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (((Offset >> 2) & ~255U) == 0) { 693a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 694a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 695a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset >> 2); 696a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 700a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 701a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, 8, 1); 702a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 703a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 704a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 70588b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 706a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 707a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 708a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 709a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 710a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 711a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 712a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 713a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 714a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 715a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(255); 716a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng Offset = (Offset - 255 * 4); 717a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 721a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 725a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false); 726a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 727a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 728a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 729a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 730a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 731a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 732a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 733a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 734a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 735a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 736a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 737a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 738a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 739a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 740a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 741a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 745a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 746a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 747a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 748a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 750a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 751a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 752a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 753a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 754a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 755a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 756a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 757a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 758a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 759a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 760a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 761a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 762a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 7637142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 7647142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 7688fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 769a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 770a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 77258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 773a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 7749312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 775a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 776a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 777a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 778a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 77958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 780a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 7818e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 7828e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 7838e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 7848e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 7858e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 7868e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 7878e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 7888e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 7898e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 7908e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 7918e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 79288b633165a20398d1015eec561856500fcf30d7dEvan Cheng 7935ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 7945ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 7955ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 7965ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 7975ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 7985ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 7995ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 800a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 801a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 8025ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 8035ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 8045ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 80588b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 80688b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 807a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 808a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 809a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 81088b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 811a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 812a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 813a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 814a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 815a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 816a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 817a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 81858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 819a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 820a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 821a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 822a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 8237142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 8247142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 8257142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 826403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 8277142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 8287142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 8297142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 8307142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 8317142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 832a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8335b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 834a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 8357142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 8367142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 8377142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 8385b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 839a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 840a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 841a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 842a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 843a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 844a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 845a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 8468bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 847a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 8485b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 849a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 8507142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 8515b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 852a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2); 853a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 854a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 8558bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn()) 8568bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3); 8577142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 8587142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 859403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 8607142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 8617142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 8627142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 8637142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 8647142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 865a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8665b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 8675b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 8687142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 8697142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 8707142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 8717142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 8728bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 8738bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 8748bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 8757142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12); 8768bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn()) 8778bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12); 878a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 879a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 880a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 881a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 882a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 883a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 884a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 885a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg, 886a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 887a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(ARM::R12, false); 888a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 8897bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 8907bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 8917bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 892a8e2989ece6dc46df59b0768184028257f913843Evan ChengprocessFunctionBeforeCalleeSavedScan(MachineFunction &MF) const { 89375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 89475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 89575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 896a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 89775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 898a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 899a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 900a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 901a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 902a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 90375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 90475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 90575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 90675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 90775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 90875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 90975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 91075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 91175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 91275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 91375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 91475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 91575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 91675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 91775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 91875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 91975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 920a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 921a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 92275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 923a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 92475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 92575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 92675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 92775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 928c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 929c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 930c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 931c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else 932c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng CS1Spilled = true; 933c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 934c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 935c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 93675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 93775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 93875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 93975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 94075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 94175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 94275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 94375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 94475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 94575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 94675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 94775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 94875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 94975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 95075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 951c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 952c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 953c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 954c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 955c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 95675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 95775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 95875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 95975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 96075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 96175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 96275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 96375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 96475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 96575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 96675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 967a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 968a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 969a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 970a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 971a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 97278268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 973d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 974d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 975d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 976d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // Force LR spill if the Thumb function size is > 2048. This enables the 977d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 978d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // the branch fix up path will undo it. 979d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 980d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 981d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 982d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 983d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 984d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 9857588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 98675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 987a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 988a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 989a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 990a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 991a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(ARM::LR, true); 992a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 993a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 994a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 995d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 996a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 997a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 9983548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 9993548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 10007588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 10013548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng MF.changePhyRegUsed(FramePtr, true); 10023548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 10033548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 10043548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1005c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng // If stack and double are 8-byte aligned and we are spilling an odd number 1006a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of GPRs. Spill one extra callee save GPR so we won't have to pad between 1007a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // the integer and double callee save areas. 1008a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1009a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1010a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (CS1Spilled && !UnspilledCS1GPRs.empty()) 1011a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS1GPRs.front(), true); 1012c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else if (!UnspilledCS2GPRs.empty()) 1013a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true); 1014a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1015a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 101678268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 1017d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 1018d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng MF.changePhyRegUsed(ARM::LR, true); 1019d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng AFI->setLRIsForceSpilled(true); 1020d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1021a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1022a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1023a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 1024a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 1025a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 1026a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1027a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1028a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1029a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1030a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1031a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1032a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1033a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1034a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1035a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 103675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1037a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1038a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1039a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 104075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1041970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1042a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 104375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 104475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1045a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1046a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1047a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1048a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1049a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1050a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1051a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1052a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1053a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1054a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1055a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1056a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1057a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 10587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 10597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1060355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 106144819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1062355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1063a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1064a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1065a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1066a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1067a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1068a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1069355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1070236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 10718bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 10728bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 10738bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 10748bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 10758bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 10768bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 10778bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 10788bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 10798bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1080236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1081236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1082236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1083236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1084236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1085a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1086a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1087a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1088a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1089acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1090acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (VARegSaveSize) 1091acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII); 1092acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1093236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1094236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 1095236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1096236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1097236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1098236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1099236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1100236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1101236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1102236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1103236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1104236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1105236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1106236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1107236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1108236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1109236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1110236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1111236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1112236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1113236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1114236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1115236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1116236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1117236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1118236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1119236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1120236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1121236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1122236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1123a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1124a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1125a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1126236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1127236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1128236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1129236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1131236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1133236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Align == 8 && (GPRCS1Size & 7) != 0) 1134236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Pad CS1 to ensure proper alignment. 1135236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1136c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 1137236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1138236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1139236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII); 1140236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1141236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1142236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1143a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 11443548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 11453548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 11463548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 1147236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr) 1148236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 1149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1150236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1151236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1152236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII); 1153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1154236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1155236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 1156236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII); 1157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 11587ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1160236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1161236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1162236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1163236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1164236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1165236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1166236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1168236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1169236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1170236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1171236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1172236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 1173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1174236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 117515f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 11807ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1181a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1188a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 11918e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 11947bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11957bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 11967bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 11977bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock &MBB) const { 1198355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1200a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1202355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1203355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1204355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1209236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1210236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 12113df62bde9b3f2557cccfa1f18d25b57bf0477f60Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 12129d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 1213acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Unwind MBBI to point to first LDR / FLDD. 1214acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio const unsigned *CSRegs = getCalleeSavedRegs(); 1215acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI != MBB.begin()) { 1216acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio do 1217acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio --MBBI; 1218acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1219acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (!isCSRestore(MBBI, CSRegs)) 1220acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio ++MBBI; 1221acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1222acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1223acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of FP callee save spill area. 1224acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1225acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getGPRCalleeSavedArea2Size() + 1226acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize()); 1227acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (isThumb) { 1228acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (hasFP(MF)) { 1229acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1230acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1231acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1232236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1233acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 1234236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 1235acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::SP).addReg(FramePtr); 1236acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1237acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI->getOpcode() == ARM::tBX_RET && 1238acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio &MBB.front() != MBBI && 1239acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio prior(MBBI)->getOpcode() == ARM::tPOP) { 1240acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio MachineBasicBlock::iterator PMBBI = prior(MBBI); 1241acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII); 1242acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else 1243acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 1244acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1245acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1246acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Darwin ABI requires FP to point to the stack slot that contains the 1247acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // previous FP. 1248acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (STI.isTargetDarwin() || hasFP(MF)) { 1249acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1250acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1251acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1252acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (AFI->getGPRCalleeSavedArea2Size() || 1253acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize() || 1254acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 1255acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio hasFP(MF)) 1256acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (NumBytes) 1257acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 1258acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio .addImm(NumBytes); 1259acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio else 1260acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr); 1261acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else if (NumBytes) { 1262acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, NumBytes, false, TII); 1263acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 12643548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1265acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 2. 1266acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 1267acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII); 1268236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1269acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 1. 1270acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 1271acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII); 1272236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1273acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to SP upon entry to the function. 1274acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 1275acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII); 1276acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1278236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 12799d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1280f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1281f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1282f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1283f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1284f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1285236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII); 1286f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1287f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1288f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1289f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1290f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 12919d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 12927bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12937bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12947bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 12967bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12977bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12987bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1299a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11; 13007bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 13017bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 130262819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHExceptionRegister() const { 130362819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception register"); 130462819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 130562819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 130662819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 130762819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHHandlerRegister() const { 130862819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception handler register"); 130962819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 131062819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 131162819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 13127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 13137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1314