ARMRegisterInfo.cpp revision aee4af68ae2016afc5b4ec0c430e539c5810a766
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 285ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng#include "llvm/CodeGen/RegisterScavenging.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 30b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 317ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 32b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 35ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng#include "llvm/Support/CommandLine.h" 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 39e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Chengstatic cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging", 40e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::Hidden, 41e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::desc("Enable register scavenging on Thumb")); 42ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng 43a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 76a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 798fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 80a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 8115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 8215f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 8315f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 84a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 86c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 884c6d20a096ad28aa6f812c07a48268e8a6ccb8feLauro Ramos Venancio FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng} 905ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng 91a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 100ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 101ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng unsigned Reg = CSI[i-1].getReg(); 102ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng // Add the callee-saved register as live-in. It's killed at the spill. 103ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MBB.addLiveIn(Reg); 104ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); 105ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng } 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 109a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1179d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1239d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1249d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1259d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 13566f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengstatic inline 13666f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengconst MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 13766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 13866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 13966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 14066f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengstatic inline 14166f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengconst MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 14266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return MIB.addReg(0); 14366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 14466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 14566f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengstatic const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB, 14666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineOperand &MO) { 14766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (MO.isRegister()) 14866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); 14966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng else if (MO.isImmediate()) 15066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = MIB.addImm(MO.getImm()); 15166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng else if (MO.isFrameIndex()) 15266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = MIB.addFrameIndex(MO.getFrameIndex()); 15366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng else 15466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng assert(0 && "Unknown operand for ARMInstrAddOperand!"); 15566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 15666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return MIB; 15766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 15866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 1597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1607bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1617bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1627bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 167ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true) 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 17066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::STR)) 17166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg, false, false, true) 17266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addReg(0).addImm(0)); 17366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else if (RC == ARM::DPRRegisterClass) { 17466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FSTD)) 17566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg, false, false, true) 17666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 17766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else { 17866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 17966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FSTS)) 18066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg, false, false, true) 18166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 18266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 18366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 18466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 18566f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengvoid ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 186f0a0cddbcda344a90b7217b744c78dccec71851cEvan Cheng SmallVectorImpl<MachineOperand> &Addr, 18766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng const TargetRegisterClass *RC, 18858184e6878fdab651bc7c9a59dab2687ca82ede2Evan Cheng SmallVectorImpl<MachineInstr*> &NewMIs) const { 18966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng unsigned Opc = 0; 19066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (RC == ARM::GPRRegisterClass) { 19166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 19266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (AFI->isThumbFunction()) { 19366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR; 19466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = 19566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, true); 19666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 19766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 19866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 19966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 20066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 20166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::STR; 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 20366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FSTD; 204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 20666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FSTS; 207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 20866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 20966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = 21066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, true); 21166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 21266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 21366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(MIB); 21466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 21566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 2167bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 2187bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 2197bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 2207bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 2217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 2268e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 22966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 23066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addReg(0).addImm(0)); 231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 23266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 23366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 23666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 23766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 2397bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2407bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 24166f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengvoid ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 242f0a0cddbcda344a90b7217b744c78dccec71851cEvan Cheng SmallVectorImpl<MachineOperand> &Addr, 24366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng const TargetRegisterClass *RC, 24458184e6878fdab651bc7c9a59dab2687ca82ede2Evan Cheng SmallVectorImpl<MachineInstr*> &NewMIs) const { 24566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng unsigned Opc = 0; 24666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (RC == ARM::GPRRegisterClass) { 24766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 24866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (AFI->isThumbFunction()) { 24966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR; 25066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); 25166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 25266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 25366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 25466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 25566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 25666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::LDR; 25766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else if (RC == ARM::DPRRegisterClass) { 25866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FLDD; 25966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else { 26066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 26166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FLDS; 26266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 26366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 26466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); 26566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 26666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 26766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(MIB); 26866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 26966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 27066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 27166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 2727bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 274a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 2759efce638d307b2c71bd7f0258d47501661434c27Evan Cheng const TargetRegisterClass *DestRC, 2769efce638d307b2c71bd7f0258d47501661434c27Evan Cheng const TargetRegisterClass *SrcRC) const { 2779efce638d307b2c71bd7f0258d47501661434c27Evan Cheng if (DestRC != SrcRC) { 2789efce638d307b2c71bd7f0258d47501661434c27Evan Cheng cerr << "Not yet supported!"; 2799efce638d307b2c71bd7f0258d47501661434c27Evan Cheng abort(); 2809efce638d307b2c71bd7f0258d47501661434c27Evan Cheng } 2819efce638d307b2c71bd7f0258d47501661434c27Evan Cheng 2829efce638d307b2c71bd7f0258d47501661434c27Evan Cheng if (DestRC == ARM::GPRRegisterClass) { 283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 28544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (AFI->isThumbFunction()) 28644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg); 28744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng else 28866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg) 28966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg))); 2909efce638d307b2c71bd7f0258d47501661434c27Evan Cheng } else if (DestRC == ARM::SPRRegisterClass) 29166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg) 29266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg)); 2939efce638d307b2c71bd7f0258d47501661434c27Evan Cheng else if (DestRC == ARM::DPRRegisterClass) 29466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg) 29566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg)); 296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 2987bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2997bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 300bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize the 301bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// specified immediate. 302bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 303bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator &MBBI, 3043b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned DestReg, int Val, 3053b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 306bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const TargetInstrInfo &TII, bool isThumb) { 307bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineFunction &MF = *MBB.getParent(); 308bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 309bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, Val); 310bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 311bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (isThumb) 312bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx); 313bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng else 314bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx) 3153b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg); 316bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 317bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 318bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengvoid ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 319bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator I, 320bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned DestReg, 321bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const MachineInstr *Orig) const { 322bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (Orig->getOpcode() == ARM::MOVi2pieces) { 32344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitLoadConstPool(MBB, I, DestReg, 32444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng Orig->getOperand(1).getImmedValue(), 3253b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(), 3263b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng Orig->getOperand(3).getReg(), 327bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng TII, false); 328bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng return; 329bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng } 330bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 331bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineInstr *MI = Orig->clone(); 332bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MI->getOperand(0).setReg(DestReg); 333bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MBB.insert(I, MI); 334bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 335bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 33640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 33740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 33840984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 33940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 34040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 34140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 34240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 34340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 34440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 34540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 34640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 34740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 34840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 349a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 350aee4af68ae2016afc5b4ec0c430e539c5810a766Evan Cheng SmallVectorImpl<unsigned> &Ops, 351aee4af68ae2016afc5b4ec0c430e539c5810a766Evan Cheng int FI) const { 352aee4af68ae2016afc5b4ec0c430e539c5810a766Evan Cheng if (Ops.size() != 1) return NULL; 353aee4af68ae2016afc5b4ec0c430e539c5810a766Evan Cheng 354aee4af68ae2016afc5b4ec0c430e539c5810a766Evan Cheng unsigned OpNum = Ops[0]; 355a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 356a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 357a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 358a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 3599f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::MOVr: { 36013ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng if (MI->getOperand(4).getReg() == ARM::CPSR) 36113ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng // If it is updating CPSR, then it cannot be foled. 36213ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng break; 36344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 3643b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 365a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 366a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 367a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 3683b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 369a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 370a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 371a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 3723b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 373a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 374a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 375a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 3769f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::tMOVr: { 377a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 378a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 379bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 3808e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 38140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 3828e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 383a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 384a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 385a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 386bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 3878e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 38840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 3898e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 390a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 391a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 392a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 393a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 394a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 39544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 3963b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 397a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 398a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 399a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 4003b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 401a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 402a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 40344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI) 4043b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 405a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 406a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 407a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 40944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 4103b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 411a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 412a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 413a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 4143b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 415a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 416a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 41744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI) 4183b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 419a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 420a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 421a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 422a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 423a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 425a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 426a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 4277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 4287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 42964d80e3387f328d21cd9cc06464b5de7861e3f27Evan Chengconst unsigned* 43064d80e3387f328d21cd9cc06464b5de7861e3f27Evan ChengARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 431c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 432a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 433a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 434a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 435a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 436a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 437a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 438ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 439a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 440a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 441a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 442a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 443a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 444a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 445a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 446a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 447a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 448970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 4490f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 4500f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 4510f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 4522365f51ed03afe6993bae962fdc2e5a956a64cd5Anton KorobeynikovARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 453c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 454a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 455a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 456a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 457a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 458a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 459a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 460a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 461ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 462c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 4630f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 4640f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 465b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 466c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // FIXME: avoid re-calculating this everytime. 467b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 468b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::SP); 469ad78ef215485389bb5c5698fa6f1ac670f0076d8Evan Cheng Reserved.set(ARM::PC); 470b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 471b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(FramePtr); 472b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // Some targets reserve R9. 473b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isR9Reserved()) 474b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::R9); 475b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 476b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 477b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 47836230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Chengbool 479140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { 480140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng switch (Reg) { 481140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng default: break; 482140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::SP: 483140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::PC: 484140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 485140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R7: 486140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R11: 487140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 488140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 489140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng break; 490140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R9: 491140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return STI.isR9Reserved(); 492140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 493140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 494140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return false; 495140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 496140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 497140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengbool 49836230cdda48edf6c634f2dcf69f9d78ac5a17377Evan ChengARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 49936230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 500e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng return ThumbRegScavenging || !AFI->isThumbFunction(); 5011b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng} 5021b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng 503a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 504a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 505a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 506a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 507dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 508a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 509a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 510a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5115c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 5125c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// not required, we reserve argument space for call sites in the function 5135c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// immediately on entry to the current function. This eliminates the need for 5145c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// add/sub sp brackets around call sites. Returns true if the call frame is 5155c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// included as part of the stack frame. 5165c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Chengbool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { 5175c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 5185c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng unsigned CFSize = FFI->getMaxCallFrameSize(); 5195c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 5205c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // It's not always a good idea to include the call frame as part of the 5215c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // stack frame. ARM (especially Thumb) has small immediate offset to 5225c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // address the stack frame. So a large call frame can cause poor codegen 5235c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // and may even makes it impossible to scavenge a register. 5245c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (AFI->isThumbFunction()) { 5255c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 5265c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return false; 5275c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng } else { 5285c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 5295c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return false; 5305c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng } 5314558b807a2076e199bcb019f5edc9eabbc5922c1Evan Cheng return !MF.getFrameInfo()->hasVarSizedObjects(); 5325c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng} 5335c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng 53436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 535a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 536a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 537a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 538a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 5393b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 5403b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 5413b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng const TargetInstrInfo &TII) { 542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 547a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 548a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 550a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 551a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 552a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 554a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 555a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 556a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 557a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 55944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addReg(BaseReg, false, false, true).addImm(SOImmVal) 56013ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 561a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 562a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 563a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 56536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 56636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 56736640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 56836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 56936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 57036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 57136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 57236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 57336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 57436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 57536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 57636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 5773d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 1; // Followed by a number of tADDi8. 57836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 57936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 58036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 58136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 58236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 58336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 58436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 58536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 58636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 58736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 58836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 589403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 590403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 591403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 59236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 59336640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 594403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 59536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 59636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 597a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 598a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 5997142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 6007142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 60136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 60236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 603a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 604a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 605a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 606a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 60736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 60836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 60936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 61036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 61136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 61236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 61336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 6149f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12) 6155ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 61636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 617a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 618a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 6199f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 6208bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 6219f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 6225ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) 6235ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(LdReg, false, false, true); 6248bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 6253b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true); 6267142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 62736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 62836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 62936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 6305ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng if (DestReg == ARM::SP || isSub) 6315ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(BaseReg).addReg(LdReg, false, false, true); 63236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 6335ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(LdReg).addReg(BaseReg, false, false, true); 63436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 6359f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3) 6365ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 63736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 63836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 63936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 641a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 642a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 643a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 644a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 645a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 649a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 650a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 6518e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 6535b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 65436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 65536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 656a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 657a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 6605b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 661a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 662a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 663a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 6645b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 6655b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 6665b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 6675b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 668a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 669a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 670a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 672a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 6735b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 674a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 675a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 67636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 67736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 67836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 67936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 6808e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 68636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 6878e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 68836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 68936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 69036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 691403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 69236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 69336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 69436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 6958e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 69636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 69736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 69836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 69936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 70036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 70136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 7025ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(ThisVal); 70336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 7049f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg) 7055ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true); 70636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 70736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 70836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 70936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 7105b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 711a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 712a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 7135b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 7145b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 715a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 716a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 7173fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 7195ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng bool isKill = BaseReg != ARM::SP; 7205ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg) 7215ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, isKill).addImm(ThisVal); 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 725a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 726a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 727a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 728a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 7295b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 7305b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 731a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 732a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 733a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 734a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 735a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 736a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 737a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 7385ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg) 7395ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true) 740a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 741a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 743a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 744a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 7453b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, 7463b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng bool isThumb, const TargetInstrInfo &TII) { 747a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 748a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 7503b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, 7513b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng Pred, PredReg, TII); 752a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 753a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 7547bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 7557bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 7567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 7575c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (!hasReservedCallFrame(MF)) { 758a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 759a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 760a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 761b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 762b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 763b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 764a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 768b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 769b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 770b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 77244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Opc = Old->getOpcode(); 77344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng bool isThumb = AFI->isThumbFunction(); 77444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ARMCC::CondCodes Pred = isThumb 77544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue(); 77644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 7770f8d9c04d9feef86cee35cf5fecfb348a6b3de50Bill Wendling // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 7780f8d9c04d9feef86cee35cf5fecfb348a6b3de50Bill Wendling unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg(); 7793b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII); 780b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 7810f8d9c04d9feef86cee35cf5fecfb348a6b3de50Bill Wendling // Note: PredReg is operand 3 for ADJCALLSTACKUP. 7820f8d9c04d9feef86cee35cf5fecfb348a6b3de50Bill Wendling unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg(); 78344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 7843b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII); 785b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 786b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 7877ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 7887bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 7897bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 7907bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 791a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 792a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 793a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 794a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 795a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 796a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 797a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 798a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 799a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 800a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 801a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 802a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 8039f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); 804a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 805a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 806a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 8075ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg) 8085ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true); 809a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 810a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 811c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// findScratchRegister - Find a 'free' ARM register. If register scavenger 812c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// is not being used, R12 is available. Otherwise, try for a call-clobbered 813c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// register first and then a spilled callee-saved register if that fails. 814c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengstatic 815c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengunsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 816c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng ARMFunctionInfo *AFI) { 817c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12; 818c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng if (Reg == 0) 819c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // Try a already spilled CS register. 820c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters()); 821c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 822c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng return Reg; 823c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng} 824c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 8251b051fc6a491c40cf3f926c089ad082938b653f0Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 82697de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng int SPAdj, RegScavenger *RS) const{ 827a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 82858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 82958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 83058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 831a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 832a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 83358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 834a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 835a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 836a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 837a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 838a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 839a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 840a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 841a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 84297de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng MF.getFrameInfo()->getStackSize() + SPAdj; 84358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 844a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 845a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 846a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 847a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 848a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 849a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 85075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 85197de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng assert(SPAdj == 0 && "Unexpected"); 852a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 853a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 854a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 855b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 856a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 857a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 858a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 859a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 860a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 861a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 8623d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 863a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 864a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 865a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 866a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 8679f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVr)); 868a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 869a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 870a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 871a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 872a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 873a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 874a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 875a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 87658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 877a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 878a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 879a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 880a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 881a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 882a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 883a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 884a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 885a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 886a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 887a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 888a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 889a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 890b03eacdbf39b37a98b65b936046b22cca8215d8dEvan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 891a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 892a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 893a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 894a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 895a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 896a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 897a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 898a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 899a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 900a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 9013d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 9023d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng // Can't use tADDrSPi if it's based off the frame pointer. 9033d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumBits = 0; 9043d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Scale = 1; 9053d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (FrameReg != ARM::SP) { 9063d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Opcode = ARM::tADDi3; 9073d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDi3)); 9083d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 3; 9093d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } else { 9103d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 8; 9113d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 4; 9123d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng assert((Offset & 3) == 0 && 9133d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 9143d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } 9153d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 916a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 917a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 9189f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVr)); 919a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 920a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 921a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 922a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 923a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 924a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 9253d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Mask = (1 << NumBits) - 1; 9263d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (((Offset / Scale) & ~Mask) == 0) { 927a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 928a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 9293d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset / Scale); 930a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 931a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 932a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 933a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 934a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 9353d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale); 936a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 937a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 938a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 93988b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 940a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 941a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 942a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 943a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 944a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 945a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 946a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 947a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 948a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 9493d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Mask); 9503d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Offset = (Offset - Mask * Scale); 951a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 952a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 953a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 954a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 955a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 956a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 957a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 958a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 9595ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); 960a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 961a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 962a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 963a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 964a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 965a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 966a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 967a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 968a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 969a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 970a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 971a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 972a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 973a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 974a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 975a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 976a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 977a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 978a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 979a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 980a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 981a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 982a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 983a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 984a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 985a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 986a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 987a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 988a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 989a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 990a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 991a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 992a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 993a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 994a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 995a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 996a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 9977142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 9987142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 999a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1000a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1001a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 10028fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 1003a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 1004a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1005a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 100658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 1007a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 10089312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 1009a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 1010a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 1011a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 1012a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 101358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 1014a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 10158e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 10168e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 10178e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 10188e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 10198e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 10208e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 10218e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 10228e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 10238e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 10248e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 10258e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 102688b633165a20398d1015eec561856500fcf30d7dEvan Cheng 10275ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 10285ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 10295ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 10305ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 10315ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 10325ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 10335ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 1034a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 1035a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 10365ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 10375ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 10385ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 103988b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 104088b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 1041a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 1042a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 1043a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 104488b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 1045a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1046a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1047a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1048a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 1049a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 1050a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 1051a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 105258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 1053a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 1054a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 1055a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 1056a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 10577142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 10587142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 10597142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 1060403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 10617142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 10623b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true); 10637142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 10647142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 10657142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 1066a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 10675b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 10685ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 10697142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 10707142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 10717142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 10725ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 1073a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 1074a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 1075a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 1076a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 1077a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 1078a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 1079a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 10808bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 1081a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 10825b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 1083a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 10847142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 10855b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 10869f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 10875ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R2, false, false, true); 1088a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 1089a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1090f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 10919f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 10925ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 10937142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 10947142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 1095403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 10967142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 10973b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true); 10987142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 10997142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 11007142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 1101a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 11025b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 11035ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 11047142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 11057142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 11067142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 11077142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 11088bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 11098bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 11108bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 11119f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2) 11125ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 1113f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 11149f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3) 11155ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 1116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 1117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 1118a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 1119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 1120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 1121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 1122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 1123c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); 1124140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (ScratchReg == 0) 1125140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // No register is "free". Scavenge a register. 112697de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); 112762ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng int PIdx = MI.findFirstPredOperandIdx(); 112862ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng ARMCC::CondCodes Pred = (PIdx == -1) 112962ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue(); 11303b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 11313b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, 11323b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng isSub ? -Offset : Offset, Pred, PredReg, TII); 11331b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1134a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 11357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1137140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengstatic unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 1138140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 1139140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int Offset = 0; 1140140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 1141140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int FixedOff = -FFI->getObjectOffset(i); 1142140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FixedOff > Offset) Offset = FixedOff; 1143140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1144140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 1145140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset += FFI->getObjectSize(i); 1146140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Align = FFI->getObjectAlignment(i); 1147140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Adjust to alignment boundary 1148140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset = (Offset+Align-1)/Align*Align; 1149140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1150140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return (unsigned)Offset; 1151140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 1152140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 1153140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengvoid 1154140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1155140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RegScavenger *RS) const { 115675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 115775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 115875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 1159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 116075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 1161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 1162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 1163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 1164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 1165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 1166f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 116775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 116875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 116975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 117075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 117175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 117275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 117375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 117475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 117575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 1176f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 117775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 117875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 117975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 118075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 118175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 118275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 118375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 118475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 1185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 118775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 1188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 118975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 119075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 119175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 119275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 1193c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1194c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 1195c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 1196356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio CS1Spilled = true; 1197c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1198c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1199c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 120075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 120175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 120275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 120375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 120475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 120575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 120675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 120775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 120875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 120975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 121075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 121175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 121275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 121375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 121475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 1215c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1216c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 1217c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1218c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1219c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 122075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 122175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 122275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 122375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 122475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 122575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 122675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 122775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 122875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 122975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 123075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 1231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1236d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 1237d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 1238d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 1239f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // Force LR to be spilled if the Thumb function size is > 2048. This enables 1240d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 1241f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // then the branch fix up path will undo it. 1242d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 1243d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 1244d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 1245d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1246d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1247d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 1248140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng bool ExtraCSSpill = false; 12497588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 125075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 1251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 12556c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(ARM::LR); 1256f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 1258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1260d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 1261140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ExtraCSSpill = true; 1262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 12643548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 12653548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 12667588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 12676c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(FramePtr); 12683548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 12693548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 12703548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1271356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // If stack and double are 8-byte aligned and we are spilling an odd number 1272356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // of GPRs. Spill one extra callee save GPR so we won't have to pad between 1273356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // the integer and double callee save areas. 1274356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1275356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1276356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1277356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1278356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned Reg = UnspilledCS1GPRs[i]; 1279356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // Don't spiil high register if the function is thumb 1280356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) { 1281356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Reg); 1282356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Reg); 1283356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!isReservedReg(MF, Reg)) 1284356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio ExtraCSSpill = true; 1285356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio break; 1286356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1287356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1288356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } else if (!UnspilledCS2GPRs.empty() && 1289356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio !AFI->isThumbFunction()) { 1290356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned Reg = UnspilledCS2GPRs.front(); 1291356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Reg); 1292356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Reg); 1293356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!isReservedReg(MF, Reg)) 1294356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio ExtraCSSpill = true; 1295356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1296356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1297356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio 1298140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Estimate if we might need to scavenge a register at some point in order 1299140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // to materialize a stack offset. If so, either spill one additiona 1300140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // callee-saved register or reserve a special spill slot to facilitate 1301140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // register scavenging. 1302140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) { 1303140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng MachineFrameInfo *MFI = MF.getFrameInfo(); 1304140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Size = estimateStackSize(MF, MFI); 1305140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Limit = (1 << 12) - 1; 1306140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) 1307140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) { 1308140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) 1309140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (I->getOperand(i).isFrameIndex()) { 1310140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Opcode = I->getOpcode(); 1311140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 1312140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1313140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (AddrMode == ARMII::AddrMode3) { 1314140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Limit = (1 << 8) - 1; 1315140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng goto DoneEstimating; 1316140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else if (AddrMode == ARMII::AddrMode5) { 13175c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng unsigned ThisLimit = ((1 << 8) - 1) * 4; 13185c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (ThisLimit < Limit) 13195c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng Limit = ThisLimit; 1320140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1321140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1322140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1323140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng DoneEstimating: 1324140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (Size >= Limit) { 1325140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // If any non-reserved CS register isn't spilled, just spill one or two 1326140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // extra. That should take care of it! 1327356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned NumExtras = TargetAlign / 4; 1328356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio SmallVector<unsigned, 2> Extras; 1329356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio while (NumExtras && !UnspilledCS1GPRs.empty()) { 1330140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS1GPRs.back(); 1331140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS1GPRs.pop_back(); 1332140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1333356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio Extras.push_back(Reg); 1334356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio NumExtras--; 1335140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1336140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1337356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio while (NumExtras && !UnspilledCS2GPRs.empty()) { 1338140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS2GPRs.back(); 1339140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS2GPRs.pop_back(); 1340140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1341356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio Extras.push_back(Reg); 1342356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio NumExtras--; 1343140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1344140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1345356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (Extras.size() && NumExtras == 0) { 1346356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1347356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Extras[i]); 1348356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Extras[i]); 1349356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1350140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else { 1351140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Reserve a slot closest to SP or frame pointer. 1352140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetRegisterClass *RC = &ARM::GPRRegClass; 1353140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1354140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RC->getAlignment())); 1355140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1356f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng } 1357a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1358a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 135978268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 1360d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 13616c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(ARM::LR); 1362f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1363f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setLRIsSpilledForFarJump(true); 1364d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1365a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1366a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1367a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 1368a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 1369a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 1370a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1371a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1372a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1373a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1374a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1375a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1376a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1377a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1378a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1379a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 138075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1381a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1382a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1383a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 138475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1385970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1386a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 138775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 138875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1389a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1390a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1391a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1392a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1393a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1394a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1395a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1396a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1397a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1398a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1399a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1400a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1401a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 14027bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 14037bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1404355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 140544819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1406355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1407a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1409a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1410a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1411a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1412355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1413236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 14148bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 14158bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 14168bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 14178bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 14188bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 14198bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 14208bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 14218bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 14228bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1423236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1424236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1425236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1426236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1427236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1428a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1429a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1430a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1431a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1432acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1433acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (VARegSaveSize) 14343b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII); 1435acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1436236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1437236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 14383b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII); 1439236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1440236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1441236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1442236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1443236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1444236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1445236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1446236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1447236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1448236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1449236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1450236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1451236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1452236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1453236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1454236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1455236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1456236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1457236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1458236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1459236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1460236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1461236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1462236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1463236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1464236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1465236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1466a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1467a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1468a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1469236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1470236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1471236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1472236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1473a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1474236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1475a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1476236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1477236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 14783b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII); 1479236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1480236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1481236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1482a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 14833548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 14843548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 148544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 148644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng MachineInstrBuilder MIB = 148744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr) 1488236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 148966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (!isThumb) AddDefaultCC(AddDefaultPred(MIB)); 149044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng } 1491a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1492236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1493236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 14943b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII); 1495a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1496236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1497236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 14983b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII); 1499a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 15007ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1501a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1502236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1503236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1504236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1505236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1506236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1507236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1508236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1509a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1510236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1511236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1512236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1513236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1514236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 15153b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII); 1516236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 151715f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1518e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio if(STI.isTargetELF() && hasFP(MF)) { 1519e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1520e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio AFI->getFramePtrSpillOffset()); 1521e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio } 1522e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio 1523a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1524a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1525a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1526a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 15277ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1528a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1529a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1531a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1532a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1534a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1535a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1536a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1537a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 15388e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1539a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 15417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 15427bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 15437bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 1544bed2946a96ecb15b0b636fa74cb26ce61b1c648eAnton Korobeynikov MachineBasicBlock &MBB) const { 1545355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1547a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1548a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1549355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1550355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1551355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1552a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1554a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1555a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1556236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1557236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 15583b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 15599d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 1560acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Unwind MBBI to point to first LDR / FLDD. 1561acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio const unsigned *CSRegs = getCalleeSavedRegs(); 1562acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI != MBB.begin()) { 1563acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio do 1564acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio --MBBI; 1565acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1566acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (!isCSRestore(MBBI, CSRegs)) 1567acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio ++MBBI; 1568acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1569acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1570acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of FP callee save spill area. 1571acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1572acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getGPRCalleeSavedArea2Size() + 1573acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize()); 1574acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (isThumb) { 1575acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (hasFP(MF)) { 1576acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1577acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1578acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1579236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1580acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 1581236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 15829f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); 1583acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1584acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI->getOpcode() == ARM::tBX_RET && 1585acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio &MBB.front() != MBBI && 1586acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio prior(MBBI)->getOpcode() == ARM::tPOP) { 1587acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio MachineBasicBlock::iterator PMBBI = prior(MBBI); 15883b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 1589acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else 15903b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 1591acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1592acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1593acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Darwin ABI requires FP to point to the stack slot that contains the 1594acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // previous FP. 15959f8e50d4ed7dcc5ca0f137830ff1185b2afa38bfDale Johannesen if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) { 1596acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1597acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1598acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1599acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (AFI->getGPRCalleeSavedArea2Size() || 1600acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize() || 1601acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 1602acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio hasFP(MF)) 1603acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (NumBytes) 1604acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 160513ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm(NumBytes) 160613ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1607acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio else 160844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr) 160913ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1610acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else if (NumBytes) { 16113b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII); 1612acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 16133548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1614acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 2. 1615acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 16163b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0, 161744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1618236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1619acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 1. 1620acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 16213b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0, 162244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1623236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1624acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to SP upon entry to the function. 1625acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 16263b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0, 162744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1628acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1629a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1630236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 16319d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1632f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1633f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1634f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1635f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1636f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 16373b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII); 1638f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1639f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1640f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1641f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1642f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 16439d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 16447bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 16457bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 16467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 16487bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 16497bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 16507bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1651267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio if (STI.isTargetDarwin() || hasFP(MF)) 16524c6d20a096ad28aa6f812c07a48268e8a6ccb8feLauro Ramos Venancio return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11; 1653267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio else 1654267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio return ARM::SP; 16557bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 16567bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 165762819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHExceptionRegister() const { 165862819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception register"); 165962819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 166062819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 166162819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 166262819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHHandlerRegister() const { 166362819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception handler register"); 166462819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 166562819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 166662819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 1667b97aec663b1591e71c9ddee6dbb327d1b827eda5Dale Johannesenint ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1668f191c80cd79ee35e47b5a4feed98d687782dfe85Anton Korobeynikov assert(0 && "What is the dwarf register number"); 1669f191c80cd79ee35e47b5a4feed98d687782dfe85Anton Korobeynikov return -1; 1670f191c80cd79ee35e47b5a4feed98d687782dfe85Anton Korobeynikov} 1671f191c80cd79ee35e47b5a4feed98d687782dfe85Anton Korobeynikov 16727bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 16737bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1674