ARMRegisterInfo.cpp revision b371f457b0ea4a652a9f526ba4375c80ae542252
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 28b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 307ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 31b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 32a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 34a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 37a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 38a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 39a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 40a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 41a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 43a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 738fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 7515f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 7615f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 7715f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 78a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 79a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 80c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 81a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 82a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) { 83a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 84a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 85a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 86a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 88a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 89a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 90a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 91a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MIB.addReg(CSI[i-1].getReg()); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 105a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1079d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1139d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1149d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1159d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1237bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1257bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1267bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1338e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg) 134a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg) 137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 138a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg) 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 143a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg) 144a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1487bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1497bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1507bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1517bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1568e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1697bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1707bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1717bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr), 179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng DestReg).addReg(SrcReg); 180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 181c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); 182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 183c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg); 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 1867bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1877bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 18840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 18940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 19040984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 19140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 19240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 19340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 19440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 19540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 19640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 19740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 19840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 19940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 20040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 201a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::MOVrr: { 208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(0).addImm(0); 212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::tMOVrr: { 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 222bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 2238e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 22440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2258e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 229bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 2308e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 23140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2328e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 236a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 239a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 240a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 241a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 242a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 243a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0); 245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 247a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 248a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 249a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0); 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 261a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 2647bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2657bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 266c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 267c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 274ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 280a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 281a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 282a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 284970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 2850f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 2860f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 2870f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 288c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 289c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 297ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 298c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 2990f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 3000f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 301b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 302b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 303b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::SP); 304b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 305b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(FramePtr); 306b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // Some targets reserve R9. 307b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isR9Reserved()) 308b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::R9); 309b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // At PEI time, if LR is used, it will be spilled upon entry. 310b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR)) 311b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::LR); 312b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 313b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 314b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 315a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 316a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 317a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 318a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 319dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 320a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 321a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 322a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 32336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 324a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 325a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 326a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 327a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 328a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 329a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 330a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 331a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 332a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 333a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 334a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 335a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 336a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 337a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 338a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 339a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 340a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 341a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 342a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 343a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 344a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 345a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 346a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 347a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(BaseReg).addImm(SOImmVal); 348a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 349a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 350a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 351a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 35236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 35336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 35436640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 35536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 35636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 35736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 35836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 35936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 36036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 36136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 36236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 36336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 36436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Scale = 1; 36536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 36636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 36736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 36836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 36936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 37036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 37136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 37236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 37336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 37436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 37536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 3767142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize NumBytes 3777142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// immediate. 3787142f8755a07512d909d288f74a3f1ffa9c1411aEvan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 3797142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineBasicBlock::iterator &MBBI, 3807142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned DestReg, int NumBytes, 3817142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng const TargetInstrInfo &TII) { 3827142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineFunction &MF = *MBB.getParent(); 3837142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 3847142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes); 3857142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 3867142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx); 3877142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng} 3887142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 389403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 390403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 391403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 39236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 39336640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 394403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 39536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 39636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 397a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 398a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 3997142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 4007142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 40136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 40236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 403a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 404a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 405a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 406a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 40736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 40836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 40936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 41036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 41136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 41236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 41336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 41436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3); 41536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 416a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 417a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 418a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4198bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 4208bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4218bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg).addReg(LdReg); 4228bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 4237142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII); 4247142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 42536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 42636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 42736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 42836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 42936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(BaseReg).addReg(LdReg); 43088b633165a20398d1015eec561856500fcf30d7dEvan Cheng else if (isSub) 43188b633165a20398d1015eec561856500fcf30d7dEvan Cheng MIB.addReg(BaseReg).addReg(LdReg); 43236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 43336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(LdReg).addReg(BaseReg); 43436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 43536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12); 43636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 43736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 43836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 439a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 440a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 441a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 442a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 443a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 444a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 445a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 446a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 447a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 448a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 449a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 4508e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 451a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 4525b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 45336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 45436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 455a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 456a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 457a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 458a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 4595b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 460a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 461a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 462a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 4635b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 4645b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 4655b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 4665b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 467a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 468a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 469a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 470a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 471a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 4725b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 473a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 474a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 47536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 47636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 47736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 47836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 4798e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 480a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 481a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 482a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 483a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 484a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 48536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 4868e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 48736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 48836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 48936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 490403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 49136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 49236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 49336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 4948e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 49536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 49636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 49736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 49836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 49936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 50036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 50136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng .addReg(BaseReg).addImm(ThisVal); 50236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 50336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg); 50436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 50536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 50636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 50736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 5085b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 509a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 510a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 5115b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 5125b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 513a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 514a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 5153fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 516a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 517a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal); 518a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 519a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 520a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 521a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 522a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 523a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 524a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 5255b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 5265b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 527a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 528a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 529a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 531a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 532a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 534a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg) 535a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 536a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 537a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 538a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 539a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, bool isThumb, const TargetInstrInfo &TII) { 541a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 546a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 5487bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 5497bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 55075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (hasFP(MF)) { 551a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 552a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 553a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 554b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 555b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 556b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 557a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 559a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 560a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 561b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 562b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 563b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 565b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) { 566a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII); 567b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 568b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola assert(Old->getOpcode() == ARM::ADJCALLSTACKUP); 569a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII); 570b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 571b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 5727ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 5737bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 5747bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 5757bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 576a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 577a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 578a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 579a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 580a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 582a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 583a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 584a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 585a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 586a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 587a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 588a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal); 589a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 590a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 592a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg).addReg(DestReg); 593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 594a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 595a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 596a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 59758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 59858421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 59958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 600a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 601a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 60258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 603a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 604a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 605a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 607a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 608a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 609a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 610a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 611a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.getFrameInfo()->getStackSize(); 61258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 613a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 614a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 615a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 616a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 617a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 61975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 620a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 621a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 623b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 624a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 626a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 627a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 628a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 629a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 630a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 631a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 632a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 633a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 634a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 635a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVrr)); 636a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 638a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 639a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 643a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 64458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 645a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 649a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 650a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 651a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 653a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 655a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 656a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 657a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31); 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 660a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 661a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 662a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 663a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 665a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 666a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 668a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 669a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((Offset & 3) == 0 && 67086eb5153594b523e0b201735e14c92785d7ba601Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 672a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 673a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVrr)); 674a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 675a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 676a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 677a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 679a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 680a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (((Offset >> 2) & ~255U) == 0) { 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 683a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset >> 2); 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 687a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 688a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 689a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, 8, 1); 690a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 691a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 692a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 69388b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 694a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 695a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 696a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 697a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 700a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 701a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 702a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 703a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(255); 704a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng Offset = (Offset - 255 * 4); 705a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 706a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 707a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 708a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 709a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 710a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 711a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 712a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 713a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false); 714a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 715a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 716a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 717a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 721a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 725a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 726a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 727a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 728a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 729a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 730a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 731a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 732a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 733a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 734a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 735a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 736a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 737a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 738a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 739a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 740a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 741a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 745a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 746a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 747a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 748a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 750a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 7517142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 7527142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 753a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 754a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 755a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 7568fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 757a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 758a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 759a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 76058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 761a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 7629312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 763a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 764a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 76758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 768a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 7698e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 7708e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 7718e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 7728e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 7738e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 7748e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 7758e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 7768e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 7778e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 7788e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 7798e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 78088b633165a20398d1015eec561856500fcf30d7dEvan Cheng 7815ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 7825ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 7835ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 7845ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 7855ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 7865ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 7875ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 788a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 789a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 7905ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 7915ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 7925ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 79388b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 79488b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 795a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 796a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 797a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 79888b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 799a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 800a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 801a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 802a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 803a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 804a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 805a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 80658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 807a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 808a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 809a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 810a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 8117142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 8127142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 8137142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 814403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 8157142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 8167142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 8177142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 8187142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 8197142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 820a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8215b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 822a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 8237142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 8247142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 8257142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 8265b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 827a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 828a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 829a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 830a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 831a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 832a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 833a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 8348bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 835a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 8365b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 837a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 8387142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 8395b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 840a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2); 841a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 842a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 8438bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn()) 8448bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3); 8457142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 8467142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 847403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 8487142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 8497142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 8507142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 8517142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 8527142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 853a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8545b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 8555b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 8567142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 8577142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 8587142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 8597142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 8608bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 8618bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 8628bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 8637142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12); 8648bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn()) 8658bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12); 866a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 867a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 868a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 869a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 870a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 871a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 872a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 873a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg, 874a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 875a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(ARM::R12, false); 876a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 8777bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 8787bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 8797bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 880a8e2989ece6dc46df59b0768184028257f913843Evan ChengprocessFunctionBeforeCalleeSavedScan(MachineFunction &MF) const { 88175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 88275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 88375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 884a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 88575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 886a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 887a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 888a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 889a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 890a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 89175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 89275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 89375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 89475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 89575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 89675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 89775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 89875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 89975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 90075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 90175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 90275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 90375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 90475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 90575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 90675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 90775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 908a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 909a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 91075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 911a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 91275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 91375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 91475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 91575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 916c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 917c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 918c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 919c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else 920c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng CS1Spilled = true; 921c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 922c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 923c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 92475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 92575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 92675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 92775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 92875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 92975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 93075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 93175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 93275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 93375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 93475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 93575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 93675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 93775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 93875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 939c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 940c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 941c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 942c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 943c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 94475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 94575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 94675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 94775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 94875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 94975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 95075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 95175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 95275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 95375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 95475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 955a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 956a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 957a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 958a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 959a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 96078268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 961d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 962d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 963d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 964d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // Force LR spill if the Thumb function size is > 2048. This enables the 965d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 966d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // the branch fix up path will undo it. 967d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 968d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 969d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 970d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 971d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 972d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 9737588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 97475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 975a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 976a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 977a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 978a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 979a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(ARM::LR, true); 980a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 981a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 982a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 983d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 984a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 985a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 9863548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 9873548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 9887588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 9893548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng MF.changePhyRegUsed(FramePtr, true); 9903548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 9913548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 9923548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 993c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng // If stack and double are 8-byte aligned and we are spilling an odd number 994a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of GPRs. Spill one extra callee save GPR so we won't have to pad between 995a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // the integer and double callee save areas. 996a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 997a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TargetAlign == 8 && (NumGPRSpills & 1)) { 998a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (CS1Spilled && !UnspilledCS1GPRs.empty()) 999a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS1GPRs.front(), true); 1000c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else if (!UnspilledCS2GPRs.empty()) 1001a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true); 1002a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1003a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 100478268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 1005d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 1006d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng MF.changePhyRegUsed(ARM::LR, true); 1007d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng AFI->setLRIsForceSpilled(true); 1008d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1009a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1010a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1011a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 1012a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 1013a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 1014a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1015a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1016a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1017a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1018a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1019a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1020a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1021a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1022a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1023a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 102475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1025a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1026a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1027a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 102875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1029970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1030a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 103175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 103275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1033a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1034a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1035a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1036a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1037a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1038a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1039a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1040a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1041a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1042a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1043a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1044a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1045a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 10467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 10477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1048355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 104944819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1050355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1051a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1052a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1053a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1054a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1055a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1056a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1057355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1058236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 10598bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 10608bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 10618bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 10628bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 10638bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 10648bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 10658bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 10668bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 10678bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1068236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1069236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1070236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1071236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1072236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1073a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1074a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1075a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1076a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1077236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1078236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 1079236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1080236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1081236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1082236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1083236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (VARegSaveSize) 1084236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII); 1085236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1086236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1087236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1088236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1089236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1090236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1091236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1092236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1093236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1094236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1095236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1096236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1097236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1098236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1099236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1100236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1101236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1102236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1103236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1104236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1105236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1106236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1107236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1108236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1109236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1113236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1114236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1115236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1116236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1118236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1120236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Align == 8 && (GPRCS1Size & 7) != 0) 1121236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Pad CS1 to ensure proper alignment. 1122236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1123c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 1124236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1125236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1126236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII); 1127236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1128236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1129236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 11313548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 11323548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 11333548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 1134236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr) 1135236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 1136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1137236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1138236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1139236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII); 1140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1141236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1142236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 1143236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII); 1144a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 11457ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1146a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1147236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1148236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1149236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1150236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1151236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1152236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1153236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1155236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1156236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1157236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1158236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1159236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 1160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1161236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 116215f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 11677ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1168a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1170a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1175a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 11788e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 11817bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11827bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 11837bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 11847bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock &MBB) const { 1185355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1189355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1190355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1191355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1196236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1197236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 11983df62bde9b3f2557cccfa1f18d25b57bf0477f60Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 1199236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1200236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 120115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1202236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Unwind MBBI to point to first LDR / FLDD. 1203236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 1204236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (MBBI != MBB.begin()) { 1205236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng do 1206236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng --MBBI; 1207236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1208236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isCSRestore(MBBI, CSRegs)) 1209236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1210236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1212236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of FP callee save spill area. 1213236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1214236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getGPRCalleeSavedArea2Size() + 1215236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaSize()); 12169d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isThumb) { 12177142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (hasFP(MF)) { 12187142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 12197142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng // Reset SP based on frame pointer only if the stack frame extends beyond 12207142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng // frame pointer stack slot or target is ELF and the function has FP. 12217142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (NumBytes) 12227142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 12237142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 12247142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::SP).addReg(FramePtr); 12257142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else { 12267142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (MBBI->getOpcode() == ARM::tBX_RET && 12277142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng &MBB.front() != MBBI && 12287142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng prior(MBBI)->getOpcode() == ARM::tPOP) { 12297142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineBasicBlock::iterator PMBBI = prior(MBBI); 12307142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII); 12317142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 12327142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 12337142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 12349d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 12353548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 12363548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 12373548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 1238236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1239236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Reset SP based on frame pointer only if the stack frame extends beyond 12404642ca6589d3002861963744a157169f15d1ee90Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1241236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (AFI->getGPRCalleeSavedArea2Size() || 1242236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaSize() || 12434642ca6589d3002861963744a157169f15d1ee90Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 12444642ca6589d3002861963744a157169f15d1ee90Lauro Ramos Venancio hasFP(MF)) 1245236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1246236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 1247236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addImm(NumBytes); 1248236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 1249236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr); 1250236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (NumBytes) { 1251236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, false, TII); 1252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 12533548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1254236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of integer callee save spill area 2. 1255236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 1256236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII); 1257236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1258236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of integer callee save spill area 1. 1259236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 1260236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII); 1261236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1262236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to SP upon entry to the function. 1263236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 1264236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII); 1265a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1266236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 12679d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1268f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1269f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1270f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1271f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1272f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1273236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII); 1274f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1275f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1276f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1277f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1278f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 12799d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 12807bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12817bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12827bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1283a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 12847bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12857bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12867bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1287a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11; 12887bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12897bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12907bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 12917bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1292