ARMRegisterInfo.cpp revision bd8251a9a6d4f90065b52e04d15120bc111e56aa
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 28b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 307ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 31a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 357bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 36a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 37a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 38a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 39a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 40a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 41a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 43a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 728fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 7415f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 7515f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 7615f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 77a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 79c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 80a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 81a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) { 82a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 83a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 84a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 86a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 88a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 89a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 90a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 91a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MIB.addReg(CSI[i-1].getReg()); 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 98a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 105a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1069d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1129d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1139d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1149d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1227bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1237bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1257bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1267bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned SrcReg, int FI, 1277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1328e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg) 133a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 134a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg) 136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 138a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg) 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg) 143a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 144a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1457bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1467bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1477bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1487bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1497bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 1507bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 1558e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0); 160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1687bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1697bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1707bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetRegisterClass *RC) const { 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr), 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng DestReg).addReg(SrcReg); 179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::SPRRegisterClass) 180c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); 181a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (RC == ARM::DPRRegisterClass) 182c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg); 183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 1857bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1867bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 18740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 18840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 18940984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 19040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 19140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 19240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 19340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 19440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 19540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 19640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 19740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 19840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 19940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 200a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned OpNum, int FI) const { 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::MOVrr: { 207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(0).addImm(0); 211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::tMOVrr: { 219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 221bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 2228e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 22340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2248e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 228bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 2298e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 23040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 2318e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 236a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 239a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 240a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 241a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 242a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 243a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0); 244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 246a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 247a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 248a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 249a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0); 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 260a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 261a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 2637bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2647bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 265c2b861da18c54a4252fecba866341e1513fa18ccEvan Chengconst unsigned* ARMRegisterInfo::getCalleeSavedRegs() const { 266c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 273ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 274a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 276a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 280a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 281a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 282a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 283970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 2840f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 2850f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 2860f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 287c2b861da18c54a4252fecba866341e1513fa18ccEvan ChengARMRegisterInfo::getCalleeSavedRegClasses() const { 288c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 289a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 290a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 294a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 295a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 296ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 297c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 2980f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 2990f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 300a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 301a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 302a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 303a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 304dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 305a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 306a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 307a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 30836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 309a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 310a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 311a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 312a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 313a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 314a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 315a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 316a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 317a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 318a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 319a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 320a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 321a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 322a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 323a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 324a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 325a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 326a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 327a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 328a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 329a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 330a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 331a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 332a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addReg(BaseReg).addImm(SOImmVal); 333a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 334a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 335a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 336a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 33736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 33836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 33936640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 34036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 34136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 34236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 34336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 34436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 34536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 34636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 34736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 34836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 34936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Scale = 1; 35036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 35136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 35236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 35336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 35436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 35536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 35636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 35736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 35836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 35936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 36036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 3617142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize NumBytes 3627142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng/// immediate. 3637142f8755a07512d909d288f74a3f1ffa9c1411aEvan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 3647142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineBasicBlock::iterator &MBBI, 3657142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned DestReg, int NumBytes, 3667142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng const TargetInstrInfo &TII) { 3677142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineFunction &MF = *MBB.getParent(); 3687142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 3697142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes); 3707142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 3717142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx); 3727142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng} 3737142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 374403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 375403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 376403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 37736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 37836640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 379403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 38036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 38136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 382a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 383a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 3847142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 3857142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 38636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 38736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 388a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 389a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 390a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 391a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 39236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 39336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 39436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 39536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 39636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 39736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 39836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 39936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3); 40036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 401a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 402a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 403a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4048bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 4058bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); 4068bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg).addReg(LdReg); 4078bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 4087142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII); 4097142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 41036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 41136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 41236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 41336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 41436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(BaseReg).addReg(LdReg); 41588b633165a20398d1015eec561856500fcf30d7dEvan Cheng else if (isSub) 41688b633165a20398d1015eec561856500fcf30d7dEvan Cheng MIB.addReg(BaseReg).addReg(LdReg); 41736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 41836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MIB.addReg(LdReg).addReg(BaseReg); 41936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 42036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12); 42136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 42236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 42336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 425a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 426a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 427a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 428a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 429a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 430a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 431a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 432a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 433a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 434a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 4358e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 436a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 4375b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 43836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 43936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 440a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 441a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 442a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 443a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 4445b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 445a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 446a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 447a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 4485b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 4495b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 4505b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 4515b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 452a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 453a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 454a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 455a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 456a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 4575b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 458a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 459a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 46036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 46136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 46236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 46336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 4648e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 465a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 466a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 467a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 468a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 469a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 47036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 4718e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 47236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 47336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 47436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 475403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 47636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 47736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 47836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 4798e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 48036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 48136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 48236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 48336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 48436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 48536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 48636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng .addReg(BaseReg).addImm(ThisVal); 48736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 48836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg); 48936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 49036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 49136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 49236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 4935b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 495a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 4965b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 4975b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 498a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 499a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 5003fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 501a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 502a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal); 503a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 504a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 505a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 506a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 507a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 508a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 509a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 5105b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 5115b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 512a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 513a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 514a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 515a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 516a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 517a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 518a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 519a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg) 520a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 521a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 522a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 523a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 524a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 525a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, bool isThumb, const TargetInstrInfo &TII) { 526a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 527a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 528a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 529a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 530a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 531a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 5337bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 5347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 53575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (hasFP(MF)) { 536a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 537a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 538a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 539b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 540b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 541b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 545a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 546b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 547b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 548b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 549a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 550b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) { 551a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII); 552b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 553b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola assert(Old->getOpcode() == ARM::ADJCALLSTACKUP); 554a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII); 555b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 556b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 5577ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 5587bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 5597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 5607bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 561a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 562a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 563a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 565a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 566a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 567a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 568a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 569a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 570a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 571a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 572a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 573a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal); 574a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 575a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 576a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 577a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg).addReg(DestReg); 578a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 579a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 580a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 58258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 58358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 58458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 585a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 586a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 58758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 588a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 589a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 590a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 592a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 594a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 595a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 596a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.getFrameInfo()->getStackSize(); 59758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 598a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 599a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 600a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 601a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 602a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 603a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 60475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 605a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 606a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 607a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 608b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 609a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 610a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 611a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 612a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 613a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 614a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 615a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 616a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 617a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 618a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 619a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 620a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVrr)); 621a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 622a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 623a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 624a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 625a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 626a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 627a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 628a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 62958421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 630a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 631a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 632a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 633a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 634a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 635a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 636a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 637a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 638a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 639a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 640a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 641a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 642a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 643a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31); 644a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 645a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 646a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 647a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 648a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 649a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 650a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 651a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 652a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 653a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 654a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((Offset & 3) == 0 && 65586eb5153594b523e0b201735e14c92785d7ba601Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 656a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 657a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 658a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVrr)); 659a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 660a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 661a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 662a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 663a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 665a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (((Offset >> 2) & ~255U) == 0) { 666a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 668a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset >> 2); 669a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 670a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 671a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 672a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 673a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 674a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, 8, 1); 675a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 676a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 677a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 67888b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 679a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 680a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 681a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 682a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 685a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 687a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 688a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(255); 689a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng Offset = (Offset - 255 * 4); 690a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 692a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 693a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 694a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 696a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 698a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false); 699a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 700a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 701a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 702a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 703a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 704a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 705a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 706a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 707a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 708a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 709a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 710a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 711a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 712a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 713a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 714a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 715a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 716a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 717a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 720a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 721a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 722a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 723a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 724a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 725a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 726a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 727a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 728a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 729a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 730a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 731a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 732a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 733a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 734a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 735a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 7367142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 7377142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 738a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 739a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 740a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 7418fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 742a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 743a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 744a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 74558421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 746a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 7479312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 748a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 750a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 751a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 75258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 753a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 7548e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 7558e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 7568e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 7578e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 7588e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 7598e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 7608e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 7618e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 7628e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 7638e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 7648e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 76588b633165a20398d1015eec561856500fcf30d7dEvan Cheng 7665ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 7675ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 7685ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 7695ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 7705ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 7715ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 7725ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 773a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 774a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 7755ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 7765ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 7775ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 77888b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 77988b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 780a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 781a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 782a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 78388b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 784a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 785a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 786a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 787a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 788a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 789a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 790a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 79158421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 792a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 793a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 794a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 795a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 7967142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 7977142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 7987142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 799403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 8007142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 8017142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 8027142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 8037142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 8047142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 805a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8065b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 807a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 8087142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 8097142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 8107142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 8115b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 812a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 813a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 814a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 815a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 816a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 817a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 818a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 8198bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 820a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 8215b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 822a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 8237142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 8245b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 825a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2); 826a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 827a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 8288bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn()) 8298bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3); 8307142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 8317142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 832403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 8337142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 8347142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, TII); 8357142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 8367142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 8377142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 838a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 8395b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 8405b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false); 8417142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 8427142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 8437142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 8447142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 8458bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 8468bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 8478bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 8487142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12); 8498bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn()) 8508bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12); 851a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 852a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 853a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 854a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 855a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 856a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 857a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 858a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg, 859a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub ? -Offset : Offset, TII); 860a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(ARM::R12, false); 861a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 8627bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 8637bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 8647bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 865a8e2989ece6dc46df59b0768184028257f913843Evan ChengprocessFunctionBeforeCalleeSavedScan(MachineFunction &MF) const { 86675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 86775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 86875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 869a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 87075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 871a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 872a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 873a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 874a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 875a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 87675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 87775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 87875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 87975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 88075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 88175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 88275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 88375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 88475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 88575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 88675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 88775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 88875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 88975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 89075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 89175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 89275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 893a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 894a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 89575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 896a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 89775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 89875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 89975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 90075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 901c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 902c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 903c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 904c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else 905c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng CS1Spilled = true; 906c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 907c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 908c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 90975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 91075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 91175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 91275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 91375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 91475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 91575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 91675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 91775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 91875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 91975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 92075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 92175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 92275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 92375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 924c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 925c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 926c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 927c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 928c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 92975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 93075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 93175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 93275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 93375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 93475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 93575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 93675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 93775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 93875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 93975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 940a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 941a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 942a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 943a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 944a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 94578268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 946d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 947d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 948d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 949d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // Force LR spill if the Thumb function size is > 2048. This enables the 950d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 951d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // the branch fix up path will undo it. 952d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 953d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 954d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 955d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 956d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 957d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 9587588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 95975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 960a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 961a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 962a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 963a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 964a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(ARM::LR, true); 965a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 966a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 967a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 968d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 969a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 970a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 9713548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 9723548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 9737588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 9743548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng MF.changePhyRegUsed(FramePtr, true); 9753548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 9763548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 9773548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 978c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng // If stack and double are 8-byte aligned and we are spilling an odd number 979a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of GPRs. Spill one extra callee save GPR so we won't have to pad between 980a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // the integer and double callee save areas. 981a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 982a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TargetAlign == 8 && (NumGPRSpills & 1)) { 983a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (CS1Spilled && !UnspilledCS1GPRs.empty()) 984a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS1GPRs.front(), true); 985c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng else if (!UnspilledCS2GPRs.empty()) 986a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true); 987a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 988a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 98978268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 990d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 991d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng MF.changePhyRegUsed(ARM::LR, true); 992d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng AFI->setLRIsForceSpilled(true); 993d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 994a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 995a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 996a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 997a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 998a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 999a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1000a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1001a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1002a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1003a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1004a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1005a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1006a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1007a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1008a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 100975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1010a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1011a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1012a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 101375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1014970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1015a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 101675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 101775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1018a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1019a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1020a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1021a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1022a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1023a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1024a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1025a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1026a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1027a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1028a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1029a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1030a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 10317bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 10327bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1033355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 103444819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1035355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1036a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1037a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1038a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1039a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1040a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1041a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1042355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1043236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 10448bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 10458bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 10468bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 10478bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 10488bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 10498bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 10508bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 10518bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 10528bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1053236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1054236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1055236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1056236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1057236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1058a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1059a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1060a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1061a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1062236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1063236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 1064236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1065236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1066236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1067236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1068236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (VARegSaveSize) 1069236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII); 1070236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1071236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1072236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1073236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1074236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1075236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1076236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1077236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1078236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1079236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1080236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1081236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1082236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1083236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1084236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1085236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1086236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1087236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1088236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1089236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1090236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1091236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1092236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1093236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1094236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1095a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1096a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1097a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1098236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1099236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1100236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1101236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1103236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1105236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Align == 8 && (GPRCS1Size & 7) != 0) 1106236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Pad CS1 to ensure proper alignment. 1107236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1108c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 1109236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1110236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1111236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII); 1112236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1113236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1114236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 11163548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 11173548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 11183548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 1119236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr) 1120236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 1121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1122236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1123236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1124236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII); 1125a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1126236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1127236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 1128236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII); 1129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 11307ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1132236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1133236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1134236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1135236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1136236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1137236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1138236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1140236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1141236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1142236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1143236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1144236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 1145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII); 1146236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 114715f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 11527ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1153a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1160a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 11638e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 11667bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11677bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 11687bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 11697bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock &MBB) const { 1170355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1174355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1175355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1176355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1181236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1182236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 11833df62bde9b3f2557cccfa1f18d25b57bf0477f60Evan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 1184236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1185236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 118615f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1187236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Unwind MBBI to point to first LDR / FLDD. 1188236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 1189236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (MBBI != MBB.begin()) { 1190236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng do 1191236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng --MBBI; 1192236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1193236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isCSRestore(MBBI, CSRegs)) 1194236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1195236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1196a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1197236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of FP callee save spill area. 1198236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1199236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getGPRCalleeSavedArea2Size() + 1200236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaSize()); 12019d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isThumb) { 12027142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (hasFP(MF)) { 12037142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 12047142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng // Reset SP based on frame pointer only if the stack frame extends beyond 12057142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng // frame pointer stack slot or target is ELF and the function has FP. 12067142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (NumBytes) 12077142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 12087142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 12097142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::SP).addReg(FramePtr); 12107142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else { 12117142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (MBBI->getOpcode() == ARM::tBX_RET && 12127142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng &MBB.front() != MBBI && 12137142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng prior(MBBI)->getOpcode() == ARM::tPOP) { 12147142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MachineBasicBlock::iterator PMBBI = prior(MBBI); 12157142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII); 12167142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 12177142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); 12187142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 12199d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 12203548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 12213548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 12223548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 1223236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1224236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Reset SP based on frame pointer only if the stack frame extends beyond 12254642ca6589d3002861963744a157169f15d1ee90Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1226236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (AFI->getGPRCalleeSavedArea2Size() || 1227236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->getDPRCalleeSavedAreaSize() || 12284642ca6589d3002861963744a157169f15d1ee90Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 12294642ca6589d3002861963744a157169f15d1ee90Lauro Ramos Venancio hasFP(MF)) 1230236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1231236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 1232236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addImm(NumBytes); 1233236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 1234236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr); 1235236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (NumBytes) { 1236236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, false, TII); 1237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 12383548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1239236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of integer callee save spill area 2. 1240236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 1241236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII); 1242236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1243236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to start of integer callee save spill area 1. 1244236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 1245236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII); 1246236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1247236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Move SP to SP upon entry to the function. 1248236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 1249236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII); 1250a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1251236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 12529d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1253f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1254f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1255f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1256f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1257f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1258236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII); 1259f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1260f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1261f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1262f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1263f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 12649d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 12657bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12667bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12677bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 12697bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12707bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12717bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11; 12737bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 12747bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 12757bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 12767bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1277