ARMRegisterInfo.cpp revision d64b5c82b97ad1b74eb9fd2f23257a7899b0c307
17bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 27bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 37bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// The LLVM Compiler Infrastructure 47bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 57bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file was developed by the "Instituto Nokia de Tecnologia" and 67bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// is distributed under the University of Illinois Open Source 77bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// License. See LICENSE.TXT for details. 87bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 97bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 107bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 117bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// This file contains the ARM implementation of the MRegisterInfo class. 127bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola// 137bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola//===----------------------------------------------------------------------===// 147bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 157bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARM.h" 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMAddressingModes.h" 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMInstrInfo.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMMachineFunctionInfo.h" 197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMRegisterInfo.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "ARMSubtarget.h" 2136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/Constants.h" 2236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/DerivedTypes.h" 2336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 2536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 277bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/CodeGen/MachineLocation.h" 285ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng#include "llvm/CodeGen/RegisterScavenging.h" 29b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetFrameInfo.h" 30b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola#include "llvm/Target/TargetMachine.h" 317ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola#include "llvm/Target/TargetOptions.h" 32b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/ADT/SmallVector.h" 347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "llvm/ADT/STLExtras.h" 35ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng#include "llvm/Support/CommandLine.h" 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <algorithm> 377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolausing namespace llvm; 387bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 39e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Chengstatic cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging", 40e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::Hidden, 41e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng cl::desc("Enable register scavenging on Thumb")); 42ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng 43a8e2989ece6dc46df59b0768184028257f913843Evan Chengunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng using namespace ARM; 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (RegEnum) { 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R0: case S0: case D0: return 0; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R1: case S1: case D1: return 1; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R2: case S2: case D2: return 2; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R3: case S3: case D3: return 3; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R4: case S4: case D4: return 4; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R5: case S5: case D5: return 5; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R6: case S6: case D6: return 6; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R7: case S7: case D7: return 7; 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R8: case S8: case D8: return 8; 55a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R9: case S9: case D9: return 9; 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R10: case S10: case D10: return 10; 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R11: case S11: case D11: return 11; 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case R12: case S12: case D12: return 12; 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case SP: case S13: case D13: return 13; 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case LR: case S14: case D14: return 14; 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case PC: case S15: case D15: return 15; 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S16: return 16; 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S17: return 17; 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S18: return 18; 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S19: return 19; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S20: return 20; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S21: return 21; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S22: return 22; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S23: return 23; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S24: return 24; 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S25: return 25; 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S26: return 26; 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S27: return 27; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S28: return 28; 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S29: return 29; 76a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S30: return 30; 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case S31: return 31; 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 798fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unknown ARM register!"); 80a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 8115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola } 8215f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola} 8315f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 84a8e2989ece6dc46df59b0768184028257f913843Evan ChengARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &sti) 86c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TII(tii), STI(sti), 884c6d20a096ad28aa6f812c07a48268e8a6ccb8feLauro Ramos Venancio FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 895ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng} 905ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng 91a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); 100ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 101ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng unsigned Reg = CSI[i-1].getReg(); 102ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng // Add the callee-saved register as live-in. It's killed at the spill. 103ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MBB.addLiveIn(Reg); 104ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); 105ead75905813e175898677cb8c4e4cc919ad2782dEvan Cheng } 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 109a8e2989ece6dc46df59b0768184028257f913843Evan Chengbool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator MI, 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI) const { 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!AFI->isThumbFunction() || CSI.empty()) 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1179d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.insert(MI, PopMI); 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = CSI.size(); i != 0; --i) { 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Reg = CSI[i-1].getReg(); 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == ARM::LR) { 1239d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng // Special epilogue for vararg functions. See emitEpilogue 1249d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (isVarArg) 1259d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng continue; 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Reg = ARM::PC; 127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBB.erase(MI); 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PopMI->addRegOperand(Reg, true); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1337bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 1347bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 13566f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengstatic inline 13666f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengconst MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 13766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 13866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 13966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 14066f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengstatic inline 14166f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengconst MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 14266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return MIB.addReg(0); 14366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 14466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 14566f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengstatic const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB, 14666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineOperand &MO) { 14766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (MO.isRegister()) 14866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); 14966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng else if (MO.isImmediate()) 15066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = MIB.addImm(MO.getImm()); 15166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng else if (MO.isFrameIndex()) 15266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = MIB.addFrameIndex(MO.getFrameIndex()); 15366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng else 15466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng assert(0 && "Unknown operand for ARMInstrAddOperand!"); 15566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 15666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return MIB; 15766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 15866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 1597bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 1607bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 161d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng unsigned SrcReg, bool isKill, int FI, 1627bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 167d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, isKill) 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 17066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::STR)) 171d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng .addReg(SrcReg, false, false, isKill) 17266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addReg(0).addImm(0)); 17366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else if (RC == ARM::DPRRegisterClass) { 17466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FSTD)) 175d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng .addReg(SrcReg, false, false, isKill) 17666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 17766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else { 17866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 17966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FSTS)) 180d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng .addReg(SrcReg, false, false, isKill) 18166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 18266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 18366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 18466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 18566f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengvoid ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 186d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng bool isKill, 187f0a0cddbcda344a90b7217b744c78dccec71851cEvan Cheng SmallVectorImpl<MachineOperand> &Addr, 18866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng const TargetRegisterClass *RC, 18958184e6878fdab651bc7c9a59dab2687ca82ede2Evan Cheng SmallVectorImpl<MachineInstr*> &NewMIs) const { 19066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng unsigned Opc = 0; 19166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (RC == ARM::GPRRegisterClass) { 19266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 19366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (AFI->isThumbFunction()) { 19466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR; 19566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = 196d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill); 19766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 19866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 19966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 20066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 20166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 20266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::STR; 203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 20466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FSTD; 205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 20766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FSTS; 208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 20966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 21066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = 211d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill); 21266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 21366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 21466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(MIB); 21566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 21666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 2177bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2187bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 2197bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 2207bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 2217bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola unsigned DestReg, int FI, 2227bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola const TargetRegisterClass *RC) const { 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (RC == ARM::GPRRegisterClass) { 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isThumbFunction()) 2278e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg) 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addFrameIndex(FI).addImm(0); 229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 23066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) 23166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addReg(0).addImm(0)); 232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (RC == ARM::DPRRegisterClass) { 23366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) 23466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 236a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 23766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) 23866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addFrameIndex(FI).addImm(0)); 239a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 2407bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 2417bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 24266f0f640820b61cf9db814b6d187bae9faf7279cEvan Chengvoid ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 243f0a0cddbcda344a90b7217b744c78dccec71851cEvan Cheng SmallVectorImpl<MachineOperand> &Addr, 24466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng const TargetRegisterClass *RC, 24558184e6878fdab651bc7c9a59dab2687ca82ede2Evan Cheng SmallVectorImpl<MachineInstr*> &NewMIs) const { 24666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng unsigned Opc = 0; 24766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (RC == ARM::GPRRegisterClass) { 24866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 24966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (AFI->isThumbFunction()) { 25066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR; 25166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); 25266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 25366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 25466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 25566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 25666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 25766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::LDR; 25866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else if (RC == ARM::DPRRegisterClass) { 25966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FLDD; 26066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } else { 26166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); 26266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng Opc = ARM::FLDS; 26366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng } 26466f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 26566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); 26666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng for (unsigned i = 0, e = Addr.size(); i != e; ++i) 26766f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng MIB = ARMInstrAddOperand(MIB, Addr[i]); 26866f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(MIB); 26966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng NewMIs.push_back(MIB); 27066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng return; 27166f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng} 27266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng 2737bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 274a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator I, 275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned SrcReg, 2769efce638d307b2c71bd7f0258d47501661434c27Evan Cheng const TargetRegisterClass *DestRC, 2779efce638d307b2c71bd7f0258d47501661434c27Evan Cheng const TargetRegisterClass *SrcRC) const { 2789efce638d307b2c71bd7f0258d47501661434c27Evan Cheng if (DestRC != SrcRC) { 2799efce638d307b2c71bd7f0258d47501661434c27Evan Cheng cerr << "Not yet supported!"; 2809efce638d307b2c71bd7f0258d47501661434c27Evan Cheng abort(); 2819efce638d307b2c71bd7f0258d47501661434c27Evan Cheng } 2829efce638d307b2c71bd7f0258d47501661434c27Evan Cheng 2839efce638d307b2c71bd7f0258d47501661434c27Evan Cheng if (DestRC == ARM::GPRRegisterClass) { 284a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineFunction &MF = *MBB.getParent(); 285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 28644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (AFI->isThumbFunction()) 28744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg); 28844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng else 28966f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg) 29066f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg))); 2919efce638d307b2c71bd7f0258d47501661434c27Evan Cheng } else if (DestRC == ARM::SPRRegisterClass) 29266f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg) 29366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg)); 2949efce638d307b2c71bd7f0258d47501661434c27Evan Cheng else if (DestRC == ARM::DPRRegisterClass) 29566f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg) 29666f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng .addReg(SrcReg)); 297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 298a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 2997bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 3007bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 301bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// emitLoadConstPool - Emits a load from constpool to materialize the 302bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng/// specified immediate. 303bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengstatic void emitLoadConstPool(MachineBasicBlock &MBB, 304bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator &MBBI, 3053b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned DestReg, int Val, 3063b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 307bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const TargetInstrInfo &TII, bool isThumb) { 308bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineFunction &MF = *MBB.getParent(); 309bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineConstantPool *ConstantPool = MF.getConstantPool(); 310bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng Constant *C = ConstantInt::get(Type::Int32Ty, Val); 311bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); 312bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (isThumb) 313bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx); 314bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng else 315bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx) 3163b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg); 317bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 318bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 319bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Chengvoid ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 320bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineBasicBlock::iterator I, 321bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng unsigned DestReg, 322bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng const MachineInstr *Orig) const { 323bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng if (Orig->getOpcode() == ARM::MOVi2pieces) { 32444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng emitLoadConstPool(MBB, I, DestReg, 32544bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng Orig->getOperand(1).getImmedValue(), 3263b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(), 3273b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng Orig->getOperand(3).getReg(), 328bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng TII, false); 329bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng return; 330bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng } 331bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 332bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MachineInstr *MI = Orig->clone(); 333bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MI->getOperand(0).setReg(DestReg); 334bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng MBB.insert(I, MI); 335bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng} 336bf2c8b3c96f5c885095a10b0fcb29438f92d73c2Evan Cheng 33740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// isLowRegister - Returns true if the register is low register r0-r7. 33840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng/// 33940984d7449c80a3d0365d31f25dff451fd54f060Evan Chengstatic bool isLowRegister(unsigned Reg) { 34040984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng using namespace ARM; 34140984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng switch (Reg) { 34240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R0: case R1: case R2: case R3: 34340984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng case R4: case R5: case R6: case R7: 34440984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return true; 34540984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng default: 34640984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng return false; 34740984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng } 34840984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng} 34940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng 350a8e2989ece6dc46df59b0768184028257f913843Evan ChengMachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, 351aee4af68ae2016afc5b4ec0c430e539c5810a766Evan Cheng SmallVectorImpl<unsigned> &Ops, 352aee4af68ae2016afc5b4ec0c430e539c5810a766Evan Cheng int FI) const { 353aee4af68ae2016afc5b4ec0c430e539c5810a766Evan Cheng if (Ops.size() != 1) return NULL; 354aee4af68ae2016afc5b4ec0c430e539c5810a766Evan Cheng 355aee4af68ae2016afc5b4ec0c430e539c5810a766Evan Cheng unsigned OpNum = Ops[0]; 356a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opc = MI->getOpcode(); 357a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineInstr *NewMI = NULL; 358a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Opc) { 359a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: break; 3609f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::MOVr: { 36113ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng if (MI->getOperand(4).getReg() == ARM::CPSR) 36213ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng // If it is updating CPSR, then it cannot be foled. 36313ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng break; 36444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 3653b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 366a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 367a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 368a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) 3693b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 370a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 371a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 372a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) 3733b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 374a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 375a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 376a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 3779f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng case ARM::tMOVr: { 378a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 379a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 380bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 3818e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tSpill cannot take a high register operand. 38240984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 3838e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI) 384a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 385a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 386a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 387bd8251a9a6d4f90065b52e04d15120bc111e56aaEvan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 3888e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // tRestore cannot target a high register operand. 38940984d7449c80a3d0365d31f25dff451fd54f060Evan Cheng break; 3908e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI) 391a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(0); 392a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 393a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 394a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 395a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYS: { 39644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 3973b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 398a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 399a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 400a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) 4013b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 402a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 403a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 40444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI) 4053b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 406a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 407a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 409a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::FCPYD: { 41044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Pred = MI->getOperand(2).getImmedValue(); 4113b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 412a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (OpNum == 0) { // move -> store 413a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 414a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) 4153b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 416a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { // move -> load 417a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 41844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI) 4193b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng .addImm(0).addImm(Pred).addReg(PredReg); 420a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 421a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 422a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 423a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 425a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (NewMI) 426a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NewMI->copyKillDeadInfo(MI); 427a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NewMI; 4287bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 4297bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 430d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Chengbool ARMRegisterInfo::canFoldMemoryOperand(MachineInstr *MI, 431d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng SmallVectorImpl<unsigned> &Ops) const { 432d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng if (Ops.size() != 1) return NULL; 433d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng 434d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng unsigned OpNum = Ops[0]; 435d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng unsigned Opc = MI->getOpcode(); 436d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng switch (Opc) { 437d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng default: break; 438d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng case ARM::MOVr: 439d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng // If it is updating CPSR, then it cannot be foled. 440d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng return MI->getOperand(4).getReg() != ARM::CPSR; 441d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng case ARM::tMOVr: { 442d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng if (OpNum == 0) { // move -> store 443d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 444d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) 445d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng // tSpill cannot take a high register operand. 446d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng return false; 447d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng } else { // move -> load 448d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 449d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg)) 450d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng // tRestore cannot target a high register operand. 451d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng return false; 452d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng } 453d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng return true; 454d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng } 455d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng case ARM::FCPYS: 456d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng case ARM::FCPYD: 457d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng return true; 458d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng } 459d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng 460d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng return false; 461d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng} 462d64b5c82b97ad1b74eb9fd2f23257a7899b0c307Evan Cheng 46364d80e3387f328d21cd9cc06464b5de7861e3f27Evan Chengconst unsigned* 46464d80e3387f328d21cd9cc06464b5de7861e3f27Evan ChengARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 465c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const unsigned CalleeSavedRegs[] = { 466a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 467a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R7, ARM::R6, ARM::R5, ARM::R4, 468a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 469a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 470a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 471a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 472ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 473a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 474a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static const unsigned DarwinCalleeSavedRegs[] = { 475a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 476a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::R11, ARM::R10, ARM::R9, ARM::R8, 477a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 478a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D15, ARM::D14, ARM::D13, ARM::D12, 479a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARM::D11, ARM::D10, ARM::D9, ARM::D8, 480a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 481a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 482970a419633ba41cac44ae636543f192ea632fe00Evan Cheng return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 4830f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 4840f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 4850f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Chengconst TargetRegisterClass* const * 4862365f51ed03afe6993bae962fdc2e5a956a64cd5Anton KorobeynikovARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 487c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 488a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 489a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 490a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 491a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 492a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 493a8e2989ece6dc46df59b0768184028257f913843Evan Cheng &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 0 495ec46ea34dcc615558294e9e0dbd0dd0f2894f574Rafael Espindola }; 496c2b861da18c54a4252fecba866341e1513fa18ccEvan Cheng return CalleeSavedRegClasses; 4970f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 4980f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 499b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 500c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // FIXME: avoid re-calculating this everytime. 501b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 502b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::SP); 503ad78ef215485389bb5c5698fa6f1ac670f0076d8Evan Cheng Reserved.set(ARM::PC); 504b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) 505b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(FramePtr); 506b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng // Some targets reserve R9. 507b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (STI.isR9Reserved()) 508b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(ARM::R9); 509b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 510b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 511b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 51236230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Chengbool 513140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { 514140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng switch (Reg) { 515140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng default: break; 516140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::SP: 517140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::PC: 518140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 519140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R7: 520140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R11: 521140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 522140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return true; 523140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng break; 524140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng case ARM::R9: 525140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return STI.isR9Reserved(); 526140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 527140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 528140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return false; 529140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 530140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 531140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengbool 53236230cdda48edf6c634f2dcf69f9d78ac5a17377Evan ChengARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 53336230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 534e6257632fc2cc79a76ff0b5ba213f6ba2a7c469aEvan Cheng return ThumbRegScavenging || !AFI->isThumbFunction(); 5351b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng} 5361b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng 537a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// hasFP - Return true if the specified function should have a dedicated frame 538a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// pointer register. This is true if the function has variable sized allocas 539a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// or if frame pointer elimination is disabled. 540a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 541dc77540d9506dc151d79b94bae88bd841880ef37Evan Chengbool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 542a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 544a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5455c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 5465c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// not required, we reserve argument space for call sites in the function 5475c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// immediately on entry to the current function. This eliminates the need for 5485c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// add/sub sp brackets around call sites. Returns true if the call frame is 5495c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng// included as part of the stack frame. 5505c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Chengbool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { 5515c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 5525c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng unsigned CFSize = FFI->getMaxCallFrameSize(); 5535c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 5545c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // It's not always a good idea to include the call frame as part of the 5555c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // stack frame. ARM (especially Thumb) has small immediate offset to 5565c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // address the stack frame. So a large call frame can cause poor codegen 5575c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng // and may even makes it impossible to scavenge a register. 5585c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (AFI->isThumbFunction()) { 5595c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 5605c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return false; 5615c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng } else { 5625c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 5635c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng return false; 5645c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng } 5654558b807a2076e199bcb019f5edc9eabbc5922c1Evan Cheng return !MF.getFrameInfo()->hasVarSizedObjects(); 5665c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng} 5675c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng 56836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 569a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in ARM code. 570a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 571a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 572a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 5733b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 5743b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 5753b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng const TargetInstrInfo &TII) { 576a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 577a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) NumBytes = -NumBytes; 578a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 579a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (NumBytes) { 580a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 582a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 583a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 584a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 585a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBytes &= ~ThisVal; 586a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 587a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 588a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 589a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(SOImmVal != -1 && "Bit extraction didn't work?"); 590a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new ADD / SUB. 592a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 59344bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng .addReg(BaseReg, false, false, true).addImm(SOImmVal) 59413ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 595a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 596a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 597a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 598a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 59936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// calcNumMI - Returns the number of instructions required to materialize 60036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// the specific add / sub r, c instruction. 60136640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 60236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumBits, unsigned Scale) { 60336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = 0; 60436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 60536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 60636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (Opc == ARM::tADDrSPi) { 60736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 60836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 60936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 61036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBits = 8; 6113d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 1; // Followed by a number of tADDi8. 61236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 61336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 61436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 61536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs += Bytes / Chunk; 61636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if ((Bytes % Chunk) != 0) 61736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 61836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (ExtraOpc) 61936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumMIs++; 62036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return NumMIs; 62136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 62236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 623403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 624403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 625403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng/// in a register using mov / mvn sequences or load the immediate from a 62636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// constpool entry. 62736640905e1b2b2f1179845acc46f3de02f972c8cEvan Chengstatic 628403e4a4725af21c267d4189fe88bc48bd438b08cEvan Chengvoid emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 62936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng MachineBasicBlock::iterator &MBBI, 63036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned DestReg, unsigned BaseReg, 631a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng int NumBytes, bool CanChangeCC, 632a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng const TargetInstrInfo &TII) { 6337142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool isHigh = !isLowRegister(DestReg) || 6347142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng (BaseReg != 0 && !isLowRegister(BaseReg)); 63536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng bool isSub = false; 63636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Subtract doesn't have high register version. Load the negative value 637a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // if either base or dest register is a high register. Also, if do not 638a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // issue sub as part of the sequence if condition register is to be 639a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // preserved. 640a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes < 0 && !isHigh && CanChangeCC) { 64136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng isSub = true; 64236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng NumBytes = -NumBytes; 64336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 64436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned LdReg = DestReg; 64536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) { 64636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng assert(BaseReg == ARM::SP && "Unexpected!"); 64736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng LdReg = ARM::R3; 6489f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12) 6495ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 65036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 651a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng 652a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (NumBytes <= 255 && NumBytes >= 0) 6539f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 6548bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng else if (NumBytes < 0 && NumBytes >= -255) { 6559f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 6565ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) 6575ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(LdReg, false, false, true); 6588bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } else 6593b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true); 6607142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng 66136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // Emit add / sub. 66236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 66336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); 6645ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng if (DestReg == ARM::SP || isSub) 6655ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(BaseReg).addReg(LdReg, false, false, true); 66636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng else 6675ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MIB.addReg(LdReg).addReg(BaseReg, false, false, true); 66836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg == ARM::SP) 6699f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3) 6705ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 67136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng} 67236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 67336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 674a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// a destreg = basereg + immediate in Thumb code. 675a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 676a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 677a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 678a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, unsigned BaseReg, 679a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes, const TargetInstrInfo &TII) { 680a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = NumBytes < 0; 681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Bytes = (unsigned)NumBytes; 682a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Bytes = -NumBytes; 683a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isMul4 = (Bytes & 3) == 0; 684a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isTwoAddr = false; 6858e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng bool DstNotEqBase = false; 686a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 1; 6875b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Scale = 1; 68836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int Opc = 0; 68936640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng int ExtraOpc = 0; 690a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 691a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (DestReg == BaseReg && BaseReg == ARM::SP) { 692a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 693a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 7; 6945b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 695a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 696a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 697a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (!isSub && BaseReg == ARM::SP) { 6985b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 403 6995b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // => 7005b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add sp, 100 * 4 7015b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng // r1 = add r1, 3 702a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!isMul4) { 703a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Bytes &= ~3; 704a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ExtraOpc = ARM::tADDi3; 705a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 706a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 7075b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 4; 708a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = ARM::tADDrSPi; 709a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 71036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // sp = sub sp, c 71136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r1 = sub sp, c 71236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // r8 = sub sp, c 71336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (DestReg != BaseReg) 7148e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng DstNotEqBase = true; 715a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 716a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 717a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 718a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 719a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 72036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 7218e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 72236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (NumMIs > Threshold) { 72336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // This will expand into too many instructions. Load the immediate from a 72436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // constpool entry. 725403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII); 72636640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng return; 72736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 72836640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 7298e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (DstNotEqBase) { 73036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng if (isLowRegister(DestReg) && isLowRegister(BaseReg)) { 73136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 73236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned Chunk = (1 << 3) - 1; 73336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 73436640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng Bytes -= ThisVal; 73536640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 7365ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true).addImm(ThisVal); 73736640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } else { 7389f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg) 7395ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, true); 74036640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 74136640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng BaseReg = DestReg; 74236640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng } 74336640905e1b2b2f1179845acc46f3de02f972c8cEvan Cheng 7445b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned Chunk = ((1 << NumBits) - 1) * Scale; 745a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (Bytes) { 746a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 7475b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Bytes -= ThisVal; 7485b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng ThisVal /= Scale; 749a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Build the new tADD / tSUB. 750a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isTwoAddr) 7513fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60Evan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); 752a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else { 7535ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng bool isKill = BaseReg != ARM::SP; 7545ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(Opc), DestReg) 7555ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(BaseReg, false, false, isKill).addImm(ThisVal); 756a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BaseReg = DestReg; 757a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 758a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opc == ARM::tADDrSPi) { 759a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add sp, imm 760a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r4 = add r4, imm 761a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ... 762a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 7635b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Scale = 1; 7645b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng Chunk = ((1 << NumBits) - 1) * Scale; 765a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 766a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isTwoAddr = true; 767a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 768a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 769a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 770a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 771a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ExtraOpc) 7725ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg) 7735ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true) 774a8e2989ece6dc46df59b0768184028257f913843Evan Cheng .addImm(((unsigned)NumBytes) & 3); 775a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 776a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 777a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic 778a8e2989ece6dc46df59b0768184028257f913843Evan Chengvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 7793b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, 7803b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng bool isThumb, const TargetInstrInfo &TII) { 781a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) 782a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); 783a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else 7843b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, 7853b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng Pred, PredReg, TII); 786a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 787a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 7887bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo:: 7897bc59bc3952ad7842b1e079753deb32217a768a3Rafael EspindolaeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 7907bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MachineBasicBlock::iterator I) const { 7915c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (!hasReservedCallFrame(MF)) { 792a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we have alloca, convert as follows: 793a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKDOWN -> sub, sp, sp, amount 794a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ADJCALLSTACKUP -> add, sp, sp, amount 795b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola MachineInstr *Old = I; 796b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Amount = Old->getOperand(0).getImmedValue(); 797b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola if (Amount != 0) { 798a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 799a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We need to keep the stack aligned properly. To do this, we round the 800a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // amount of space needed for the outgoing arguments up to the next 801a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // alignment boundary. 802b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 803b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola Amount = (Amount+Align-1)/Align*Align; 804b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola 805a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the pseudo instruction with a new instruction... 80644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng unsigned Opc = Old->getOpcode(); 80744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng bool isThumb = AFI->isThumbFunction(); 80844bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ARMCC::CondCodes Pred = isThumb 80944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue(); 81044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 8110f8d9c04d9feef86cee35cf5fecfb348a6b3de50Bill Wendling // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 8120f8d9c04d9feef86cee35cf5fecfb348a6b3de50Bill Wendling unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg(); 8133b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII); 814b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } else { 8150f8d9c04d9feef86cee35cf5fecfb348a6b3de50Bill Wendling // Note: PredReg is operand 3 for ADJCALLSTACKUP. 8160f8d9c04d9feef86cee35cf5fecfb348a6b3de50Bill Wendling unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg(); 81744bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 8183b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII); 819b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 820b191e0ab51174cfb86502308f520f139daa9e4a0Rafael Espindola } 8217ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola } 8227bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola MBB.erase(I); 8237bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 8247bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 825a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// emitThumbConstant - Emit a series of instructions to materialize a 826a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// constant. 827a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void emitThumbConstant(MachineBasicBlock &MBB, 828a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 829a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg, int Imm, 830a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrInfo &TII) { 831a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Imm < 0; 832a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) Imm = -Imm; 833a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 834a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Chunk = (1 << 8) - 1; 835a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisVal = (Imm > Chunk) ? Chunk : Imm; 836a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Imm -= ThisVal; 8379f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); 838a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Imm > 0) 839a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); 840a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 8415ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg) 8425ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(DestReg, false, false, true); 843a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 844a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 845c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// findScratchRegister - Find a 'free' ARM register. If register scavenger 846c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// is not being used, R12 is available. Otherwise, try for a call-clobbered 847c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng/// register first and then a spilled callee-saved register if that fails. 848c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengstatic 849c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Chengunsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 850c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng ARMFunctionInfo *AFI) { 851c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12; 852c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng if (Reg == 0) 853c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng // Try a already spilled CS register. 854c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters()); 855c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 856c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng return Reg; 857c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng} 858c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng 8591b051fc6a491c40cf3f926c089ad082938b653f0Evan Chengvoid ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 86097de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng int SPAdj, RegScavenger *RS) const{ 861a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned i = 0; 86258421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineInstr &MI = *II; 86358421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineBasicBlock &MBB = *MI.getParent(); 86458421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola MachineFunction &MF = *MBB.getParent(); 865a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 866a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 86758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 868a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (!MI.getOperand(i).isFrameIndex()) { 869a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++i; 870a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 871a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 872a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 873a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned FrameReg = ARM::SP; 874a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FrameIndex = MI.getOperand(i).getFrameIndex(); 875a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 87697de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng MF.getFrameInfo()->getStackSize() + SPAdj; 87758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 878a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 879a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea1Offset(); 880a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 881a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getGPRCalleeSavedArea2Offset(); 882a8e2989ece6dc46df59b0768184028257f913843Evan Cheng else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 883a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset -= AFI->getDPRCalleeSavedAreaOffset(); 88475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng else if (hasFP(MF)) { 88597de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng assert(SPAdj == 0 && "Unexpected"); 886a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // There is alloca()'s in this function, must reference off the frame 887a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // pointer instead. 888a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FrameReg = getFrameRegister(MF); 889b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7Lauro Ramos Venancio Offset -= AFI->getFramePtrSpillOffset(); 890a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 891a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 892a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Opcode = MI.getOpcode(); 893a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 894a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 895a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = false; 8963d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 897a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Opcode == ARM::ADDri) { 898a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 899a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 900a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 9019f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::MOVr)); 902a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 903a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 904a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 905a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Offset < 0) { 906a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 907a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 908a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::SUBri)); 909a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 91058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 911a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 912a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ImmedOffset = ARM_AM::getSOImmVal(Offset); 913a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ImmedOffset != -1) { 914a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 915a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 916a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 917a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 918a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 919a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 920a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we fallback to common code below to form the imm offset with 921a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // a sequence of ADDri instructions. First though, pull as much of the imm 922a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // into this ADDri as possible. 923a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 924b03eacdbf39b37a98b65b936046b22cca8215d8dEvan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 925a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 926a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // We will handle these bits from offset, clear them. 927a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset &= ~ThisImmVal; 928a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 929a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Get the properly encoded SOImmVal field. 930a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 931a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 932a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 933a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (Opcode == ARM::tADDrSPi) { 934a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += MI.getOperand(i+1).getImm(); 9353d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 9363d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng // Can't use tADDrSPi if it's based off the frame pointer. 9373d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumBits = 0; 9383d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Scale = 1; 9393d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (FrameReg != ARM::SP) { 9403d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Opcode = ARM::tADDi3; 9413d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDi3)); 9423d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 3; 9433d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } else { 9443d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng NumBits = 8; 9453d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Scale = 4; 9463d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng assert((Offset & 3) == 0 && 9473d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 9483d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng } 9493d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng 950a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset == 0) { 951a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Turn it into a move. 9529f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tMOVr)); 953a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 954a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.RemoveOperand(i+1); 955a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 956a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 957a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 958a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Common case: small offset, fits into instruction. 9593d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned Mask = (1 << NumBits) - 1; 9603d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng if (((Offset / Scale) & ~Mask) == 0) { 961a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Replace the FrameIndex with sp / fp 962a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 9633d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset / Scale); 964a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 965a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 966a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 967a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned DestReg = MI.getOperand(0).getReg(); 968a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng unsigned Bytes = (Offset > 0) ? Offset : -Offset; 9693d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale); 970a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // MI would expand into a large number of instructions. Don't try to 971a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng // simplify the immediate. 972a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng if (NumMIs > 2) { 97388b633165a20398d1015eec561856500fcf30d7dEvan Cheng emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII); 974a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng MBB.erase(II); 975a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng return; 976a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng } 977a21335dd763ab98ef3cf98e7a0573367c6dc845fEvan Cheng 978a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Offset > 0) { 979a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, imm to 980a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add sp, 255*4 981a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, (imm - 255*4) 982a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 9833d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng MI.getOperand(i+1).ChangeToImmediate(Mask); 9843d06cf4584b44ea8c4a49778c2b61f8990692157Evan Cheng Offset = (Offset - Mask * Scale); 985a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator NII = next(II); 986a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII); 987a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 988a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Translate r0 = add sp, -imm to 989a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = -imm (this is then translated into a series of instructons) 990a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r0 = add r0, sp 991a8e2989ece6dc46df59b0768184028257f913843Evan Cheng emitThumbConstant(MBB, II, DestReg, Offset, TII); 992a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); 9935ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); 994a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 995a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 996a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return; 997a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else { 998a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ImmIdx = 0; 999a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int InstrOffs = 0; 1000a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBits = 0; 1001a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Scale = 1; 1002a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (AddrMode) { 1003a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode2: { 1004a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 1005a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 1006a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1007a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 1008a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 12; 1009a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1010a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1011a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode3: { 1012a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+2; 1013a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 1014a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1015a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 1016a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 1017a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1018a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1019a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrMode5: { 1020a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 1021a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 1022a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1023a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs *= -1; 1024a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumBits = 8; 1025a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Scale = 4; 1026a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1027a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1028a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARMII::AddrModeTs: { 1029a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmIdx = i+1; 1030a8e2989ece6dc46df59b0768184028257f913843Evan Cheng InstrOffs = MI.getOperand(ImmIdx).getImm(); 10317142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng NumBits = (FrameReg == ARM::SP) ? 8 : 5; 10327142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng Scale = 4; 1033a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1034a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1035a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 10368fdbe560a0bc600121f1f2de10638c7b5d58a47aEvan Cheng assert(0 && "Unsupported addressing mode!"); 1037a8e2989ece6dc46df59b0768184028257f913843Evan Cheng abort(); 1038a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1039a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 104058421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 1041a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset += InstrOffs * Scale; 10429312313a56ca3d4d904e8f7e9b4fe152a293eae1Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 1043a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng if (Offset < 0 && !isThumb) { 1044a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Offset = -Offset; 1045a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isSub = true; 1046a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 104758421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 1048a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // Common case: small offset, fits into instruction. 10498e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 10508e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng int ImmedOffset = Offset / Scale; 10518e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng unsigned Mask = (1 << NumBits) - 1; 10528e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if ((unsigned)Offset <= Mask * Scale) { 10538e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng // Replace the FrameIndex with sp 10548e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false); 10558e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng if (isSub) 10568e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmedOffset |= 1 << NumBits; 10578e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 10588e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng return; 10598e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng } 106088b633165a20398d1015eec561856500fcf30d7dEvan Cheng 10615ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 10625ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs) { 10635ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // Thumb tLDRspi, tSTRspi. These will change to instructions that use 10645ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng // a different base register. 10655ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng NumBits = 5; 10665ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng Mask = (1 << NumBits) - 1; 10675ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng } 1068a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // If this is a thumb spill / restore, we will be using a constpool load to 1069a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng // materialize the offset. 10705ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 10715ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng ImmOp.ChangeToImmediate(0); 10725ebd10e5ac6f7746f228da3e37729760a1903a1eEvan Cheng else { 107388b633165a20398d1015eec561856500fcf30d7dEvan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 107488b633165a20398d1015eec561856500fcf30d7dEvan Cheng ImmedOffset = ImmedOffset & Mask; 1075a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isSub) 1076a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmedOffset |= 1 << NumBits; 1077a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 107888b633165a20398d1015eec561856500fcf30d7dEvan Cheng Offset &= ~(Mask*Scale); 1079a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1080a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1081a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1082a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we get here, the immediate doesn't fit into the instruction. We folded 1083a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // as much as possible above, handle the rest, providing a register that is 1084a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // SP+LargeImm. 1085a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Offset && "This code isn't needed if offset already handled!"); 108658421d7d0847bbb5f4cc95c647726d55c45582c0Rafael Espindola 1087a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (isThumb) { 1088a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (TII.isLoad(Opcode)) { 1089a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use the destination register to materialize sp + offset. 1090a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = MI.getOperand(0).getReg(); 10917142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 10927142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tRestore) { 10937142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 1094403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 10957142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 10963b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true); 10977142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 10987142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 10997142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 1100a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 11015b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tLDR)); 11025ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 11037142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 11047142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 11057142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 11065ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.addRegOperand(0, false); // tLDR has an extra register operand. 1107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else if (TII.isStore(Opcode)) { 1108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // FIXME! This is horrific!!! We need register scavenging. 1109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Our temporary workaround has marked r3 unavailable. Of course, r3 is 1110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // also a ABI register so it's possible that is is the register that is 1111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // being storing here. If that's the case, we do the following: 1112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r12 = r2 1113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use r2 to materialize sp + offset 11148bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // str r3, r2 1115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // r2 = r12 11165b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng unsigned ValReg = MI.getOperand(0).getReg(); 1117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TmpReg = ARM::R3; 11187142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng bool UseRR = false; 11195b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng if (ValReg == ARM::R3) { 11209f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 11215ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R2, false, false, true); 1122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng TmpReg = ARM::R2; 1123a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1124f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 11259f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) 11265ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R3, false, false, true); 11277142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (Opcode == ARM::tSpill) { 11287142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (FrameReg == ARM::SP) 1129403e4a4725af21c267d4189fe88bc48bd438b08cEvan Cheng emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); 11307142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else { 11313b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true); 11327142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng UseRR = true; 11337142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } 11347142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng } else 1135a01faf4a7ac34b2b89c93d62d3159a5c9c421149Evan Cheng emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII); 11365b91c7f69ac2dc19edec1dbf76e5a8667c67bd28Evan Cheng MI.setInstrDescriptor(TII.get(ARM::tSTR)); 11375ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 11387142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng if (UseRR) 11397142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode. 11407142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng else 11417142f8755a07512d909d288f74a3f1ffa9c1411aEvan Cheng MI.addRegOperand(0, false); // tSTR has an extra register operand. 11428bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 11438bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng MachineBasicBlock::iterator NII = next(II); 11448bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if (ValReg == ARM::R3) 11459f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2) 11465ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 1147f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 11489f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3) 11495ef9226f30d0615558cdfc6a2b76c7a914a8e32fEvan Cheng .addReg(ARM::R12, false, false, true); 1150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } else 1151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(false && "Unexpected opcode!"); 1152a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } else { 1153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Insert a set of r12 with the full address: r12 = sp + offset 1154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If the offset we have is too large to fit into the instruction, we need 1155a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to form it with a series of ADDri's. Do this by taking 8-bit chunks 1156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // out of 'Offset'. 1157c1c2de0ae7abecb4120dd28f722a2b73319b0cd8Evan Cheng unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); 1158140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (ScratchReg == 0) 1159140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // No register is "free". Scavenge a register. 116097de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); 116162ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng int PIdx = MI.findFirstPredOperandIdx(); 116262ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng ARMCC::CondCodes Pred = (PIdx == -1) 116362ccdbf0b3b75661bcdb20476609fece499c767fEvan Cheng ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue(); 11643b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 11653b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, 11663b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng isSub ? -Offset : Offset, Pred, PredReg, TII); 11671b051fc6a491c40cf3f926c089ad082938b653f0Evan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1168a4e64359aafaf23e440e9dc171859daef1995f1bRafael Espindola } 11697bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 11707bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1171140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengstatic unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 1172140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const MachineFrameInfo *FFI = MF.getFrameInfo(); 1173140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int Offset = 0; 1174140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 1175140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng int FixedOff = -FFI->getObjectOffset(i); 1176140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (FixedOff > Offset) Offset = FixedOff; 1177140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1178140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 1179140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset += FFI->getObjectSize(i); 1180140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Align = FFI->getObjectAlignment(i); 1181140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Adjust to alignment boundary 1182140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Offset = (Offset+Align-1)/Align*Align; 1183140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1184140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng return (unsigned)Offset; 1185140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng} 1186140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng 1187140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Chengvoid 1188140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan ChengARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1189140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RegScavenger *RS) const { 119075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // This tells PEI to spill the FP as if it is any other callee-save register 119175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // to take advantage the eliminateFrameIndex machinery. This also ensures it 119275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // is spilled in the order specified by getCalleeSavedRegs() to make it easier 1193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // to combine multiple loads / stores. 119475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool CanEliminateFrame = true; 1195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool CS1Spilled = false; 1196a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool LRSpilled = false; 1197a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumGPRSpills = 0; 1198a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS1GPRs; 1199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SmallVector<unsigned, 4> UnspilledCS2GPRs; 1200f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 120175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 120275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Don't spill FP if the frame can be eliminated. This is determined 120375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // by scanning the callee-save registers to see if any is used. 120475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const unsigned *CSRegs = getCalleeSavedRegs(); 120575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 120675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) { 120775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng unsigned Reg = CSRegs[i]; 120875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng bool Spilled = false; 120975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(Reg)) { 1210f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(Reg); 121175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 121275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 121375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 121475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Check alias registers too. 121575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 121675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (MF.isPhysRegUsed(*Aliases)) { 121775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng Spilled = true; 121875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CanEliminateFrame = false; 1219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 122175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 1222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 122375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (CSRegClasses[i] == &ARM::GPRRegClass) { 122475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng if (Spilled) { 122575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng NumGPRSpills++; 122675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng 1227c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1228c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (Reg == ARM::LR) 1229c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng LRSpilled = true; 1230356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio CS1Spilled = true; 1231c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1232c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1233c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 123475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 123575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 123675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 123775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng LRSpilled = true; 123875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng // Fallthrough 123975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 124075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 124175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 124275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 124375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng CS1Spilled = true; 124475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 124575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 124675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 124775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } 124875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng } else { 1249c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng if (!STI.isTargetDarwin()) { 1250c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng UnspilledCS1GPRs.push_back(Reg); 1251c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng continue; 1252c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng } 1253c1c728304731fe582afba73ddbb26b1dc59f5900Evan Cheng 125475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng switch (Reg) { 125575e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: 125675e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R5: 125775e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R6: 125875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R7: 125975e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::LR: 126075e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS1GPRs.push_back(Reg); 126175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 126275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng default: 126375e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng UnspilledCS2GPRs.push_back(Reg); 126475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng break; 1265a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1270d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng bool ForceLRSpill = false; 1271d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (!LRSpilled && AFI->isThumbFunction()) { 1272d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng unsigned FnSize = ARM::GetFunctionSize(MF); 1273f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // Force LR to be spilled if the Thumb function size is > 2048. This enables 1274d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng // use of BL to implement far jump. If it turns out that it's not needed 1275f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng // then the branch fix up path will undo it. 1276d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (FnSize >= (1 << 11)) { 1277d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng CanEliminateFrame = false; 1278d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = true; 1279d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1280d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1281d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng 1282140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng bool ExtraCSSpill = false; 12837588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (!CanEliminateFrame || hasFP(MF)) { 128475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng AFI->setHasStackFrame(true); 1285a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1286a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1287a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1288a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (!LRSpilled && CS1Spilled) { 12896c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(ARM::LR); 1290f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1291a8e2989ece6dc46df59b0768184028257f913843Evan Cheng NumGPRSpills++; 1292a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1293a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1294d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng ForceLRSpill = false; 1295140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng ExtraCSSpill = true; 1296a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1297a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 12983548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 12993548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 13007588ad478aa95a7eb109034f0496f6d5a9769103Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 13016c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(FramePtr); 13023548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng NumGPRSpills++; 13033548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng } 13043548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1305356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // If stack and double are 8-byte aligned and we are spilling an odd number 1306356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // of GPRs. Spill one extra callee save GPR so we won't have to pad between 1307356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // the integer and double callee save areas. 1308356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1309356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1310356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1311356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1312356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned Reg = UnspilledCS1GPRs[i]; 1313356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio // Don't spiil high register if the function is thumb 1314356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) { 1315356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Reg); 1316356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Reg); 1317356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!isReservedReg(MF, Reg)) 1318356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio ExtraCSSpill = true; 1319356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio break; 1320356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1321356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1322356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } else if (!UnspilledCS2GPRs.empty() && 1323356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio !AFI->isThumbFunction()) { 1324356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned Reg = UnspilledCS2GPRs.front(); 1325356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Reg); 1326356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Reg); 1327356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (!isReservedReg(MF, Reg)) 1328356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio ExtraCSSpill = true; 1329356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1330356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1331356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio 1332140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Estimate if we might need to scavenge a register at some point in order 1333140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // to materialize a stack offset. If so, either spill one additiona 1334140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // callee-saved register or reserve a special spill slot to facilitate 1335140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // register scavenging. 1336140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) { 1337140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng MachineFrameInfo *MFI = MF.getFrameInfo(); 1338140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Size = estimateStackSize(MF, MFI); 1339140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Limit = (1 << 12) - 1; 1340140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) 1341140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) { 1342140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) 1343140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (I->getOperand(i).isFrameIndex()) { 1344140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Opcode = I->getOpcode(); 1345140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetInstrDescriptor &Desc = TII.get(Opcode); 1346140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1347140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (AddrMode == ARMII::AddrMode3) { 1348140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng Limit = (1 << 8) - 1; 1349140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng goto DoneEstimating; 1350140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else if (AddrMode == ARMII::AddrMode5) { 13515c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng unsigned ThisLimit = ((1 << 8) - 1) * 4; 13525c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng if (ThisLimit < Limit) 13535c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5Evan Cheng Limit = ThisLimit; 1354140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1355140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1356140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1357140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng DoneEstimating: 1358140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (Size >= Limit) { 1359140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // If any non-reserved CS register isn't spilled, just spill one or two 1360140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // extra. That should take care of it! 1361356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio unsigned NumExtras = TargetAlign / 4; 1362356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio SmallVector<unsigned, 2> Extras; 1363356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio while (NumExtras && !UnspilledCS1GPRs.empty()) { 1364140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS1GPRs.back(); 1365140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS1GPRs.pop_back(); 1366140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1367356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio Extras.push_back(Reg); 1368356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio NumExtras--; 1369140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1370140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1371356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio while (NumExtras && !UnspilledCS2GPRs.empty()) { 1372140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng unsigned Reg = UnspilledCS2GPRs.back(); 1373140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng UnspilledCS2GPRs.pop_back(); 1374140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng if (!isReservedReg(MF, Reg)) { 1375356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio Extras.push_back(Reg); 1376356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio NumExtras--; 1377140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1378140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1379356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio if (Extras.size() && NumExtras == 0) { 1380356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1381356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio MF.setPhysRegUsed(Extras[i]); 1382356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio AFI->setCSRegisterIsSpilled(Extras[i]); 1383356e72c4f1a90b0ff306838e8841b9b550460cd9Lauro Ramos Venancio } 1384140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } else { 1385140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng // Reserve a slot closest to SP or frame pointer. 1386140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng const TargetRegisterClass *RC = &ARM::GPRRegClass; 1387140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1388140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng RC->getAlignment())); 1389140e33cfd1386b65bc936c7346d1b1cb72b26caeEvan Cheng } 1390f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng } 1391a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1392a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 139378268b943669cd0c0e1e874e2a329fcf200bd59bEvan Cheng 1394d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng if (ForceLRSpill) { 13956c087e5585b227f3c1d8278304c7cfbc7cd4f6e8Evan Cheng MF.setPhysRegUsed(ARM::LR); 1396f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setCSRegisterIsSpilled(ARM::LR); 1397f49407b790d8664d8ff9c103931b115ebe9cc96eEvan Cheng AFI->setLRIsSpilledForFarJump(true); 1398d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fdEvan Cheng } 1399a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1400a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1401a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// Move iterator pass the next bunch of callee save load / store ops for 1402a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// the particular spill area (1: integer area 1, 2: integer area 2, 1403a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// 3: fp area, 0: don't care). 1404a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1405a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MachineBasicBlock::iterator &MBBI, 1406a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int Opc, unsigned Area, 1407a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget &STI) { 1408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng while (MBBI != MBB.end() && 1409a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { 1410a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Area != 0) { 1411a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool Done = false; 1412a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Category = 0; 1413a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (MBBI->getOperand(0).getReg()) { 141475e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1415a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM::LR: 1416a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 1; 1417a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 141875e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1419970a419633ba41cac44ae636543f192ea632fe00Evan Cheng Category = STI.isTargetDarwin() ? 2 : 1; 1420a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 142175e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 142275e18c403e4046057cb99accb3afc7cdf6fadd61Evan Cheng case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1423a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Category = 3; 1424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1425a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: 1426a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Done = true; 1427a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1428a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1429a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Done || Category != Area) 1430a8e2989ece6dc46df59b0768184028257f913843Evan Cheng break; 1431a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1432a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1433a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ++MBBI; 1434a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1435a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 14367bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 14377bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1438355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock &MBB = MF.front(); 143944819cb20ab8e84fc14ea1e6fc69fb797c70a50dRafael Espindola MachineBasicBlock::iterator MBBI = MBB.begin(); 1440355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1441a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1442a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1443a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1444a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned NumBytes = MFI->getStackSize(); 1445a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1446355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1447236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (isThumb) { 14488bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng // Check if R3 is live in. It might have to be used as a scratch register. 14498bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); 14508bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng I != E; ++I) { 14518bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng if ((*I).first == ARM::R3) { 14528bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng AFI->setR3IsLiveIn(true); 14538bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng break; 14548bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 14558bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng } 14568bed6c968fd7164222bc0cf4b86686c88381c3b8Evan Cheng 1457236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1458236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = (NumBytes + 3) & ~3; 1459236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng MFI->setStackSize(NumBytes); 1460236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1461236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1462a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine the sizes of each callee-save spill areas and record which frame 1463a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // belongs to which callee-save spill areas. 1464a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1465a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int FramePtrSpillFI = 0; 1466acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1467acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (VARegSaveSize) 14683b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII); 1469acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1470236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1471236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 14723b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII); 1473236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng return; 1474236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1475236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1476236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1477236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned Reg = CSI[i].getReg(); 1478236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng int FI = CSI[i].getFrameIdx(); 1479236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng switch (Reg) { 1480236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R4: 1481236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R5: 1482236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R6: 1483236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R7: 1484236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::LR: 1485236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1486236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1487236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1488236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS1Size += 4; 1489236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1490236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R8: 1491236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R9: 1492236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R10: 1493236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng case ARM::R11: 1494236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (Reg == FramePtr) 1495236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng FramePtrSpillFI = FI; 1496236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (STI.isTargetDarwin()) { 1497236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addGPRCalleeSavedArea2Frame(FI); 1498236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng GPRCS2Size += 4; 1499236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else { 1500a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->addGPRCalleeSavedArea1Frame(FI); 1501a8e2989ece6dc46df59b0768184028257f913843Evan Cheng GPRCS1Size += 4; 1502a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1503236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng break; 1504236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng default: 1505236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->addDPRCalleeSavedAreaFrame(FI); 1506236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng DPRCSSize += 8; 1507a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1508236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 1509a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1510236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1511236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 1. 15123b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII); 1513236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1514236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) 1515236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng ++MBBI; 1516a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 15173548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // Darwin ABI requires FP to point to the stack slot that contains the 15183548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng // previous FP. 151944bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng if (STI.isTargetDarwin() || hasFP(MF)) { 152044bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng MachineInstrBuilder MIB = 152144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr) 1522236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng .addFrameIndex(FramePtrSpillFI).addImm(0); 152366f0f640820b61cf9db814b6d187bae9faf7279cEvan Cheng if (!isThumb) AddDefaultCC(AddDefaultPred(MIB)); 152444bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng } 1525a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1526236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) { 1527236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for integer callee-save spill area 2. 15283b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII); 1529a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1530236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Build the new SUBri to adjust SP for FP callee-save spill area. 1531236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 15323b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII); 1533a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 15347ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1535a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Determine starting offsets of spill areas. 1536236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1537236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1538236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1539236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1540236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1541236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1542236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1543a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1544236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng NumBytes = DPRCSOffset; 1545236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) { 1546236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng // Insert it after all the callee-save spills. 1547236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!isThumb) 1548236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 15493b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII); 1550236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng } 155115f17a7c4746b8533aabf7c78bde82503ad9fc9fRafael Espindola 1552e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio if(STI.isTargetELF() && hasFP(MF)) { 1553e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1554e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio AFI->getFramePtrSpillOffset()); 1555e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio } 1556e8e5495474d67cd5151bd88e502be3f46ace7a85Lauro Ramos Venancio 1557a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1558a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1559a8e2989ece6dc46df59b0768184028257f913843Evan Cheng AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1560a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 15617ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362Rafael Espindola 1562a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1563a8e2989ece6dc46df59b0768184028257f913843Evan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 1564a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (Reg == CSRegs[i]) 1565a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return true; 1566a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 1567a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 1568a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1569a8e2989ece6dc46df59b0768184028257f913843Evan Chengstatic bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1570a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((MI->getOpcode() == ARM::FLDD || 1571a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOpcode() == ARM::LDR || 15728e59ea998f1357768aa43cb00187e6c1c1a1cc7eEvan Cheng MI->getOpcode() == ARM::tRestore) && 1573a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MI->getOperand(1).isFrameIndex() && 1574a8e2989ece6dc46df59b0768184028257f913843Evan Cheng isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 15757bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 15767bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 15777bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolavoid ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 1578bed2946a96ecb15b0b636fa74cb26ce61b1c648eAnton Korobeynikov MachineBasicBlock &MBB) const { 1579355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1580a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert((MBBI->getOpcode() == ARM::BX_RET || 1581a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tBX_RET || 1582a8e2989ece6dc46df59b0768184028257f913843Evan Cheng MBBI->getOpcode() == ARM::tPOP_RET) && 1583355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola "Can only insert epilog into returning blocks"); 1584355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola 1585355746359ebca83ccb5accab0f3ffd20f0374a35Rafael Espindola MachineFrameInfo *MFI = MF.getFrameInfo(); 1586a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1587a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isThumb = AFI->isThumbFunction(); 1588a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1589a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int NumBytes = (int)MFI->getStackSize(); 1590236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (!AFI->hasStackFrame()) { 1591236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes != 0) 15923b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 15939d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } else { 1594acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Unwind MBBI to point to first LDR / FLDD. 1595acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio const unsigned *CSRegs = getCalleeSavedRegs(); 1596acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI != MBB.begin()) { 1597acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio do 1598acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio --MBBI; 1599acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1600acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (!isCSRestore(MBBI, CSRegs)) 1601acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio ++MBBI; 1602acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1603acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio 1604acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of FP callee save spill area. 1605acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1606acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getGPRCalleeSavedArea2Size() + 1607acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize()); 1608acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (isThumb) { 1609acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (hasFP(MF)) { 1610acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1611acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1612acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1613236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng if (NumBytes) 1614acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); 1615236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng else 16169f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); 1617acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1618acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (MBBI->getOpcode() == ARM::tBX_RET && 1619acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio &MBB.front() != MBBI && 1620acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio prior(MBBI)->getOpcode() == ARM::tPOP) { 1621acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio MachineBasicBlock::iterator PMBBI = prior(MBBI); 16223b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 1623acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else 16243b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); 1625acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1626acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else { 1627acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Darwin ABI requires FP to point to the stack slot that contains the 1628acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // previous FP. 16299f8e50d4ed7dcc5ca0f137830ff1185b2afa38bfDale Johannesen if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) { 1630acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1631acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Reset SP based on frame pointer only if the stack frame extends beyond 1632acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // frame pointer stack slot or target is ELF and the function has FP. 1633acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (AFI->getGPRCalleeSavedArea2Size() || 1634acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaSize() || 1635acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio AFI->getDPRCalleeSavedAreaOffset()|| 1636acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio hasFP(MF)) 1637acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio if (NumBytes) 1638acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 163913ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm(NumBytes) 164013ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1641acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio else 164244bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr) 164313ab020ea08826f1b87db6ec3da63889a12e3d9dEvan Cheng .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1644acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } else if (NumBytes) { 16453b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII); 1646acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 16473548006a29ea9e5b63b53c9923fff96326fdc302Evan Cheng 1648acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 2. 1649acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 16503b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0, 165144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1652236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1653acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to start of integer callee save spill area 1. 1654acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 16553b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0, 165644bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1657236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 1658acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio // Move SP to SP upon entry to the function. 1659acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 16603b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0, 166144bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4Evan Cheng false, TII); 1662acdfa445ac370cbf392234e9176c98f46bb3f672Lauro Ramos Venancio } 1663a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 1664236f677e48d45847ac10614bb9923129a028a4dfEvan Cheng 16659d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng if (VARegSaveSize) { 1666f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) 1667f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // Epilogue for vararg functions: pop LR to R3 and branch off it. 1668f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng // FIXME: Verify this is still ok when R3 is no longer being reserved. 1669f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); 1670f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 16713b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1eEvan Cheng emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII); 1672f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng 1673f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng if (isThumb) { 1674f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1675f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng MBB.erase(MBBI); 1676f48ae3353eafcd9f5dd26fd9d76d87674328b78eEvan Cheng } 16779d945f78e5d26dac6778665bd7018a8fb3fd38c5Evan Cheng } 16787bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 16797bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 16807bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getRARegister() const { 1681a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ARM::LR; 16827bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 16837bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 16847bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindolaunsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1685267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio if (STI.isTargetDarwin() || hasFP(MF)) 16864c6d20a096ad28aa6f812c07a48268e8a6ccb8feLauro Ramos Venancio return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11; 1687267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio else 1688267bfb553e3ab44de2d4bac2866afc6de808c3f8Lauro Ramos Venancio return ARM::SP; 16897bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola} 16907bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 169162819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHExceptionRegister() const { 169262819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception register"); 169362819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 169462819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 169562819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 169662819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned ARMRegisterInfo::getEHHandlerRegister() const { 169762819f31440fe1b1415473a89b8683b5b690d5faJim Laskey assert(0 && "What is the exception handler register"); 169862819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return 0; 169962819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 170062819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 1701b97aec663b1591e71c9ddee6dbb327d1b827eda5Dale Johannesenint ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1702f191c80cd79ee35e47b5a4feed98d687782dfe85Anton Korobeynikov assert(0 && "What is the dwarf register number"); 1703f191c80cd79ee35e47b5a4feed98d687782dfe85Anton Korobeynikov return -1; 1704f191c80cd79ee35e47b5a4feed98d687782dfe85Anton Korobeynikov} 1705f191c80cd79ee35e47b5a4feed98d687782dfe85Anton Korobeynikov 17067bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola#include "ARMGenRegisterInfo.inc" 17077bc59bc3952ad7842b1e079753deb32217a768a3Rafael Espindola 1708