ARMSchedule.td revision d0c6bc220433fab06bc1507f963ea5883fdc4f69 
1//===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Instruction Itinerary classes used for ARM
12//
13def IIC_iALUx      : InstrItinClass;
14def IIC_iALUi      : InstrItinClass;
15def IIC_iALUr      : InstrItinClass;
16def IIC_iALUsi     : InstrItinClass;
17def IIC_iALUsir    : InstrItinClass;
18def IIC_iALUsr     : InstrItinClass;
19def IIC_iBITi      : InstrItinClass;
20def IIC_iBITr      : InstrItinClass;
21def IIC_iBITsi     : InstrItinClass;
22def IIC_iBITsr     : InstrItinClass;
23def IIC_iUNAr      : InstrItinClass;
24def IIC_iUNAsi     : InstrItinClass;
25def IIC_iEXTr      : InstrItinClass;
26def IIC_iEXTAr     : InstrItinClass;
27def IIC_iEXTAsr    : InstrItinClass;
28def IIC_iCMPi      : InstrItinClass;
29def IIC_iCMPr      : InstrItinClass;
30def IIC_iCMPsi     : InstrItinClass;
31def IIC_iCMPsr     : InstrItinClass;
32def IIC_iTSTi      : InstrItinClass;
33def IIC_iTSTr      : InstrItinClass;
34def IIC_iTSTsi     : InstrItinClass;
35def IIC_iTSTsr     : InstrItinClass;
36def IIC_iMOVi      : InstrItinClass;
37def IIC_iMOVr      : InstrItinClass;
38def IIC_iMOVsi     : InstrItinClass;
39def IIC_iMOVsr     : InstrItinClass;
40def IIC_iMOVix2    : InstrItinClass;
41def IIC_iMVNi      : InstrItinClass;
42def IIC_iMVNr      : InstrItinClass;
43def IIC_iMVNsi     : InstrItinClass;
44def IIC_iMVNsr     : InstrItinClass;
45def IIC_iCMOVi     : InstrItinClass;
46def IIC_iCMOVr     : InstrItinClass;
47def IIC_iCMOVsi    : InstrItinClass;
48def IIC_iCMOVsr    : InstrItinClass;
49def IIC_iMUL16     : InstrItinClass;
50def IIC_iMAC16     : InstrItinClass;
51def IIC_iMUL32     : InstrItinClass;
52def IIC_iMAC32     : InstrItinClass;
53def IIC_iMUL64     : InstrItinClass;
54def IIC_iMAC64     : InstrItinClass;
55def IIC_iLoad_i    : InstrItinClass;
56def IIC_iLoad_r    : InstrItinClass;
57def IIC_iLoad_si   : InstrItinClass;
58def IIC_iLoad_iu   : InstrItinClass;
59def IIC_iLoad_ru   : InstrItinClass;
60def IIC_iLoad_siu  : InstrItinClass;
61def IIC_iLoad_bh_i   : InstrItinClass;
62def IIC_iLoad_bh_r   : InstrItinClass;
63def IIC_iLoad_bh_si  : InstrItinClass;
64def IIC_iLoad_bh_iu  : InstrItinClass;
65def IIC_iLoad_bh_ru  : InstrItinClass;
66def IIC_iLoad_bh_siu : InstrItinClass;
67def IIC_iLoad_d_i  : InstrItinClass;
68def IIC_iLoad_d_r  : InstrItinClass;
69def IIC_iLoad_d_ru : InstrItinClass;
70def IIC_iLoad_m    : InstrItinClass<0>;  // micro-coded
71def IIC_iLoad_mu   : InstrItinClass<0>;  // micro-coded
72def IIC_iLoad_mBr  : InstrItinClass<0>;  // micro-coded
73def IIC_iPop       : InstrItinClass<0>;  // micro-coded
74def IIC_iPop_Br    : InstrItinClass<0>;  // micro-coded
75def IIC_iLoadiALU  : InstrItinClass;
76def IIC_iStore_i   : InstrItinClass;
77def IIC_iStore_r   : InstrItinClass;
78def IIC_iStore_si  : InstrItinClass;
79def IIC_iStore_iu  : InstrItinClass;
80def IIC_iStore_ru  : InstrItinClass;
81def IIC_iStore_siu : InstrItinClass;
82def IIC_iStore_bh_i   : InstrItinClass;
83def IIC_iStore_bh_r   : InstrItinClass;
84def IIC_iStore_bh_si  : InstrItinClass;
85def IIC_iStore_bh_iu  : InstrItinClass;
86def IIC_iStore_bh_ru  : InstrItinClass;
87def IIC_iStore_bh_siu : InstrItinClass;
88def IIC_iStore_d_i   : InstrItinClass;
89def IIC_iStore_d_r   : InstrItinClass;
90def IIC_iStore_d_ru  : InstrItinClass;
91def IIC_iStore_m   : InstrItinClass<0>;  // micro-coded
92def IIC_iStore_mu  : InstrItinClass<0>;  // micro-coded
93def IIC_Br         : InstrItinClass;
94def IIC_fpSTAT     : InstrItinClass;
95def IIC_fpUNA32    : InstrItinClass;
96def IIC_fpUNA64    : InstrItinClass;
97def IIC_fpCMP32    : InstrItinClass;
98def IIC_fpCMP64    : InstrItinClass;
99def IIC_fpCVTSD    : InstrItinClass;
100def IIC_fpCVTDS    : InstrItinClass;
101def IIC_fpCVTSH    : InstrItinClass;
102def IIC_fpCVTHS    : InstrItinClass;
103def IIC_fpCVTIS    : InstrItinClass;
104def IIC_fpCVTID    : InstrItinClass;
105def IIC_fpCVTSI    : InstrItinClass;
106def IIC_fpCVTDI    : InstrItinClass;
107def IIC_fpMOVIS    : InstrItinClass;
108def IIC_fpMOVID    : InstrItinClass;
109def IIC_fpMOVSI    : InstrItinClass;
110def IIC_fpMOVDI    : InstrItinClass;
111def IIC_fpALU32    : InstrItinClass;
112def IIC_fpALU64    : InstrItinClass;
113def IIC_fpMUL32    : InstrItinClass;
114def IIC_fpMUL64    : InstrItinClass;
115def IIC_fpMAC32    : InstrItinClass;
116def IIC_fpMAC64    : InstrItinClass;
117def IIC_fpDIV32    : InstrItinClass;
118def IIC_fpDIV64    : InstrItinClass;
119def IIC_fpSQRT32   : InstrItinClass;
120def IIC_fpSQRT64   : InstrItinClass;
121def IIC_fpLoad32   : InstrItinClass;
122def IIC_fpLoad64   : InstrItinClass;
123def IIC_fpLoad_m   : InstrItinClass<0>;  // micro-coded
124def IIC_fpLoad_mu  : InstrItinClass<0>;  // micro-coded
125def IIC_fpStore32  : InstrItinClass;
126def IIC_fpStore64  : InstrItinClass;
127def IIC_fpStore_m  : InstrItinClass<0>;  // micro-coded
128def IIC_fpStore_mu : InstrItinClass<0>;  // micro-coded
129def IIC_VLD1       : InstrItinClass;
130def IIC_VLD1x2     : InstrItinClass;
131def IIC_VLD1x3     : InstrItinClass;
132def IIC_VLD1x4     : InstrItinClass;
133def IIC_VLD1u      : InstrItinClass;
134def IIC_VLD1x2u    : InstrItinClass;
135def IIC_VLD1x3u    : InstrItinClass;
136def IIC_VLD1x4u    : InstrItinClass;
137def IIC_VLD1ln     : InstrItinClass;
138def IIC_VLD1lnu    : InstrItinClass;
139def IIC_VLD2       : InstrItinClass;
140def IIC_VLD2x2     : InstrItinClass;
141def IIC_VLD2u      : InstrItinClass;
142def IIC_VLD2x2u    : InstrItinClass;
143def IIC_VLD2ln     : InstrItinClass;
144def IIC_VLD2lnu    : InstrItinClass;
145def IIC_VLD3       : InstrItinClass;
146def IIC_VLD3ln     : InstrItinClass;
147def IIC_VLD3u      : InstrItinClass;
148def IIC_VLD3lnu    : InstrItinClass;
149def IIC_VLD4       : InstrItinClass;
150def IIC_VLD4ln     : InstrItinClass;
151def IIC_VLD4u      : InstrItinClass;
152def IIC_VLD4lnu    : InstrItinClass;
153def IIC_VST1       : InstrItinClass;
154def IIC_VST1x2     : InstrItinClass;
155def IIC_VST1x3     : InstrItinClass;
156def IIC_VST1x4     : InstrItinClass;
157def IIC_VST1u      : InstrItinClass;
158def IIC_VST1x2u    : InstrItinClass;
159def IIC_VST1x3u    : InstrItinClass;
160def IIC_VST1x4u    : InstrItinClass;
161def IIC_VST1ln     : InstrItinClass;
162def IIC_VST1lnu    : InstrItinClass;
163def IIC_VST2       : InstrItinClass;
164def IIC_VST2x2     : InstrItinClass;
165def IIC_VST2u      : InstrItinClass;
166def IIC_VST2x2u    : InstrItinClass;
167def IIC_VST2ln     : InstrItinClass;
168def IIC_VST2lnu    : InstrItinClass;
169def IIC_VST3       : InstrItinClass;
170def IIC_VST3u      : InstrItinClass;
171def IIC_VST3ln     : InstrItinClass;
172def IIC_VST3lnu    : InstrItinClass;
173def IIC_VST4       : InstrItinClass;
174def IIC_VST4u      : InstrItinClass;
175def IIC_VST4ln     : InstrItinClass;
176def IIC_VST4lnu    : InstrItinClass;
177def IIC_VUNAD      : InstrItinClass;
178def IIC_VUNAQ      : InstrItinClass;
179def IIC_VBIND      : InstrItinClass;
180def IIC_VBINQ      : InstrItinClass;
181def IIC_VPBIND     : InstrItinClass;
182def IIC_VFMULD     : InstrItinClass;
183def IIC_VFMULQ     : InstrItinClass;
184def IIC_VMOV       : InstrItinClass;
185def IIC_VMOVImm    : InstrItinClass;
186def IIC_VMOVD      : InstrItinClass;
187def IIC_VMOVQ      : InstrItinClass;
188def IIC_VMOVIS     : InstrItinClass;
189def IIC_VMOVID     : InstrItinClass;
190def IIC_VMOVISL    : InstrItinClass;
191def IIC_VMOVSI     : InstrItinClass;
192def IIC_VMOVDI     : InstrItinClass;
193def IIC_VMOVN      : InstrItinClass;
194def IIC_VPERMD     : InstrItinClass;
195def IIC_VPERMQ     : InstrItinClass;
196def IIC_VPERMQ3    : InstrItinClass;
197def IIC_VMACD      : InstrItinClass;
198def IIC_VMACQ      : InstrItinClass;
199def IIC_VRECSD     : InstrItinClass;
200def IIC_VRECSQ     : InstrItinClass;
201def IIC_VCNTiD     : InstrItinClass;
202def IIC_VCNTiQ     : InstrItinClass;
203def IIC_VUNAiD     : InstrItinClass;
204def IIC_VUNAiQ     : InstrItinClass;
205def IIC_VQUNAiD    : InstrItinClass;
206def IIC_VQUNAiQ    : InstrItinClass;
207def IIC_VBINiD     : InstrItinClass;
208def IIC_VBINiQ     : InstrItinClass;
209def IIC_VSUBiD     : InstrItinClass;
210def IIC_VSUBiQ     : InstrItinClass;
211def IIC_VBINi4D    : InstrItinClass;
212def IIC_VBINi4Q    : InstrItinClass;
213def IIC_VSUBi4D    : InstrItinClass;
214def IIC_VSUBi4Q    : InstrItinClass;
215def IIC_VABAD      : InstrItinClass;
216def IIC_VABAQ      : InstrItinClass;
217def IIC_VSHLiD     : InstrItinClass;
218def IIC_VSHLiQ     : InstrItinClass;
219def IIC_VSHLi4D    : InstrItinClass;
220def IIC_VSHLi4Q    : InstrItinClass;
221def IIC_VPALiD     : InstrItinClass;
222def IIC_VPALiQ     : InstrItinClass;
223def IIC_VMULi16D   : InstrItinClass;
224def IIC_VMULi32D   : InstrItinClass;
225def IIC_VMULi16Q   : InstrItinClass;
226def IIC_VMULi32Q   : InstrItinClass;
227def IIC_VMACi16D   : InstrItinClass;
228def IIC_VMACi32D   : InstrItinClass;
229def IIC_VMACi16Q   : InstrItinClass;
230def IIC_VMACi32Q   : InstrItinClass;
231def IIC_VEXTD      : InstrItinClass;
232def IIC_VEXTQ      : InstrItinClass;
233def IIC_VTB1       : InstrItinClass;
234def IIC_VTB2       : InstrItinClass;
235def IIC_VTB3       : InstrItinClass;
236def IIC_VTB4       : InstrItinClass;
237def IIC_VTBX1      : InstrItinClass;
238def IIC_VTBX2      : InstrItinClass;
239def IIC_VTBX3      : InstrItinClass;
240def IIC_VTBX4      : InstrItinClass;
241
242//===----------------------------------------------------------------------===//
243// Processor instruction itineraries.
244
245def GenericItineraries : ProcessorItineraries<[], [], []>;
246
247include "ARMScheduleV6.td"
248include "ARMScheduleA8.td"
249include "ARMScheduleA9.td"
250