ARMScheduleV6.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- ARMScheduleV6.td - ARM v6 Scheduling Definitions ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the itinerary class data for the ARM v6 processors. 11// 12//===----------------------------------------------------------------------===// 13 14// Model based on ARM1176 15// 16// Functional Units 17def V6_Pipe : FuncUnit; // pipeline 18 19// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual" 20// 21def ARMV6Itineraries : ProcessorItineraries< 22 [V6_Pipe], [], [ 23 // 24 // No operand cycles 25 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>, 26 // 27 // Binary Instructions that produce a result 28 InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 29 InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 30 InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 31 InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 32 // 33 // Bitwise Instructions that produce a result 34 InstrItinData<IIC_iBITi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 35 InstrItinData<IIC_iBITr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 36 InstrItinData<IIC_iBITsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 37 InstrItinData<IIC_iBITsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 38 // 39 // Unary Instructions that produce a result 40 InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 41 InstrItinData<IIC_iUNAsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 42 // 43 // Zero and sign extension instructions 44 InstrItinData<IIC_iEXTr , [InstrStage<1, [V6_Pipe]>], [1, 1]>, 45 InstrItinData<IIC_iEXTAr , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 46 InstrItinData<IIC_iEXTAsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 47 // 48 // Compare instructions 49 InstrItinData<IIC_iCMPi , [InstrStage<1, [V6_Pipe]>], [2]>, 50 InstrItinData<IIC_iCMPr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 51 InstrItinData<IIC_iCMPsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 52 InstrItinData<IIC_iCMPsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 53 // 54 // Test instructions 55 InstrItinData<IIC_iTSTi , [InstrStage<1, [V6_Pipe]>], [2]>, 56 InstrItinData<IIC_iTSTr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 57 InstrItinData<IIC_iTSTsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 58 InstrItinData<IIC_iTSTsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 59 // 60 // Move instructions, unconditional 61 InstrItinData<IIC_iMOVi , [InstrStage<1, [V6_Pipe]>], [2]>, 62 InstrItinData<IIC_iMOVr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 63 InstrItinData<IIC_iMOVsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 64 InstrItinData<IIC_iMOVsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 65 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [V6_Pipe]>, 66 InstrStage<1, [V6_Pipe]>], [2]>, 67 InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [V6_Pipe]>, 68 InstrStage<1, [V6_Pipe]>, 69 InstrStage<1, [V6_Pipe]>], [3]>, 70 InstrItinData<IIC_iMOVix2ld , [InstrStage<1, [V6_Pipe]>, 71 InstrStage<1, [V6_Pipe]>, 72 InstrStage<1, [V6_Pipe]>], [5]>, 73 // 74 // Move instructions, conditional 75 InstrItinData<IIC_iCMOVi , [InstrStage<1, [V6_Pipe]>], [3]>, 76 InstrItinData<IIC_iCMOVr , [InstrStage<1, [V6_Pipe]>], [3, 2]>, 77 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [V6_Pipe]>], [3, 1]>, 78 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>, 79 InstrItinData<IIC_iCMOVix2 , [InstrStage<1, [V6_Pipe]>, 80 InstrStage<1, [V6_Pipe]>], [4]>, 81 // 82 // MVN instructions 83 InstrItinData<IIC_iMVNi , [InstrStage<1, [V6_Pipe]>], [2]>, 84 InstrItinData<IIC_iMVNr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 85 InstrItinData<IIC_iMVNsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 86 InstrItinData<IIC_iMVNsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 87 88 // Integer multiply pipeline 89 // 90 InstrItinData<IIC_iMUL16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 91 InstrItinData<IIC_iMAC16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1, 2]>, 92 InstrItinData<IIC_iMUL32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1]>, 93 InstrItinData<IIC_iMAC32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1, 2]>, 94 InstrItinData<IIC_iMUL64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1]>, 95 InstrItinData<IIC_iMAC64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1, 2]>, 96 97 // Integer load pipeline 98 // 99 // Immediate offset 100 InstrItinData<IIC_iLoad_i , [InstrStage<1, [V6_Pipe]>], [4, 1]>, 101 InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [V6_Pipe]>], [4, 1]>, 102 InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [V6_Pipe]>], [4, 1]>, 103 // 104 // Register offset 105 InstrItinData<IIC_iLoad_r , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 106 InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 107 InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 108 // 109 // Scaled register offset, issues over 2 cycles 110 InstrItinData<IIC_iLoad_si , [InstrStage<2, [V6_Pipe]>], [5, 2, 1]>, 111 InstrItinData<IIC_iLoad_bh_si, [InstrStage<2, [V6_Pipe]>], [5, 2, 1]>, 112 // 113 // Immediate offset with update 114 InstrItinData<IIC_iLoad_iu , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>, 115 InstrItinData<IIC_iLoad_bh_iu, [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>, 116 // 117 // Register offset with update 118 InstrItinData<IIC_iLoad_ru , [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>, 119 InstrItinData<IIC_iLoad_bh_ru, [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>, 120 InstrItinData<IIC_iLoad_d_ru , [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>, 121 // 122 // Scaled register offset with update, issues over 2 cycles 123 InstrItinData<IIC_iLoad_siu, [InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>, 124 InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>, 125 126 // 127 // Load multiple, def is the 5th operand. 128 InstrItinData<IIC_iLoad_m , [InstrStage<3, [V6_Pipe]>], [1, 1, 1, 1, 4]>, 129 // 130 // Load multiple + update, defs are the 1st and 5th operands. 131 InstrItinData<IIC_iLoad_mu , [InstrStage<3, [V6_Pipe]>], [2, 1, 1, 1, 4]>, 132 // 133 // Load multiple plus branch 134 InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [V6_Pipe]>, 135 InstrStage<1, [V6_Pipe]>], [1, 2, 1, 1, 4]>, 136 137 // 138 // iLoadi + iALUr for t2LDRpci_pic. 139 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>, 140 InstrStage<1, [V6_Pipe]>], [3, 1]>, 141 142 // 143 // Pop, def is the 3rd operand. 144 InstrItinData<IIC_iPop , [InstrStage<3, [V6_Pipe]>], [1, 1, 4]>, 145 // 146 // Pop + branch, def is the 3rd operand. 147 InstrItinData<IIC_iPop_Br, [InstrStage<3, [V6_Pipe]>, 148 InstrStage<1, [V6_Pipe]>], [1, 2, 4]>, 149 150 // Integer store pipeline 151 // 152 // Immediate offset 153 InstrItinData<IIC_iStore_i , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 154 InstrItinData<IIC_iStore_bh_i, [InstrStage<1, [V6_Pipe]>], [2, 1]>, 155 InstrItinData<IIC_iStore_d_i , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 156 // 157 // Register offset 158 InstrItinData<IIC_iStore_r , [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>, 159 InstrItinData<IIC_iStore_bh_r, [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>, 160 InstrItinData<IIC_iStore_d_r , [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>, 161 // 162 // Scaled register offset, issues over 2 cycles 163 InstrItinData<IIC_iStore_si , [InstrStage<2, [V6_Pipe]>], [2, 2, 1]>, 164 InstrItinData<IIC_iStore_bh_si, [InstrStage<2, [V6_Pipe]>], [2, 2, 1]>, 165 // 166 // Immediate offset with update 167 InstrItinData<IIC_iStore_iu , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 168 InstrItinData<IIC_iStore_bh_iu, [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 169 // 170 // Register offset with update 171 InstrItinData<IIC_iStore_ru, [InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>, 172 InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>, 173 InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>, 174 // 175 // Scaled register offset with update, issues over 2 cycles 176 InstrItinData<IIC_iStore_siu, [InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>, 177 InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>, 178 // 179 // Store multiple 180 InstrItinData<IIC_iStore_m , [InstrStage<3, [V6_Pipe]>]>, 181 // 182 // Store multiple + update 183 InstrItinData<IIC_iStore_mu , [InstrStage<3, [V6_Pipe]>], [2]>, 184 185 // Branch 186 // 187 // no delay slots, so the latency of a branch is unimportant 188 InstrItinData<IIC_Br , [InstrStage<1, [V6_Pipe]>]>, 189 190 // VFP 191 // Issue through integer pipeline, and execute in NEON unit. We assume 192 // RunFast mode so that NFP pipeline is used for single-precision when 193 // possible. 194 // 195 // FP Special Register to Integer Register File Move 196 InstrItinData<IIC_fpSTAT , [InstrStage<1, [V6_Pipe]>], [3]>, 197 // 198 // Single-precision FP Unary 199 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 200 // 201 // Double-precision FP Unary 202 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 203 // 204 // Single-precision FP Compare 205 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 206 // 207 // Double-precision FP Compare 208 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 209 // 210 // Single to Double FP Convert 211 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 212 // 213 // Double to Single FP Convert 214 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 215 // 216 // Single-Precision FP to Integer Convert 217 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 218 // 219 // Double-Precision FP to Integer Convert 220 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 221 // 222 // Integer to Single-Precision FP Convert 223 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 224 // 225 // Integer to Double-Precision FP Convert 226 InstrItinData<IIC_fpCVTID , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 227 // 228 // Single-precision FP ALU 229 InstrItinData<IIC_fpALU32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 230 // 231 // Double-precision FP ALU 232 InstrItinData<IIC_fpALU64 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 233 // 234 // Single-precision FP Multiply 235 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 236 // 237 // Double-precision FP Multiply 238 InstrItinData<IIC_fpMUL64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2]>, 239 // 240 // Single-precision FP MAC 241 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2, 2]>, 242 // 243 // Double-precision FP MAC 244 InstrItinData<IIC_fpMAC64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>, 245 // 246 // Single-precision Fused FP MAC 247 InstrItinData<IIC_fpFMAC32, [InstrStage<1, [V6_Pipe]>], [9, 2, 2, 2]>, 248 // 249 // Double-precision Fused FP MAC 250 InstrItinData<IIC_fpFMAC64, [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>, 251 // 252 // Single-precision FP DIV 253 InstrItinData<IIC_fpDIV32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>, 254 // 255 // Double-precision FP DIV 256 InstrItinData<IIC_fpDIV64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>, 257 // 258 // Single-precision FP SQRT 259 InstrItinData<IIC_fpSQRT32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>, 260 // 261 // Double-precision FP SQRT 262 InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>, 263 // 264 // Integer to Single-precision Move 265 InstrItinData<IIC_fpMOVIS, [InstrStage<1, [V6_Pipe]>], [10, 1]>, 266 // 267 // Integer to Double-precision Move 268 InstrItinData<IIC_fpMOVID, [InstrStage<1, [V6_Pipe]>], [10, 1, 1]>, 269 // 270 // Single-precision to Integer Move 271 InstrItinData<IIC_fpMOVSI, [InstrStage<1, [V6_Pipe]>], [10, 1]>, 272 // 273 // Double-precision to Integer Move 274 InstrItinData<IIC_fpMOVDI, [InstrStage<1, [V6_Pipe]>], [10, 10, 1]>, 275 // 276 // Single-precision FP Load 277 InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>, 278 // 279 // Double-precision FP Load 280 InstrItinData<IIC_fpLoad64 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>, 281 // 282 // FP Load Multiple 283 InstrItinData<IIC_fpLoad_m , [InstrStage<3, [V6_Pipe]>], [2, 1, 1, 5]>, 284 // 285 // FP Load Multiple + update 286 InstrItinData<IIC_fpLoad_mu, [InstrStage<3, [V6_Pipe]>], [3, 2, 1, 1, 5]>, 287 // 288 // Single-precision FP Store 289 InstrItinData<IIC_fpStore32 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 290 // 291 // Double-precision FP Store 292 // use FU_Issue to enforce the 1 load/store per cycle limit 293 InstrItinData<IIC_fpStore64 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 294 // 295 // FP Store Multiple 296 InstrItinData<IIC_fpStore_m, [InstrStage<3, [V6_Pipe]>], [2, 2, 2, 2]>, 297 // 298 // FP Store Multiple + update 299 InstrItinData<IIC_fpStore_mu,[InstrStage<3, [V6_Pipe]>], [3, 2, 2, 2, 2]> 300]>; 301