ARMSubtarget.h revision 929bdb23794b615dc6b0cc59db21f0450c3ce33b 
1//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "MCTargetDesc/ARMMCTargetDesc.h"
18#include "llvm/ADT/Triple.h"
19#include "llvm/MC/MCInstrItineraries.h"
20#include "llvm/Target/TargetSubtargetInfo.h"
21#include <string>
22
23#define GET_SUBTARGETINFO_HEADER
24#include "ARMGenSubtargetInfo.inc"
25
26namespace llvm {
27class GlobalValue;
28class StringRef;
29class TargetOptions;
30
31class ARMSubtarget : public ARMGenSubtargetInfo {
32protected:
33  enum ARMProcFamilyEnum {
34    Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift, CortexA53, CortexA57
35  };
36  enum ARMProcClassEnum {
37    None, AClass, RClass, MClass
38  };
39
40  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
41  ARMProcFamilyEnum ARMProcFamily;
42
43  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
44  ARMProcClassEnum ARMProcClass;
45
46  /// HasV4TOps, HasV5TOps, HasV5TEOps,
47  /// HasV6Ops, HasV6MOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
48  /// Specify whether target support specific ARM ISA variants.
49  bool HasV4TOps;
50  bool HasV5TOps;
51  bool HasV5TEOps;
52  bool HasV6Ops;
53  bool HasV6MOps;
54  bool HasV6T2Ops;
55  bool HasV7Ops;
56  bool HasV8Ops;
57
58  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
59  /// floating point ISAs are supported.
60  bool HasVFPv2;
61  bool HasVFPv3;
62  bool HasVFPv4;
63  bool HasFPARMv8;
64  bool HasNEON;
65
66  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
67  /// specified. Use the method useNEONForSinglePrecisionFP() to
68  /// determine if NEON should actually be used.
69  bool UseNEONForSinglePrecisionFP;
70
71  /// UseMulOps - True if non-microcoded fused integer multiply-add and
72  /// multiply-subtract instructions should be used.
73  bool UseMulOps;
74
75  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
76  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
77  bool SlowFPVMLx;
78
79  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
80  /// forwarding to allow mul + mla being issued back to back.
81  bool HasVMLxForwarding;
82
83  /// SlowFPBrcc - True if floating point compare + branch is slow.
84  bool SlowFPBrcc;
85
86  /// InThumbMode - True if compiling for Thumb, false for ARM.
87  bool InThumbMode;
88
89  /// HasThumb2 - True if Thumb2 instructions are supported.
90  bool HasThumb2;
91
92  /// NoARM - True if subtarget does not support ARM mode execution.
93  bool NoARM;
94
95  /// PostRAScheduler - True if using post-register-allocation scheduler.
96  bool PostRAScheduler;
97
98  /// IsR9Reserved - True if R9 is a not available as general purpose register.
99  bool IsR9Reserved;
100
101  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
102  /// imms (including global addresses).
103  bool UseMovt;
104
105  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
106  /// must be able to synthesize call stubs for interworking between ARM and
107  /// Thumb.
108  bool SupportsTailCall;
109
110  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
111  /// only so far)
112  bool HasFP16;
113
114  /// HasD16 - True if subtarget is limited to 16 double precision
115  /// FP registers for VFPv3.
116  bool HasD16;
117
118  /// HasHardwareDivide - True if subtarget supports [su]div
119  bool HasHardwareDivide;
120
121  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
122  bool HasHardwareDivideInARM;
123
124  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
125  /// instructions.
126  bool HasT2ExtractPack;
127
128  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
129  /// instructions.
130  bool HasDataBarrier;
131
132  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
133  /// over 16-bit ones.
134  bool Pref32BitThumb;
135
136  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
137  /// that partially update CPSR and add false dependency on the previous
138  /// CPSR setting instruction.
139  bool AvoidCPSRPartialUpdate;
140
141  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
142  /// movs with shifter operand (i.e. asr, lsl, lsr).
143  bool AvoidMOVsShifterOperand;
144
145  /// HasRAS - Some processors perform return stack prediction. CodeGen should
146  /// avoid issue "normal" call instructions to callees which do not return.
147  bool HasRAS;
148
149  /// HasMPExtension - True if the subtarget supports Multiprocessing
150  /// extension (ARMv7 only).
151  bool HasMPExtension;
152
153  /// HasVirtualization - True if the subtarget supports the Virtualization
154  /// extension.
155  bool HasVirtualization;
156
157  /// FPOnlySP - If true, the floating point unit only supports single
158  /// precision.
159  bool FPOnlySP;
160
161  /// If true, the processor supports the Performance Monitor Extensions. These
162  /// include a generic cycle-counter as well as more fine-grained (often
163  /// implementation-specific) events.
164  bool HasPerfMon;
165
166  /// HasTrustZone - if true, processor supports TrustZone security extensions
167  bool HasTrustZone;
168
169  /// HasCrypto - if true, processor supports Cryptography extensions
170  bool HasCrypto;
171
172  /// HasCRC - if true, processor supports CRC instructions
173  bool HasCRC;
174
175  /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
176  /// accesses for some types.  For details, see
177  /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
178  bool AllowsUnalignedMem;
179
180  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
181  ///  blocks to conform to ARMv8 rule.
182  bool RestrictIT;
183
184  /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
185  /// and such) instructions in Thumb2 code.
186  bool Thumb2DSP;
187
188  /// NaCl TRAP instruction is generated instead of the regular TRAP.
189  bool UseNaClTrap;
190
191  /// Target machine allowed unsafe FP math (such as use of NEON fp)
192  bool UnsafeFPMath;
193
194  /// stackAlignment - The minimum alignment known to hold of the stack frame on
195  /// entry to the function and which must be maintained by every function.
196  unsigned stackAlignment;
197
198  /// CPUString - String name of used CPU.
199  std::string CPUString;
200
201  /// TargetTriple - What processor and OS we're targeting.
202  Triple TargetTriple;
203
204  /// SchedModel - Processor specific instruction costs.
205  const MCSchedModel *SchedModel;
206
207  /// Selected instruction itineraries (one entry per itinerary class.)
208  InstrItineraryData InstrItins;
209
210  /// Options passed via command line that could influence the target
211  const TargetOptions &Options;
212
213 public:
214  enum {
215    ARM_ABI_APCS,
216    ARM_ABI_AAPCS // ARM EABI
217  } TargetABI;
218
219  /// This constructor initializes the data members to match that
220  /// of the specified triple.
221  ///
222  ARMSubtarget(const std::string &TT, const std::string &CPU,
223               const std::string &FS, const TargetOptions &Options);
224
225  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
226  /// that still makes it profitable to inline the call.
227  unsigned getMaxInlineSizeThreshold() const {
228    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
229    // Change this once Thumb1 ldmia / stmia support is added.
230    return isThumb1Only() ? 0 : 64;
231  }
232  /// ParseSubtargetFeatures - Parses features string setting specified
233  /// subtarget options.  Definition of function is auto generated by tblgen.
234  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
235
236  /// \brief Reset the features for the ARM target.
237  virtual void resetSubtargetFeatures(const MachineFunction *MF);
238private:
239  void initializeEnvironment();
240  void resetSubtargetFeatures(StringRef CPU, StringRef FS);
241public:
242  void computeIssueWidth();
243
244  bool hasV4TOps()  const { return HasV4TOps;  }
245  bool hasV5TOps()  const { return HasV5TOps;  }
246  bool hasV5TEOps() const { return HasV5TEOps; }
247  bool hasV6Ops()   const { return HasV6Ops;   }
248  bool hasV6MOps()  const { return HasV6MOps;  }
249  bool hasV6T2Ops() const { return HasV6T2Ops; }
250  bool hasV7Ops()   const { return HasV7Ops;  }
251  bool hasV8Ops()   const { return HasV8Ops;  }
252
253  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
254  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
255  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
256  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
257  bool isSwift()    const { return ARMProcFamily == Swift; }
258  bool isCortexM3() const { return CPUString == "cortex-m3"; }
259  bool isLikeA9() const { return isCortexA9() || isCortexA15(); }
260  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
261
262  bool hasARMOps() const { return !NoARM; }
263
264  bool hasVFP2() const { return HasVFPv2; }
265  bool hasVFP3() const { return HasVFPv3; }
266  bool hasVFP4() const { return HasVFPv4; }
267  bool hasFPARMv8() const { return HasFPARMv8; }
268  bool hasNEON() const { return HasNEON;  }
269  bool hasCrypto() const { return HasCrypto; }
270  bool hasCRC() const { return HasCRC; }
271  bool hasVirtualization() const { return HasVirtualization; }
272  bool useNEONForSinglePrecisionFP() const {
273    return hasNEON() && UseNEONForSinglePrecisionFP; }
274
275  bool hasDivide() const { return HasHardwareDivide; }
276  bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
277  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
278  bool hasDataBarrier() const { return HasDataBarrier; }
279  bool hasAnyDataBarrier() const {
280    return HasDataBarrier || (hasV6Ops() && !isThumb());
281  }
282  bool useMulOps() const { return UseMulOps; }
283  bool useFPVMLx() const { return !SlowFPVMLx; }
284  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
285  bool isFPBrccSlow() const { return SlowFPBrcc; }
286  bool isFPOnlySP() const { return FPOnlySP; }
287  bool hasPerfMon() const { return HasPerfMon; }
288  bool hasTrustZone() const { return HasTrustZone; }
289  bool prefers32BitThumb() const { return Pref32BitThumb; }
290  bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
291  bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
292  bool hasRAS() const { return HasRAS; }
293  bool hasMPExtension() const { return HasMPExtension; }
294  bool hasThumb2DSP() const { return Thumb2DSP; }
295  bool useNaClTrap() const { return UseNaClTrap; }
296
297  bool hasFP16() const { return HasFP16; }
298  bool hasD16() const { return HasD16; }
299
300  const Triple &getTargetTriple() const { return TargetTriple; }
301
302  bool isTargetIOS() const { return TargetTriple.isiOS(); }
303  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
304  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
305  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
306  bool isTargetELF() const { return !isTargetDarwin(); }
307  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
308  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
309  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
310  // even for GNUEABI, so we can make a distinction here and still conform to
311  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
312  bool isTargetAEABI() const {
313    return TargetTriple.getEnvironment() == Triple::EABI;
314  }
315
316  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
317  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
318
319  bool isThumb() const { return InThumbMode; }
320  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
321  bool isThumb2() const { return InThumbMode && HasThumb2; }
322  bool hasThumb2() const { return HasThumb2; }
323  bool isMClass() const { return ARMProcClass == MClass; }
324  bool isRClass() const { return ARMProcClass == RClass; }
325  bool isAClass() const { return ARMProcClass == AClass; }
326
327  bool isR9Reserved() const { return IsR9Reserved; }
328
329  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
330  bool supportsTailCall() const { return SupportsTailCall; }
331
332  bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
333
334  bool restrictIT() const { return RestrictIT; }
335
336  const std::string & getCPUString() const { return CPUString; }
337
338  unsigned getMispredictionPenalty() const;
339
340  /// This function returns true if the target has sincos() routine in its
341  /// compiler runtime or math libraries.
342  bool hasSinCos() const;
343
344  /// enablePostRAScheduler - True at 'More' optimization.
345  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
346                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
347                             RegClassVector& CriticalPathRCs) const;
348
349  /// getInstrItins - Return the instruction itineraies based on subtarget
350  /// selection.
351  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
352
353  /// getStackAlignment - Returns the minimum alignment known to hold of the
354  /// stack frame on entry to the function and which must be maintained by every
355  /// function for this subtarget.
356  unsigned getStackAlignment() const { return stackAlignment; }
357
358  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
359  /// symbol.
360  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
361};
362} // End llvm namespace
363
364#endif  // ARMSUBTARGET_H
365