ARMSubtarget.h revision eb1641d54a7eda7717304bc4d55d059208d8ebed 
1//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "MCTargetDesc/ARMMCTargetDesc.h"
18#include "llvm/Target/TargetSubtargetInfo.h"
19#include "llvm/MC/MCInstrItineraries.h"
20#include "llvm/ADT/Triple.h"
21#include <string>
22
23#define GET_SUBTARGETINFO_HEADER
24#include "ARMGenSubtargetInfo.inc"
25
26namespace llvm {
27class GlobalValue;
28class StringRef;
29
30class ARMSubtarget : public ARMGenSubtargetInfo {
31protected:
32  enum ARMProcFamilyEnum {
33    Others, CortexA8, CortexA9, CortexA15, Swift
34  };
35
36  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
37  ARMProcFamilyEnum ARMProcFamily;
38
39  /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
40  /// Specify whether target support specific ARM ISA variants.
41  bool HasV4TOps;
42  bool HasV5TOps;
43  bool HasV5TEOps;
44  bool HasV6Ops;
45  bool HasV6T2Ops;
46  bool HasV7Ops;
47
48  /// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON - Specify what
49  /// floating point ISAs are supported.
50  bool HasVFPv2;
51  bool HasVFPv3;
52  bool HasVFPv4;
53  bool HasNEON;
54
55  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
56  /// specified. Use the method useNEONForSinglePrecisionFP() to
57  /// determine if NEON should actually be used.
58  bool UseNEONForSinglePrecisionFP;
59
60  /// UseMulOps - True if non-microcoded fused integer multiply-add and
61  /// multiply-subtract instructions should be used.
62  bool UseMulOps;
63
64  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
65  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
66  bool SlowFPVMLx;
67
68  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
69  /// forwarding to allow mul + mla being issued back to back.
70  bool HasVMLxForwarding;
71
72  /// SlowFPBrcc - True if floating point compare + branch is slow.
73  bool SlowFPBrcc;
74
75  /// InThumbMode - True if compiling for Thumb, false for ARM.
76  bool InThumbMode;
77
78  /// HasThumb2 - True if Thumb2 instructions are supported.
79  bool HasThumb2;
80
81  /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
82  /// v6m, v7m for example.
83  bool IsMClass;
84
85  /// NoARM - True if subtarget does not support ARM mode execution.
86  bool NoARM;
87
88  /// PostRAScheduler - True if using post-register-allocation scheduler.
89  bool PostRAScheduler;
90
91  /// IsR9Reserved - True if R9 is a not available as general purpose register.
92  bool IsR9Reserved;
93
94  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
95  /// imms (including global addresses).
96  bool UseMovt;
97
98  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
99  /// must be able to synthesize call stubs for interworking between ARM and
100  /// Thumb.
101  bool SupportsTailCall;
102
103  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
104  /// only so far)
105  bool HasFP16;
106
107  /// HasD16 - True if subtarget is limited to 16 double precision
108  /// FP registers for VFPv3.
109  bool HasD16;
110
111  /// HasHardwareDivide - True if subtarget supports [su]div
112  bool HasHardwareDivide;
113
114  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
115  bool HasHardwareDivideInARM;
116
117  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
118  /// instructions.
119  bool HasT2ExtractPack;
120
121  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
122  /// instructions.
123  bool HasDataBarrier;
124
125  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
126  /// over 16-bit ones.
127  bool Pref32BitThumb;
128
129  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
130  /// that partially update CPSR and add false dependency on the previous
131  /// CPSR setting instruction.
132  bool AvoidCPSRPartialUpdate;
133
134  /// HasRAS - Some processors perform return stack prediction. CodeGen should
135  /// avoid issue "normal" call instructions to callees which do not return.
136  bool HasRAS;
137
138  /// HasMPExtension - True if the subtarget supports Multiprocessing
139  /// extension (ARMv7 only).
140  bool HasMPExtension;
141
142  /// FPOnlySP - If true, the floating point unit only supports single
143  /// precision.
144  bool FPOnlySP;
145
146  /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
147  /// accesses for some types.  For details, see
148  /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
149  bool AllowsUnalignedMem;
150
151  /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
152  /// and such) instructions in Thumb2 code.
153  bool Thumb2DSP;
154
155  /// stackAlignment - The minimum alignment known to hold of the stack frame on
156  /// entry to the function and which must be maintained by every function.
157  unsigned stackAlignment;
158
159  /// CPUString - String name of used CPU.
160  std::string CPUString;
161
162  /// TargetTriple - What processor and OS we're targeting.
163  Triple TargetTriple;
164
165  /// SchedModel - Processor specific instruction costs.
166  const MCSchedModel *SchedModel;
167
168  /// Selected instruction itineraries (one entry per itinerary class.)
169  InstrItineraryData InstrItins;
170
171 public:
172  enum {
173    isELF, isDarwin
174  } TargetType;
175
176  enum {
177    ARM_ABI_APCS,
178    ARM_ABI_AAPCS // ARM EABI
179  } TargetABI;
180
181  /// This constructor initializes the data members to match that
182  /// of the specified triple.
183  ///
184  ARMSubtarget(const std::string &TT, const std::string &CPU,
185               const std::string &FS);
186
187  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
188  /// that still makes it profitable to inline the call.
189  unsigned getMaxInlineSizeThreshold() const {
190    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
191    // Change this once Thumb1 ldmia / stmia support is added.
192    return isThumb1Only() ? 0 : 64;
193  }
194  /// ParseSubtargetFeatures - Parses features string setting specified
195  /// subtarget options.  Definition of function is auto generated by tblgen.
196  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
197
198  void computeIssueWidth();
199
200  bool hasV4TOps()  const { return HasV4TOps;  }
201  bool hasV5TOps()  const { return HasV5TOps;  }
202  bool hasV5TEOps() const { return HasV5TEOps; }
203  bool hasV6Ops()   const { return HasV6Ops;   }
204  bool hasV6T2Ops() const { return HasV6T2Ops; }
205  bool hasV7Ops()   const { return HasV7Ops;  }
206
207  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
208  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
209  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
210  bool isSwift()    const { return ARMProcFamily == Swift; }
211  bool isCortexM3() const { return CPUString == "cortex-m3"; }
212  bool isLikeA9() const { return isCortexA9() || isCortexA15(); }
213
214  bool hasARMOps() const { return !NoARM; }
215
216  bool hasVFP2() const { return HasVFPv2; }
217  bool hasVFP3() const { return HasVFPv3; }
218  bool hasVFP4() const { return HasVFPv4; }
219  bool hasNEON() const { return HasNEON;  }
220  bool useNEONForSinglePrecisionFP() const {
221    return hasNEON() && UseNEONForSinglePrecisionFP; }
222
223  bool hasDivide() const { return HasHardwareDivide; }
224  bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
225  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
226  bool hasDataBarrier() const { return HasDataBarrier; }
227  bool useMulOps() const { return UseMulOps; }
228  bool useFPVMLx() const { return !SlowFPVMLx; }
229  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
230  bool isFPBrccSlow() const { return SlowFPBrcc; }
231  bool isFPOnlySP() const { return FPOnlySP; }
232  bool prefers32BitThumb() const { return Pref32BitThumb; }
233  bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
234  bool hasRAS() const { return HasRAS; }
235  bool hasMPExtension() const { return HasMPExtension; }
236  bool hasThumb2DSP() const { return Thumb2DSP; }
237
238  bool hasFP16() const { return HasFP16; }
239  bool hasD16() const { return HasD16; }
240
241  const Triple &getTargetTriple() const { return TargetTriple; }
242
243  bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
244  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
245  bool isTargetNaCl() const {
246    return TargetTriple.getOS() == Triple::NativeClient;
247  }
248  bool isTargetELF() const { return !isTargetDarwin(); }
249
250  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
251  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
252
253  bool isThumb() const { return InThumbMode; }
254  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
255  bool isThumb2() const { return InThumbMode && HasThumb2; }
256  bool hasThumb2() const { return HasThumb2; }
257  bool isMClass() const { return IsMClass; }
258  bool isARClass() const { return !IsMClass; }
259
260  bool isR9Reserved() const { return IsR9Reserved; }
261
262  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
263  bool supportsTailCall() const { return SupportsTailCall; }
264
265  bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
266
267  const std::string & getCPUString() const { return CPUString; }
268
269  unsigned getMispredictionPenalty() const;
270
271  /// enablePostRAScheduler - True at 'More' optimization.
272  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
273                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
274                             RegClassVector& CriticalPathRCs) const;
275
276  /// getInstrItins - Return the instruction itineraies based on subtarget
277  /// selection.
278  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
279
280  /// getStackAlignment - Returns the minimum alignment known to hold of the
281  /// stack frame on entry to the function and which must be maintained by every
282  /// function for this subtarget.
283  unsigned getStackAlignment() const { return stackAlignment; }
284
285  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
286  /// symbol.
287  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
288};
289} // End llvm namespace
290
291#endif  // ARMSUBTARGET_H
292