ARMTargetMachine.cpp revision 270483466124fe1e19d5439e958fef63cebd43cd 
1//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARMTargetMachine.h"
14#include "ARMFrameLowering.h"
15#include "ARM.h"
16#include "llvm/PassManager.h"
17#include "llvm/CodeGen/Passes.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Support/FormattedStream.h"
21#include "llvm/Support/TargetRegistry.h"
22#include "llvm/Target/TargetOptions.h"
23#include "llvm/Transforms/Scalar.h"
24using namespace llvm;
25
26static cl::opt<bool>
27EnableGlobalMerge("global-merge", cl::Hidden,
28                  cl::desc("Enable global merge pass"),
29                  cl::init(true));
30
31extern "C" void LLVMInitializeARMTarget() {
32  // Register the target.
33  RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
34  RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
35}
36
37
38/// TargetMachine ctor - Create an ARM architecture model.
39///
40ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
41                                           StringRef CPU, StringRef FS,
42                                           const TargetOptions &Options,
43                                           Reloc::Model RM, CodeModel::Model CM,
44                                           CodeGenOpt::Level OL)
45  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
46    Subtarget(TT, CPU, FS),
47    JITInfo(),
48    InstrItins(Subtarget.getInstrItineraryData()) {
49  // Default to soft float ABI
50  if (Options.FloatABIType == FloatABI::Default)
51    this->Options.FloatABIType = FloatABI::Soft;
52}
53
54void ARMTargetMachine::anchor() { }
55
56ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
57                                   StringRef CPU, StringRef FS,
58                                   const TargetOptions &Options,
59                                   Reloc::Model RM, CodeModel::Model CM,
60                                   CodeGenOpt::Level OL)
61  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
62    InstrInfo(Subtarget),
63    DL(Subtarget.isAPCS_ABI() ?
64               std::string("e-p:32:32-f64:32:64-i64:32:64-"
65                           "v128:32:128-v64:32:64-n32-S32") :
66               Subtarget.isAAPCS_ABI() ?
67               std::string("e-p:32:32-f64:64:64-i64:64:64-"
68                           "v128:64:128-v64:64:64-n32-S64") :
69               std::string("e-p:32:32-f64:64:64-i64:64:64-"
70                           "v128:64:128-v64:64:64-n32-S32")),
71    ELFWriterInfo(*this),
72    TLInfo(*this),
73    TSInfo(*this),
74    FrameLowering(Subtarget),
75    STTI(&TLInfo), VTTI(&TLInfo) {
76  if (!Subtarget.hasARMOps())
77    report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
78                       "support ARM mode execution!");
79}
80
81void ThumbTargetMachine::anchor() { }
82
83ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
84                                       StringRef CPU, StringRef FS,
85                                       const TargetOptions &Options,
86                                       Reloc::Model RM, CodeModel::Model CM,
87                                       CodeGenOpt::Level OL)
88  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
89    InstrInfo(Subtarget.hasThumb2()
90              ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
91              : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
92    DL(Subtarget.isAPCS_ABI() ?
93               std::string("e-p:32:32-f64:32:64-i64:32:64-"
94                           "i16:16:32-i8:8:32-i1:8:32-"
95                           "v128:32:128-v64:32:64-a:0:32-n32-S32") :
96               Subtarget.isAAPCS_ABI() ?
97               std::string("e-p:32:32-f64:64:64-i64:64:64-"
98                           "i16:16:32-i8:8:32-i1:8:32-"
99                           "v128:64:128-v64:64:64-a:0:32-n32-S64") :
100               std::string("e-p:32:32-f64:64:64-i64:64:64-"
101                           "i16:16:32-i8:8:32-i1:8:32-"
102                           "v128:64:128-v64:64:64-a:0:32-n32-S32")),
103    ELFWriterInfo(*this),
104    TLInfo(*this),
105    TSInfo(*this),
106    FrameLowering(Subtarget.hasThumb2()
107              ? new ARMFrameLowering(Subtarget)
108              : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)),
109    STTI(&TLInfo), VTTI(&TLInfo) {
110}
111
112namespace {
113/// ARM Code Generator Pass Configuration Options.
114class ARMPassConfig : public TargetPassConfig {
115public:
116  ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
117    : TargetPassConfig(TM, PM) {}
118
119  ARMBaseTargetMachine &getARMTargetMachine() const {
120    return getTM<ARMBaseTargetMachine>();
121  }
122
123  const ARMSubtarget &getARMSubtarget() const {
124    return *getARMTargetMachine().getSubtargetImpl();
125  }
126
127  virtual bool addPreISel();
128  virtual bool addInstSelector();
129  virtual bool addPreRegAlloc();
130  virtual bool addPreSched2();
131  virtual bool addPreEmitPass();
132};
133} // namespace
134
135TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
136  return new ARMPassConfig(this, PM);
137}
138
139bool ARMPassConfig::addPreISel() {
140  if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
141    addPass(createGlobalMergePass(TM->getTargetLowering()));
142
143  return false;
144}
145
146bool ARMPassConfig::addInstSelector() {
147  addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
148
149  const ARMSubtarget *Subtarget = &getARMSubtarget();
150  if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
151      TM->Options.EnableFastISel)
152    addPass(createARMGlobalBaseRegPass());
153  return false;
154}
155
156bool ARMPassConfig::addPreRegAlloc() {
157  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
158  if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
159    addPass(createARMLoadStoreOptimizationPass(true));
160  if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isLikeA9())
161    addPass(createMLxExpansionPass());
162  return true;
163}
164
165bool ARMPassConfig::addPreSched2() {
166  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
167  if (getOptLevel() != CodeGenOpt::None) {
168    if (!getARMSubtarget().isThumb1Only()) {
169      addPass(createARMLoadStoreOptimizationPass());
170      printAndVerify("After ARM load / store optimizer");
171    }
172    if (getARMSubtarget().hasNEON())
173      addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
174  }
175
176  // Expand some pseudo instructions into multiple instructions to allow
177  // proper scheduling.
178  addPass(createARMExpandPseudoPass());
179
180  if (getOptLevel() != CodeGenOpt::None) {
181    if (!getARMSubtarget().isThumb1Only())
182      addPass(&IfConverterID);
183  }
184  if (getARMSubtarget().isThumb2())
185    addPass(createThumb2ITBlockPass());
186
187  return true;
188}
189
190bool ARMPassConfig::addPreEmitPass() {
191  if (getARMSubtarget().isThumb2()) {
192    if (!getARMSubtarget().prefers32BitThumb())
193      addPass(createThumb2SizeReductionPass());
194
195    // Constant island pass work on unbundled instructions.
196    addPass(&UnpackMachineBundlesID);
197  }
198
199  addPass(createARMConstantIslandPass());
200
201  return true;
202}
203
204bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
205                                          JITCodeEmitter &JCE) {
206  // Machine code emitter pass for ARM.
207  PM.add(createARMJITCodeEmitterPass(*this, JCE));
208  return false;
209}
210