ARMTargetMachine.cpp revision df214fa51715896d0cd5a407e8e4c57454619fc2 
1//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARMTargetMachine.h"
14#include "ARMMCAsmInfo.h"
15#include "ARMFrameLowering.h"
16#include "ARM.h"
17#include "llvm/PassManager.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Support/FormattedStream.h"
21#include "llvm/Target/TargetOptions.h"
22#include "llvm/Target/TargetRegistry.h"
23using namespace llvm;
24
25static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
26  Triple TheTriple(TT);
27
28  if (TheTriple.isOSDarwin())
29    return new ARMMCAsmInfoDarwin();
30
31  return new ARMELFMCAsmInfo();
32}
33
34// This is duplicated code. Refactor this.
35static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
36                                    MCContext &Ctx, TargetAsmBackend &TAB,
37                                    raw_ostream &OS,
38                                    MCCodeEmitter *Emitter,
39                                    bool RelaxAll,
40                                    bool NoExecStack) {
41  Triple TheTriple(TT);
42
43  if (TheTriple.isOSDarwin())
44    return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
45
46  if (TheTriple.isOSWindows()) {
47    llvm_unreachable("ARM does not support Windows COFF format");
48    return NULL;
49  }
50
51  return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack);
52}
53
54extern "C" void LLVMInitializeARMTarget() {
55  // Register the target.
56  RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
57  RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
58
59  // Register the target asm info.
60  RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
61  RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
62
63  // Register the MC Code Emitter
64  TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
65  TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
66
67  // Register the asm backend.
68  TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend);
69  TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend);
70
71  // Register the object streamer.
72  TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer);
73  TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer);
74
75}
76
77/// TargetMachine ctor - Create an ARM architecture model.
78///
79ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
80                                           const std::string &TT,
81                                           const std::string &FS,
82                                           bool isThumb)
83  : LLVMTargetMachine(T, TT),
84    Subtarget(TT, FS, isThumb),
85    JITInfo(),
86    InstrItins(Subtarget.getInstrItineraryData()) {
87  DefRelocModel = getRelocationModel();
88
89  // Default to soft float ABI
90  if (FloatABIType == FloatABI::Default)
91    FloatABIType = FloatABI::Soft;
92}
93
94ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
95                                   const std::string &FS)
96  : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
97    DataLayout(Subtarget.isAPCS_ABI() ?
98               std::string("e-p:32:32-f64:32:64-i64:32:64-"
99                           "v128:32:128-v64:32:64-n32") :
100               std::string("e-p:32:32-f64:64:64-i64:64:64-"
101                           "v128:64:128-v64:64:64-n32")),
102    ELFWriterInfo(*this),
103    TLInfo(*this),
104    TSInfo(*this),
105    FrameLowering(Subtarget) {
106  if (!Subtarget.hasARMOps())
107    report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
108                       "support ARM mode execution!");
109}
110
111ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
112                                       const std::string &FS)
113  : ARMBaseTargetMachine(T, TT, FS, true),
114    InstrInfo(Subtarget.hasThumb2()
115              ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
116              : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
117    DataLayout(Subtarget.isAPCS_ABI() ?
118               std::string("e-p:32:32-f64:32:64-i64:32:64-"
119                           "i16:16:32-i8:8:32-i1:8:32-"
120                           "v128:32:128-v64:32:64-a:0:32-n32") :
121               std::string("e-p:32:32-f64:64:64-i64:64:64-"
122                           "i16:16:32-i8:8:32-i1:8:32-"
123                           "v128:64:128-v64:64:64-a:0:32-n32")),
124    ELFWriterInfo(*this),
125    TLInfo(*this),
126    TSInfo(*this),
127    FrameLowering(Subtarget.hasThumb2()
128              ? new ARMFrameLowering(Subtarget)
129              : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
130}
131
132// Pass Pipeline Configuration
133bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
134                                      CodeGenOpt::Level OptLevel) {
135  if (OptLevel != CodeGenOpt::None)
136    PM.add(createARMGlobalMergePass(getTargetLowering()));
137
138  return false;
139}
140
141bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
142                                           CodeGenOpt::Level OptLevel) {
143  PM.add(createARMISelDag(*this, OptLevel));
144  return false;
145}
146
147bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
148                                          CodeGenOpt::Level OptLevel) {
149  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
150  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
151    PM.add(createARMLoadStoreOptimizationPass(true));
152  if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
153    PM.add(createMLxExpansionPass());
154
155  return true;
156}
157
158bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
159                                        CodeGenOpt::Level OptLevel) {
160  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
161  if (OptLevel != CodeGenOpt::None) {
162    if (!Subtarget.isThumb1Only())
163      PM.add(createARMLoadStoreOptimizationPass());
164    if (Subtarget.hasNEON())
165      PM.add(createNEONMoveFixPass());
166  }
167
168  // Expand some pseudo instructions into multiple instructions to allow
169  // proper scheduling.
170  PM.add(createARMExpandPseudoPass());
171
172  if (OptLevel != CodeGenOpt::None) {
173    if (!Subtarget.isThumb1Only())
174      PM.add(createIfConverterPass());
175  }
176  if (Subtarget.isThumb2())
177    PM.add(createThumb2ITBlockPass());
178
179  return true;
180}
181
182bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
183                                          CodeGenOpt::Level OptLevel) {
184  if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
185    PM.add(createThumb2SizeReductionPass());
186
187  PM.add(createARMConstantIslandPass());
188  return true;
189}
190
191bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
192                                          CodeGenOpt::Level OptLevel,
193                                          JITCodeEmitter &JCE) {
194  // FIXME: Move this to TargetJITInfo!
195  if (DefRelocModel == Reloc::Default)
196    setRelocationModel(Reloc::Static);
197
198  // Machine code emitter pass for ARM.
199  PM.add(createARMJITCodeEmitterPass(*this, JCE));
200  return false;
201}
202