ARMTargetMachine.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetMachine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMTARGETMACHINE_H
15#define ARMTARGETMACHINE_H
16
17#include "ARMFrameLowering.h"
18#include "ARMISelLowering.h"
19#include "ARMInstrInfo.h"
20#include "ARMJITInfo.h"
21#include "ARMSelectionDAGInfo.h"
22#include "ARMSubtarget.h"
23#include "Thumb1FrameLowering.h"
24#include "Thumb1InstrInfo.h"
25#include "Thumb2InstrInfo.h"
26#include "llvm/ADT/OwningPtr.h"
27#include "llvm/IR/DataLayout.h"
28#include "llvm/MC/MCStreamer.h"
29#include "llvm/Target/TargetMachine.h"
30
31namespace llvm {
32
33class ARMBaseTargetMachine : public LLVMTargetMachine {
34protected:
35  ARMSubtarget        Subtarget;
36private:
37  ARMJITInfo          JITInfo;
38  InstrItineraryData  InstrItins;
39
40public:
41  ARMBaseTargetMachine(const Target &T, StringRef TT,
42                       StringRef CPU, StringRef FS,
43                       const TargetOptions &Options,
44                       Reloc::Model RM, CodeModel::Model CM,
45                       CodeGenOpt::Level OL,
46                       bool isLittle);
47
48  ARMJITInfo *getJITInfo() override { return &JITInfo; }
49  const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
50  const ARMTargetLowering *getTargetLowering() const override {
51    // Implemented by derived classes
52    llvm_unreachable("getTargetLowering not implemented");
53  }
54  const InstrItineraryData *getInstrItineraryData() const override {
55    return &InstrItins;
56  }
57
58  /// \brief Register ARM analysis passes with a pass manager.
59  void addAnalysisPasses(PassManagerBase &PM) override;
60
61  // Pass Pipeline Configuration
62  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
63
64  bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
65};
66
67/// ARMTargetMachine - ARM target machine.
68///
69class ARMTargetMachine : public ARMBaseTargetMachine {
70  virtual void anchor();
71  ARMInstrInfo        InstrInfo;
72  const DataLayout    DL;       // Calculates type size & alignment
73  ARMTargetLowering   TLInfo;
74  ARMSelectionDAGInfo TSInfo;
75  ARMFrameLowering    FrameLowering;
76 public:
77  ARMTargetMachine(const Target &T, StringRef TT,
78                   StringRef CPU, StringRef FS,
79                   const TargetOptions &Options,
80                   Reloc::Model RM, CodeModel::Model CM,
81                   CodeGenOpt::Level OL,
82                   bool isLittle);
83
84  const ARMRegisterInfo *getRegisterInfo() const override {
85    return &InstrInfo.getRegisterInfo();
86  }
87
88  const ARMTargetLowering *getTargetLowering() const override {
89    return &TLInfo;
90  }
91
92  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
93    return &TSInfo;
94  }
95  const ARMFrameLowering *getFrameLowering() const override {
96    return &FrameLowering;
97  }
98  const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
99  const DataLayout *getDataLayout() const override { return &DL; }
100};
101
102/// ARMLETargetMachine - ARM little endian target machine.
103///
104class ARMLETargetMachine : public ARMTargetMachine {
105  virtual void anchor();
106public:
107  ARMLETargetMachine(const Target &T, StringRef TT,
108                     StringRef CPU, StringRef FS, const TargetOptions &Options,
109                     Reloc::Model RM, CodeModel::Model CM,
110                     CodeGenOpt::Level OL);
111};
112
113/// ARMBETargetMachine - ARM big endian target machine.
114///
115class ARMBETargetMachine : public ARMTargetMachine {
116  virtual void anchor();
117public:
118  ARMBETargetMachine(const Target &T, StringRef TT,
119                     StringRef CPU, StringRef FS, const TargetOptions &Options,
120                     Reloc::Model RM, CodeModel::Model CM,
121                     CodeGenOpt::Level OL);
122};
123
124/// ThumbTargetMachine - Thumb target machine.
125/// Due to the way architectures are handled, this represents both
126///   Thumb-1 and Thumb-2.
127///
128class ThumbTargetMachine : public ARMBaseTargetMachine {
129  virtual void anchor();
130  // Either Thumb1InstrInfo or Thumb2InstrInfo.
131  OwningPtr<ARMBaseInstrInfo> InstrInfo;
132  const DataLayout    DL;   // Calculates type size & alignment
133  ARMTargetLowering   TLInfo;
134  ARMSelectionDAGInfo TSInfo;
135  // Either Thumb1FrameLowering or ARMFrameLowering.
136  OwningPtr<ARMFrameLowering> FrameLowering;
137public:
138  ThumbTargetMachine(const Target &T, StringRef TT,
139                     StringRef CPU, StringRef FS,
140                     const TargetOptions &Options,
141                     Reloc::Model RM, CodeModel::Model CM,
142                     CodeGenOpt::Level OL,
143                     bool isLittle);
144
145  /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
146  const ARMBaseRegisterInfo *getRegisterInfo() const override {
147    return &InstrInfo->getRegisterInfo();
148  }
149
150  const ARMTargetLowering *getTargetLowering() const override {
151    return &TLInfo;
152  }
153
154  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
155    return &TSInfo;
156  }
157
158  /// returns either Thumb1InstrInfo or Thumb2InstrInfo
159  const ARMBaseInstrInfo *getInstrInfo() const override {
160    return InstrInfo.get();
161  }
162  /// returns either Thumb1FrameLowering or ARMFrameLowering
163  const ARMFrameLowering *getFrameLowering() const override {
164    return FrameLowering.get();
165  }
166  const DataLayout *getDataLayout() const override { return &DL; }
167};
168
169/// ThumbLETargetMachine - Thumb little endian target machine.
170///
171class ThumbLETargetMachine : public ThumbTargetMachine {
172  virtual void anchor();
173public:
174  ThumbLETargetMachine(const Target &T, StringRef TT,
175                     StringRef CPU, StringRef FS, const TargetOptions &Options,
176                     Reloc::Model RM, CodeModel::Model CM,
177                     CodeGenOpt::Level OL);
178};
179
180/// ThumbBETargetMachine - Thumb big endian target machine.
181///
182class ThumbBETargetMachine : public ThumbTargetMachine {
183  virtual void anchor();
184public:
185  ThumbBETargetMachine(const Target &T, StringRef TT,
186                       StringRef CPU, StringRef FS, const TargetOptions &Options,
187                       Reloc::Model RM, CodeModel::Model CM,
188                       CodeGenOpt::Level OL);
189};
190
191} // end namespace llvm
192
193#endif
194