ARMTargetMachine.h revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 
1//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetMachine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMTARGETMACHINE_H
15#define ARMTARGETMACHINE_H
16
17#include "ARMInstrInfo.h"
18#include "ARMSubtarget.h"
19#include "llvm/IR/DataLayout.h"
20#include "llvm/Target/TargetMachine.h"
21
22namespace llvm {
23
24class ARMBaseTargetMachine : public LLVMTargetMachine {
25protected:
26  ARMSubtarget        Subtarget;
27public:
28  ARMBaseTargetMachine(const Target &T, StringRef TT,
29                       StringRef CPU, StringRef FS,
30                       const TargetOptions &Options,
31                       Reloc::Model RM, CodeModel::Model CM,
32                       CodeGenOpt::Level OL,
33                       bool isLittle);
34
35  const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
36  const ARMBaseRegisterInfo *getRegisterInfo() const override {
37    return getSubtargetImpl()->getRegisterInfo();
38  }
39  const ARMTargetLowering *getTargetLowering() const override {
40    return getSubtargetImpl()->getTargetLowering();
41  }
42  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
43    return getSubtargetImpl()->getSelectionDAGInfo();
44  }
45  const ARMBaseInstrInfo *getInstrInfo() const override {
46    return getSubtargetImpl()->getInstrInfo();
47  }
48  const ARMFrameLowering *getFrameLowering() const override {
49    return getSubtargetImpl()->getFrameLowering();
50  }
51  const InstrItineraryData *getInstrItineraryData() const override {
52    return &getSubtargetImpl()->getInstrItineraryData();
53  }
54  const DataLayout *getDataLayout() const override {
55    return getSubtargetImpl()->getDataLayout();
56  }
57  ARMJITInfo *getJITInfo() override { return Subtarget.getJITInfo(); }
58
59  /// \brief Register ARM analysis passes with a pass manager.
60  void addAnalysisPasses(PassManagerBase &PM) override;
61
62  // Pass Pipeline Configuration
63  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
64
65  bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
66};
67
68/// ARMTargetMachine - ARM target machine.
69///
70class ARMTargetMachine : public ARMBaseTargetMachine {
71  virtual void anchor();
72 public:
73   ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
74                    const TargetOptions &Options, Reloc::Model RM,
75                    CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
76};
77
78/// ARMLETargetMachine - ARM little endian target machine.
79///
80class ARMLETargetMachine : public ARMTargetMachine {
81  void anchor() override;
82public:
83  ARMLETargetMachine(const Target &T, StringRef TT,
84                     StringRef CPU, StringRef FS, const TargetOptions &Options,
85                     Reloc::Model RM, CodeModel::Model CM,
86                     CodeGenOpt::Level OL);
87};
88
89/// ARMBETargetMachine - ARM big endian target machine.
90///
91class ARMBETargetMachine : public ARMTargetMachine {
92  void anchor() override;
93public:
94  ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
95                     const TargetOptions &Options, Reloc::Model RM,
96                     CodeModel::Model CM, CodeGenOpt::Level OL);
97};
98
99/// ThumbTargetMachine - Thumb target machine.
100/// Due to the way architectures are handled, this represents both
101///   Thumb-1 and Thumb-2.
102///
103class ThumbTargetMachine : public ARMBaseTargetMachine {
104  virtual void anchor();
105public:
106  ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
107                     const TargetOptions &Options, Reloc::Model RM,
108                     CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
109};
110
111/// ThumbLETargetMachine - Thumb little endian target machine.
112///
113class ThumbLETargetMachine : public ThumbTargetMachine {
114  void anchor() override;
115public:
116  ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
117                       StringRef FS, const TargetOptions &Options,
118                       Reloc::Model RM, CodeModel::Model CM,
119                       CodeGenOpt::Level OL);
120};
121
122/// ThumbBETargetMachine - Thumb big endian target machine.
123///
124class ThumbBETargetMachine : public ThumbTargetMachine {
125  void anchor() override;
126public:
127  ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
128                       StringRef FS, const TargetOptions &Options,
129                       Reloc::Model RM, CodeModel::Model CM,
130                       CodeGenOpt::Level OL);
131};
132
133} // end namespace llvm
134
135#endif
136