ARMTargetMachine.h revision dbb121b1f19bf77e0bef8725d5ee42c1b8761caf 
1//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetMachine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMTARGETMACHINE_H
15#define ARMTARGETMACHINE_H
16
17#include "llvm/Target/TargetMachine.h"
18#include "llvm/Target/TargetData.h"
19#include "ARMInstrInfo.h"
20#include "ARMFrameInfo.h"
21#include "ARMJITInfo.h"
22#include "ARMSubtarget.h"
23#include "ARMISelLowering.h"
24#include "Thumb1InstrInfo.h"
25#include "Thumb2InstrInfo.h"
26#include "llvm/ADT/OwningPtr.h"
27
28namespace llvm {
29
30class ARMBaseTargetMachine : public LLVMTargetMachine {
31protected:
32  ARMSubtarget        Subtarget;
33
34private:
35  ARMFrameInfo        FrameInfo;
36  ARMJITInfo          JITInfo;
37  InstrItineraryData  InstrItins;
38  Reloc::Model        DefRelocModel;    // Reloc model before it's overridden.
39
40public:
41  ARMBaseTargetMachine(const Target &T, const std::string &TT,
42                       const std::string &FS, bool isThumb);
43
44  virtual const ARMFrameInfo     *getFrameInfo() const { return &FrameInfo; }
45  virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
46  virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
47  virtual const InstrItineraryData getInstrItineraryData() const {
48    return InstrItins;
49  }
50
51  // Pass Pipeline Configuration
52  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
53  virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54  virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
56  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
57                              JITCodeEmitter &MCE);
58};
59
60/// ARMTargetMachine - ARM target machine.
61///
62class ARMTargetMachine : public ARMBaseTargetMachine {
63  ARMInstrInfo        InstrInfo;
64  const TargetData    DataLayout;       // Calculates type size & alignment
65  ARMTargetLowering   TLInfo;
66public:
67  ARMTargetMachine(const Target &T, const std::string &TT,
68                   const std::string &FS);
69
70  virtual const ARMRegisterInfo  *getRegisterInfo() const {
71    return &InstrInfo.getRegisterInfo();
72  }
73
74  virtual const ARMTargetLowering *getTargetLowering() const {
75    return &TLInfo;
76  }
77
78  virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
79  virtual const TargetData       *getTargetData() const { return &DataLayout; }
80};
81
82/// ThumbTargetMachine - Thumb target machine.
83/// Due to the way architectures are handled, this represents both
84///   Thumb-1 and Thumb-2.
85///
86class ThumbTargetMachine : public ARMBaseTargetMachine {
87  // Either Thumb1InstrInfo or Thumb2InstrInfo.
88  OwningPtr<ARMBaseInstrInfo> InstrInfo;
89  const TargetData    DataLayout;   // Calculates type size & alignment
90  ARMTargetLowering   TLInfo;
91public:
92  ThumbTargetMachine(const Target &T, const std::string &TT,
93                     const std::string &FS);
94
95  /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
96  virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
97    return &InstrInfo->getRegisterInfo();
98  }
99
100  virtual const ARMTargetLowering *getTargetLowering() const {
101    return &TLInfo;
102  }
103
104  /// returns either Thumb1InstrInfo or Thumb2InstrInfo
105  virtual const ARMBaseInstrInfo *getInstrInfo() const {
106    return InstrInfo.get();
107  }
108  virtual const TargetData       *getTargetData() const { return &DataLayout; }
109};
110
111} // end namespace llvm
112
113#endif
114