ARMAsmParser.cpp revision 27aacedf7d975243170206efb948a20d6fd4a2c1 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCTargetAsmParser.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMBaseInfo.h"
13#include "MCTargetDesc/ARMMCExpr.h"
14#include "llvm/ADT/BitVector.h"
15#include "llvm/ADT/OwningPtr.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/ADT/Twine.h"
20#include "llvm/MC/MCAsmInfo.h"
21#include "llvm/MC/MCAssembler.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCELFStreamer.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrDesc.h"
27#include "llvm/MC/MCParser/MCAsmLexer.h"
28#include "llvm/MC/MCParser/MCAsmParser.h"
29#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30#include "llvm/MC/MCRegisterInfo.h"
31#include "llvm/MC/MCStreamer.h"
32#include "llvm/MC/MCSubtargetInfo.h"
33#include "llvm/Support/ELF.h"
34#include "llvm/Support/MathExtras.h"
35#include "llvm/Support/SourceMgr.h"
36#include "llvm/Support/TargetRegistry.h"
37#include "llvm/Support/raw_ostream.h"
38
39using namespace llvm;
40
41namespace {
42
43class ARMOperand;
44
45enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
46
47class ARMAsmParser : public MCTargetAsmParser {
48  MCSubtargetInfo &STI;
49  MCAsmParser &Parser;
50  const MCRegisterInfo *MRI;
51
52  // Map of register aliases registers via the .req directive.
53  StringMap<unsigned> RegisterReqs;
54
55  struct {
56    ARMCC::CondCodes Cond;    // Condition for IT block.
57    unsigned Mask:4;          // Condition mask for instructions.
58                              // Starting at first 1 (from lsb).
59                              //   '1'  condition as indicated in IT.
60                              //   '0'  inverse of condition (else).
61                              // Count of instructions in IT block is
62                              // 4 - trailingzeroes(mask)
63
64    bool FirstCond;           // Explicit flag for when we're parsing the
65                              // First instruction in the IT block. It's
66                              // implied in the mask, so needs special
67                              // handling.
68
69    unsigned CurPosition;     // Current position in parsing of IT
70                              // block. In range [0,3]. Initialized
71                              // according to count of instructions in block.
72                              // ~0U if no active IT block.
73  } ITState;
74  bool inITBlock() { return ITState.CurPosition != ~0U;}
75  void forwardITPosition() {
76    if (!inITBlock()) return;
77    // Move to the next instruction in the IT block, if there is one. If not,
78    // mark the block as done.
79    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
80    if (++ITState.CurPosition == 5 - TZ)
81      ITState.CurPosition = ~0U; // Done with the IT block after this.
82  }
83
84
85  MCAsmParser &getParser() const { return Parser; }
86  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
87
88  bool Warning(SMLoc L, const Twine &Msg,
89               ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
90    return Parser.Warning(L, Msg, Ranges);
91  }
92  bool Error(SMLoc L, const Twine &Msg,
93             ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
94    return Parser.Error(L, Msg, Ranges);
95  }
96
97  int tryParseRegister();
98  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
99  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
100  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
101  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
102  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
103  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
104  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
105                              unsigned &ShiftAmount);
106  bool parseDirectiveWord(unsigned Size, SMLoc L);
107  bool parseDirectiveThumb(SMLoc L);
108  bool parseDirectiveARM(SMLoc L);
109  bool parseDirectiveThumbFunc(SMLoc L);
110  bool parseDirectiveCode(SMLoc L);
111  bool parseDirectiveSyntax(SMLoc L);
112  bool parseDirectiveReq(StringRef Name, SMLoc L);
113  bool parseDirectiveUnreq(SMLoc L);
114  bool parseDirectiveArch(SMLoc L);
115  bool parseDirectiveEabiAttr(SMLoc L);
116
117  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
118                          bool &CarrySetting, unsigned &ProcessorIMod,
119                          StringRef &ITMask);
120  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
121                             bool &CanAcceptPredicationCode);
122
123  bool isThumb() const {
124    // FIXME: Can tablegen auto-generate this?
125    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
126  }
127  bool isThumbOne() const {
128    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
129  }
130  bool isThumbTwo() const {
131    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
132  }
133  bool hasV6Ops() const {
134    return STI.getFeatureBits() & ARM::HasV6Ops;
135  }
136  bool hasV7Ops() const {
137    return STI.getFeatureBits() & ARM::HasV7Ops;
138  }
139  void SwitchMode() {
140    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
141    setAvailableFeatures(FB);
142  }
143  bool isMClass() const {
144    return STI.getFeatureBits() & ARM::FeatureMClass;
145  }
146
147  /// @name Auto-generated Match Functions
148  /// {
149
150#define GET_ASSEMBLER_HEADER
151#include "ARMGenAsmMatcher.inc"
152
153  /// }
154
155  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
156  OperandMatchResultTy parseCoprocNumOperand(
157    SmallVectorImpl<MCParsedAsmOperand*>&);
158  OperandMatchResultTy parseCoprocRegOperand(
159    SmallVectorImpl<MCParsedAsmOperand*>&);
160  OperandMatchResultTy parseCoprocOptionOperand(
161    SmallVectorImpl<MCParsedAsmOperand*>&);
162  OperandMatchResultTy parseMemBarrierOptOperand(
163    SmallVectorImpl<MCParsedAsmOperand*>&);
164  OperandMatchResultTy parseProcIFlagsOperand(
165    SmallVectorImpl<MCParsedAsmOperand*>&);
166  OperandMatchResultTy parseMSRMaskOperand(
167    SmallVectorImpl<MCParsedAsmOperand*>&);
168  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
169                                   StringRef Op, int Low, int High);
170  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171    return parsePKHImm(O, "lsl", 0, 31);
172  }
173  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
174    return parsePKHImm(O, "asr", 1, 32);
175  }
176  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
177  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
178  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
179  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
180  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
181  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
182  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
183  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
184  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
185                                       SMLoc &EndLoc);
186
187  // Asm Match Converter Methods
188  void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
189  void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
190  void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
191                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
192  void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
193                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
194  void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
195                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
196  void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
197                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
198  void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
199                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
200  void cvtStWriteBackRegAddrMode2(MCInst &Inst,
201                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
202  void cvtStWriteBackRegAddrMode3(MCInst &Inst,
203                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
204  void cvtLdExtTWriteBackImm(MCInst &Inst,
205                             const SmallVectorImpl<MCParsedAsmOperand*> &);
206  void cvtLdExtTWriteBackReg(MCInst &Inst,
207                             const SmallVectorImpl<MCParsedAsmOperand*> &);
208  void cvtStExtTWriteBackImm(MCInst &Inst,
209                             const SmallVectorImpl<MCParsedAsmOperand*> &);
210  void cvtStExtTWriteBackReg(MCInst &Inst,
211                             const SmallVectorImpl<MCParsedAsmOperand*> &);
212  void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
213  void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
214  void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
215                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
216  void cvtThumbMultiply(MCInst &Inst,
217                        const SmallVectorImpl<MCParsedAsmOperand*> &);
218  void cvtVLDwbFixed(MCInst &Inst,
219                     const SmallVectorImpl<MCParsedAsmOperand*> &);
220  void cvtVLDwbRegister(MCInst &Inst,
221                        const SmallVectorImpl<MCParsedAsmOperand*> &);
222  void cvtVSTwbFixed(MCInst &Inst,
223                     const SmallVectorImpl<MCParsedAsmOperand*> &);
224  void cvtVSTwbRegister(MCInst &Inst,
225                        const SmallVectorImpl<MCParsedAsmOperand*> &);
226  bool validateInstruction(MCInst &Inst,
227                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
228  bool processInstruction(MCInst &Inst,
229                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
230  bool shouldOmitCCOutOperand(StringRef Mnemonic,
231                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
232
233public:
234  enum ARMMatchResultTy {
235    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
236    Match_RequiresNotITBlock,
237    Match_RequiresV6,
238    Match_RequiresThumb2,
239#define GET_OPERAND_DIAGNOSTIC_TYPES
240#include "ARMGenAsmMatcher.inc"
241
242  };
243
244  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
245    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
246    MCAsmParserExtension::Initialize(_Parser);
247
248    // Cache the MCRegisterInfo.
249    MRI = &getContext().getRegisterInfo();
250
251    // Initialize the set of available features.
252    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
253
254    // Not in an ITBlock to start with.
255    ITState.CurPosition = ~0U;
256
257    // Set ELF header flags.
258    // FIXME: This should eventually end up somewhere else where more
259    // intelligent flag decisions can be made. For now we are just maintaining
260    // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
261    if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
262      MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
263  }
264
265  // Implementation of the MCTargetAsmParser interface:
266  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
267  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
268                        SMLoc NameLoc,
269                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
270  bool ParseDirective(AsmToken DirectiveID);
271
272  unsigned checkTargetMatchPredicate(MCInst &Inst);
273
274  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
275                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
276                               MCStreamer &Out, unsigned &ErrorInfo,
277                               bool MatchingInlineAsm);
278};
279} // end anonymous namespace
280
281namespace {
282
283/// ARMOperand - Instances of this class represent a parsed ARM machine
284/// operand.
285class ARMOperand : public MCParsedAsmOperand {
286  enum KindTy {
287    k_CondCode,
288    k_CCOut,
289    k_ITCondMask,
290    k_CoprocNum,
291    k_CoprocReg,
292    k_CoprocOption,
293    k_Immediate,
294    k_MemBarrierOpt,
295    k_Memory,
296    k_PostIndexRegister,
297    k_MSRMask,
298    k_ProcIFlags,
299    k_VectorIndex,
300    k_Register,
301    k_RegisterList,
302    k_DPRRegisterList,
303    k_SPRRegisterList,
304    k_VectorList,
305    k_VectorListAllLanes,
306    k_VectorListIndexed,
307    k_ShiftedRegister,
308    k_ShiftedImmediate,
309    k_ShifterImmediate,
310    k_RotateImmediate,
311    k_BitfieldDescriptor,
312    k_Token
313  } Kind;
314
315  SMLoc StartLoc, EndLoc;
316  SmallVector<unsigned, 8> Registers;
317
318  union {
319    struct {
320      ARMCC::CondCodes Val;
321    } CC;
322
323    struct {
324      unsigned Val;
325    } Cop;
326
327    struct {
328      unsigned Val;
329    } CoprocOption;
330
331    struct {
332      unsigned Mask:4;
333    } ITMask;
334
335    struct {
336      ARM_MB::MemBOpt Val;
337    } MBOpt;
338
339    struct {
340      ARM_PROC::IFlags Val;
341    } IFlags;
342
343    struct {
344      unsigned Val;
345    } MMask;
346
347    struct {
348      const char *Data;
349      unsigned Length;
350    } Tok;
351
352    struct {
353      unsigned RegNum;
354    } Reg;
355
356    // A vector register list is a sequential list of 1 to 4 registers.
357    struct {
358      unsigned RegNum;
359      unsigned Count;
360      unsigned LaneIndex;
361      bool isDoubleSpaced;
362    } VectorList;
363
364    struct {
365      unsigned Val;
366    } VectorIndex;
367
368    struct {
369      const MCExpr *Val;
370    } Imm;
371
372    /// Combined record for all forms of ARM address expressions.
373    struct {
374      unsigned BaseRegNum;
375      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
376      // was specified.
377      const MCConstantExpr *OffsetImm;  // Offset immediate value
378      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
379      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
380      unsigned ShiftImm;        // shift for OffsetReg.
381      unsigned Alignment;       // 0 = no alignment specified
382                                // n = alignment in bytes (2, 4, 8, 16, or 32)
383      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
384    } Memory;
385
386    struct {
387      unsigned RegNum;
388      bool isAdd;
389      ARM_AM::ShiftOpc ShiftTy;
390      unsigned ShiftImm;
391    } PostIdxReg;
392
393    struct {
394      bool isASR;
395      unsigned Imm;
396    } ShifterImm;
397    struct {
398      ARM_AM::ShiftOpc ShiftTy;
399      unsigned SrcReg;
400      unsigned ShiftReg;
401      unsigned ShiftImm;
402    } RegShiftedReg;
403    struct {
404      ARM_AM::ShiftOpc ShiftTy;
405      unsigned SrcReg;
406      unsigned ShiftImm;
407    } RegShiftedImm;
408    struct {
409      unsigned Imm;
410    } RotImm;
411    struct {
412      unsigned LSB;
413      unsigned Width;
414    } Bitfield;
415  };
416
417  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
418public:
419  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
420    Kind = o.Kind;
421    StartLoc = o.StartLoc;
422    EndLoc = o.EndLoc;
423    switch (Kind) {
424    case k_CondCode:
425      CC = o.CC;
426      break;
427    case k_ITCondMask:
428      ITMask = o.ITMask;
429      break;
430    case k_Token:
431      Tok = o.Tok;
432      break;
433    case k_CCOut:
434    case k_Register:
435      Reg = o.Reg;
436      break;
437    case k_RegisterList:
438    case k_DPRRegisterList:
439    case k_SPRRegisterList:
440      Registers = o.Registers;
441      break;
442    case k_VectorList:
443    case k_VectorListAllLanes:
444    case k_VectorListIndexed:
445      VectorList = o.VectorList;
446      break;
447    case k_CoprocNum:
448    case k_CoprocReg:
449      Cop = o.Cop;
450      break;
451    case k_CoprocOption:
452      CoprocOption = o.CoprocOption;
453      break;
454    case k_Immediate:
455      Imm = o.Imm;
456      break;
457    case k_MemBarrierOpt:
458      MBOpt = o.MBOpt;
459      break;
460    case k_Memory:
461      Memory = o.Memory;
462      break;
463    case k_PostIndexRegister:
464      PostIdxReg = o.PostIdxReg;
465      break;
466    case k_MSRMask:
467      MMask = o.MMask;
468      break;
469    case k_ProcIFlags:
470      IFlags = o.IFlags;
471      break;
472    case k_ShifterImmediate:
473      ShifterImm = o.ShifterImm;
474      break;
475    case k_ShiftedRegister:
476      RegShiftedReg = o.RegShiftedReg;
477      break;
478    case k_ShiftedImmediate:
479      RegShiftedImm = o.RegShiftedImm;
480      break;
481    case k_RotateImmediate:
482      RotImm = o.RotImm;
483      break;
484    case k_BitfieldDescriptor:
485      Bitfield = o.Bitfield;
486      break;
487    case k_VectorIndex:
488      VectorIndex = o.VectorIndex;
489      break;
490    }
491  }
492
493  /// getStartLoc - Get the location of the first token of this operand.
494  SMLoc getStartLoc() const { return StartLoc; }
495  /// getEndLoc - Get the location of the last token of this operand.
496  SMLoc getEndLoc() const { return EndLoc; }
497  /// getLocRange - Get the range between the first and last token of this
498  /// operand.
499  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
500
501  ARMCC::CondCodes getCondCode() const {
502    assert(Kind == k_CondCode && "Invalid access!");
503    return CC.Val;
504  }
505
506  unsigned getCoproc() const {
507    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
508    return Cop.Val;
509  }
510
511  StringRef getToken() const {
512    assert(Kind == k_Token && "Invalid access!");
513    return StringRef(Tok.Data, Tok.Length);
514  }
515
516  unsigned getReg() const {
517    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
518    return Reg.RegNum;
519  }
520
521  const SmallVectorImpl<unsigned> &getRegList() const {
522    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
523            Kind == k_SPRRegisterList) && "Invalid access!");
524    return Registers;
525  }
526
527  const MCExpr *getImm() const {
528    assert(isImm() && "Invalid access!");
529    return Imm.Val;
530  }
531
532  unsigned getVectorIndex() const {
533    assert(Kind == k_VectorIndex && "Invalid access!");
534    return VectorIndex.Val;
535  }
536
537  ARM_MB::MemBOpt getMemBarrierOpt() const {
538    assert(Kind == k_MemBarrierOpt && "Invalid access!");
539    return MBOpt.Val;
540  }
541
542  ARM_PROC::IFlags getProcIFlags() const {
543    assert(Kind == k_ProcIFlags && "Invalid access!");
544    return IFlags.Val;
545  }
546
547  unsigned getMSRMask() const {
548    assert(Kind == k_MSRMask && "Invalid access!");
549    return MMask.Val;
550  }
551
552  bool isCoprocNum() const { return Kind == k_CoprocNum; }
553  bool isCoprocReg() const { return Kind == k_CoprocReg; }
554  bool isCoprocOption() const { return Kind == k_CoprocOption; }
555  bool isCondCode() const { return Kind == k_CondCode; }
556  bool isCCOut() const { return Kind == k_CCOut; }
557  bool isITMask() const { return Kind == k_ITCondMask; }
558  bool isITCondCode() const { return Kind == k_CondCode; }
559  bool isImm() const { return Kind == k_Immediate; }
560  bool isFPImm() const {
561    if (!isImm()) return false;
562    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
563    if (!CE) return false;
564    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
565    return Val != -1;
566  }
567  bool isFBits16() const {
568    if (!isImm()) return false;
569    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
570    if (!CE) return false;
571    int64_t Value = CE->getValue();
572    return Value >= 0 && Value <= 16;
573  }
574  bool isFBits32() const {
575    if (!isImm()) return false;
576    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
577    if (!CE) return false;
578    int64_t Value = CE->getValue();
579    return Value >= 1 && Value <= 32;
580  }
581  bool isImm8s4() const {
582    if (!isImm()) return false;
583    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
584    if (!CE) return false;
585    int64_t Value = CE->getValue();
586    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
587  }
588  bool isImm0_1020s4() const {
589    if (!isImm()) return false;
590    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
591    if (!CE) return false;
592    int64_t Value = CE->getValue();
593    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
594  }
595  bool isImm0_508s4() const {
596    if (!isImm()) return false;
597    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
598    if (!CE) return false;
599    int64_t Value = CE->getValue();
600    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
601  }
602  bool isImm0_508s4Neg() const {
603    if (!isImm()) return false;
604    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
605    if (!CE) return false;
606    int64_t Value = -CE->getValue();
607    // explicitly exclude zero. we want that to use the normal 0_508 version.
608    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
609  }
610  bool isImm0_255() const {
611    if (!isImm()) return false;
612    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
613    if (!CE) return false;
614    int64_t Value = CE->getValue();
615    return Value >= 0 && Value < 256;
616  }
617  bool isImm0_4095() const {
618    if (!isImm()) return false;
619    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
620    if (!CE) return false;
621    int64_t Value = CE->getValue();
622    return Value >= 0 && Value < 4096;
623  }
624  bool isImm0_4095Neg() const {
625    if (!isImm()) return false;
626    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
627    if (!CE) return false;
628    int64_t Value = -CE->getValue();
629    return Value > 0 && Value < 4096;
630  }
631  bool isImm0_1() const {
632    if (!isImm()) return false;
633    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
634    if (!CE) return false;
635    int64_t Value = CE->getValue();
636    return Value >= 0 && Value < 2;
637  }
638  bool isImm0_3() const {
639    if (!isImm()) return false;
640    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
641    if (!CE) return false;
642    int64_t Value = CE->getValue();
643    return Value >= 0 && Value < 4;
644  }
645  bool isImm0_7() const {
646    if (!isImm()) return false;
647    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
648    if (!CE) return false;
649    int64_t Value = CE->getValue();
650    return Value >= 0 && Value < 8;
651  }
652  bool isImm0_15() const {
653    if (!isImm()) return false;
654    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
655    if (!CE) return false;
656    int64_t Value = CE->getValue();
657    return Value >= 0 && Value < 16;
658  }
659  bool isImm0_31() const {
660    if (!isImm()) return false;
661    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
662    if (!CE) return false;
663    int64_t Value = CE->getValue();
664    return Value >= 0 && Value < 32;
665  }
666  bool isImm0_63() const {
667    if (!isImm()) return false;
668    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
669    if (!CE) return false;
670    int64_t Value = CE->getValue();
671    return Value >= 0 && Value < 64;
672  }
673  bool isImm8() const {
674    if (!isImm()) return false;
675    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676    if (!CE) return false;
677    int64_t Value = CE->getValue();
678    return Value == 8;
679  }
680  bool isImm16() const {
681    if (!isImm()) return false;
682    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683    if (!CE) return false;
684    int64_t Value = CE->getValue();
685    return Value == 16;
686  }
687  bool isImm32() const {
688    if (!isImm()) return false;
689    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
690    if (!CE) return false;
691    int64_t Value = CE->getValue();
692    return Value == 32;
693  }
694  bool isShrImm8() const {
695    if (!isImm()) return false;
696    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
697    if (!CE) return false;
698    int64_t Value = CE->getValue();
699    return Value > 0 && Value <= 8;
700  }
701  bool isShrImm16() const {
702    if (!isImm()) return false;
703    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
704    if (!CE) return false;
705    int64_t Value = CE->getValue();
706    return Value > 0 && Value <= 16;
707  }
708  bool isShrImm32() const {
709    if (!isImm()) return false;
710    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
711    if (!CE) return false;
712    int64_t Value = CE->getValue();
713    return Value > 0 && Value <= 32;
714  }
715  bool isShrImm64() const {
716    if (!isImm()) return false;
717    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
718    if (!CE) return false;
719    int64_t Value = CE->getValue();
720    return Value > 0 && Value <= 64;
721  }
722  bool isImm1_7() const {
723    if (!isImm()) return false;
724    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
725    if (!CE) return false;
726    int64_t Value = CE->getValue();
727    return Value > 0 && Value < 8;
728  }
729  bool isImm1_15() const {
730    if (!isImm()) return false;
731    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
732    if (!CE) return false;
733    int64_t Value = CE->getValue();
734    return Value > 0 && Value < 16;
735  }
736  bool isImm1_31() const {
737    if (!isImm()) return false;
738    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
739    if (!CE) return false;
740    int64_t Value = CE->getValue();
741    return Value > 0 && Value < 32;
742  }
743  bool isImm1_16() const {
744    if (!isImm()) return false;
745    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
746    if (!CE) return false;
747    int64_t Value = CE->getValue();
748    return Value > 0 && Value < 17;
749  }
750  bool isImm1_32() const {
751    if (!isImm()) return false;
752    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
753    if (!CE) return false;
754    int64_t Value = CE->getValue();
755    return Value > 0 && Value < 33;
756  }
757  bool isImm0_32() const {
758    if (!isImm()) return false;
759    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
760    if (!CE) return false;
761    int64_t Value = CE->getValue();
762    return Value >= 0 && Value < 33;
763  }
764  bool isImm0_65535() const {
765    if (!isImm()) return false;
766    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
767    if (!CE) return false;
768    int64_t Value = CE->getValue();
769    return Value >= 0 && Value < 65536;
770  }
771  bool isImm0_65535Expr() const {
772    if (!isImm()) return false;
773    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
774    // If it's not a constant expression, it'll generate a fixup and be
775    // handled later.
776    if (!CE) return true;
777    int64_t Value = CE->getValue();
778    return Value >= 0 && Value < 65536;
779  }
780  bool isImm24bit() const {
781    if (!isImm()) return false;
782    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
783    if (!CE) return false;
784    int64_t Value = CE->getValue();
785    return Value >= 0 && Value <= 0xffffff;
786  }
787  bool isImmThumbSR() const {
788    if (!isImm()) return false;
789    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
790    if (!CE) return false;
791    int64_t Value = CE->getValue();
792    return Value > 0 && Value < 33;
793  }
794  bool isPKHLSLImm() const {
795    if (!isImm()) return false;
796    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
797    if (!CE) return false;
798    int64_t Value = CE->getValue();
799    return Value >= 0 && Value < 32;
800  }
801  bool isPKHASRImm() const {
802    if (!isImm()) return false;
803    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804    if (!CE) return false;
805    int64_t Value = CE->getValue();
806    return Value > 0 && Value <= 32;
807  }
808  bool isAdrLabel() const {
809    // If we have an immediate that's not a constant, treat it as a label
810    // reference needing a fixup. If it is a constant, but it can't fit
811    // into shift immediate encoding, we reject it.
812    if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
813    else return (isARMSOImm() || isARMSOImmNeg());
814  }
815  bool isARMSOImm() const {
816    if (!isImm()) return false;
817    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
818    if (!CE) return false;
819    int64_t Value = CE->getValue();
820    return ARM_AM::getSOImmVal(Value) != -1;
821  }
822  bool isARMSOImmNot() const {
823    if (!isImm()) return false;
824    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825    if (!CE) return false;
826    int64_t Value = CE->getValue();
827    return ARM_AM::getSOImmVal(~Value) != -1;
828  }
829  bool isARMSOImmNeg() const {
830    if (!isImm()) return false;
831    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832    if (!CE) return false;
833    int64_t Value = CE->getValue();
834    // Only use this when not representable as a plain so_imm.
835    return ARM_AM::getSOImmVal(Value) == -1 &&
836      ARM_AM::getSOImmVal(-Value) != -1;
837  }
838  bool isT2SOImm() const {
839    if (!isImm()) return false;
840    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
841    if (!CE) return false;
842    int64_t Value = CE->getValue();
843    return ARM_AM::getT2SOImmVal(Value) != -1;
844  }
845  bool isT2SOImmNot() const {
846    if (!isImm()) return false;
847    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848    if (!CE) return false;
849    int64_t Value = CE->getValue();
850    return ARM_AM::getT2SOImmVal(~Value) != -1;
851  }
852  bool isT2SOImmNeg() const {
853    if (!isImm()) return false;
854    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855    if (!CE) return false;
856    int64_t Value = CE->getValue();
857    // Only use this when not representable as a plain so_imm.
858    return ARM_AM::getT2SOImmVal(Value) == -1 &&
859      ARM_AM::getT2SOImmVal(-Value) != -1;
860  }
861  bool isSetEndImm() const {
862    if (!isImm()) return false;
863    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
864    if (!CE) return false;
865    int64_t Value = CE->getValue();
866    return Value == 1 || Value == 0;
867  }
868  bool isReg() const { return Kind == k_Register; }
869  bool isRegList() const { return Kind == k_RegisterList; }
870  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
871  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
872  bool isToken() const { return Kind == k_Token; }
873  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
874  bool isMem() const { return Kind == k_Memory; }
875  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
876  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
877  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
878  bool isRotImm() const { return Kind == k_RotateImmediate; }
879  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
880  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
881  bool isPostIdxReg() const {
882    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
883  }
884  bool isMemNoOffset(bool alignOK = false) const {
885    if (!isMem())
886      return false;
887    // No offset of any kind.
888    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
889     (alignOK || Memory.Alignment == 0);
890  }
891  bool isMemPCRelImm12() const {
892    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
893      return false;
894    // Base register must be PC.
895    if (Memory.BaseRegNum != ARM::PC)
896      return false;
897    // Immediate offset in range [-4095, 4095].
898    if (!Memory.OffsetImm) return true;
899    int64_t Val = Memory.OffsetImm->getValue();
900    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
901  }
902  bool isAlignedMemory() const {
903    return isMemNoOffset(true);
904  }
905  bool isAddrMode2() const {
906    if (!isMem() || Memory.Alignment != 0) return false;
907    // Check for register offset.
908    if (Memory.OffsetRegNum) return true;
909    // Immediate offset in range [-4095, 4095].
910    if (!Memory.OffsetImm) return true;
911    int64_t Val = Memory.OffsetImm->getValue();
912    return Val > -4096 && Val < 4096;
913  }
914  bool isAM2OffsetImm() const {
915    if (!isImm()) return false;
916    // Immediate offset in range [-4095, 4095].
917    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
918    if (!CE) return false;
919    int64_t Val = CE->getValue();
920    return Val > -4096 && Val < 4096;
921  }
922  bool isAddrMode3() const {
923    // If we have an immediate that's not a constant, treat it as a label
924    // reference needing a fixup. If it is a constant, it's something else
925    // and we reject it.
926    if (isImm() && !isa<MCConstantExpr>(getImm()))
927      return true;
928    if (!isMem() || Memory.Alignment != 0) return false;
929    // No shifts are legal for AM3.
930    if (Memory.ShiftType != ARM_AM::no_shift) return false;
931    // Check for register offset.
932    if (Memory.OffsetRegNum) return true;
933    // Immediate offset in range [-255, 255].
934    if (!Memory.OffsetImm) return true;
935    int64_t Val = Memory.OffsetImm->getValue();
936    // The #-0 offset is encoded as INT32_MIN, and we have to check
937    // for this too.
938    return (Val > -256 && Val < 256) || Val == INT32_MIN;
939  }
940  bool isAM3Offset() const {
941    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
942      return false;
943    if (Kind == k_PostIndexRegister)
944      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
945    // Immediate offset in range [-255, 255].
946    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
947    if (!CE) return false;
948    int64_t Val = CE->getValue();
949    // Special case, #-0 is INT32_MIN.
950    return (Val > -256 && Val < 256) || Val == INT32_MIN;
951  }
952  bool isAddrMode5() const {
953    // If we have an immediate that's not a constant, treat it as a label
954    // reference needing a fixup. If it is a constant, it's something else
955    // and we reject it.
956    if (isImm() && !isa<MCConstantExpr>(getImm()))
957      return true;
958    if (!isMem() || Memory.Alignment != 0) return false;
959    // Check for register offset.
960    if (Memory.OffsetRegNum) return false;
961    // Immediate offset in range [-1020, 1020] and a multiple of 4.
962    if (!Memory.OffsetImm) return true;
963    int64_t Val = Memory.OffsetImm->getValue();
964    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
965      Val == INT32_MIN;
966  }
967  bool isMemTBB() const {
968    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
969        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
970      return false;
971    return true;
972  }
973  bool isMemTBH() const {
974    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
975        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
976        Memory.Alignment != 0 )
977      return false;
978    return true;
979  }
980  bool isMemRegOffset() const {
981    if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
982      return false;
983    return true;
984  }
985  bool isT2MemRegOffset() const {
986    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
987        Memory.Alignment != 0)
988      return false;
989    // Only lsl #{0, 1, 2, 3} allowed.
990    if (Memory.ShiftType == ARM_AM::no_shift)
991      return true;
992    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
993      return false;
994    return true;
995  }
996  bool isMemThumbRR() const {
997    // Thumb reg+reg addressing is simple. Just two registers, a base and
998    // an offset. No shifts, negations or any other complicating factors.
999    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1000        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1001      return false;
1002    return isARMLowRegister(Memory.BaseRegNum) &&
1003      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1004  }
1005  bool isMemThumbRIs4() const {
1006    if (!isMem() || Memory.OffsetRegNum != 0 ||
1007        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1008      return false;
1009    // Immediate offset, multiple of 4 in range [0, 124].
1010    if (!Memory.OffsetImm) return true;
1011    int64_t Val = Memory.OffsetImm->getValue();
1012    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1013  }
1014  bool isMemThumbRIs2() const {
1015    if (!isMem() || Memory.OffsetRegNum != 0 ||
1016        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1017      return false;
1018    // Immediate offset, multiple of 4 in range [0, 62].
1019    if (!Memory.OffsetImm) return true;
1020    int64_t Val = Memory.OffsetImm->getValue();
1021    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1022  }
1023  bool isMemThumbRIs1() const {
1024    if (!isMem() || Memory.OffsetRegNum != 0 ||
1025        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1026      return false;
1027    // Immediate offset in range [0, 31].
1028    if (!Memory.OffsetImm) return true;
1029    int64_t Val = Memory.OffsetImm->getValue();
1030    return Val >= 0 && Val <= 31;
1031  }
1032  bool isMemThumbSPI() const {
1033    if (!isMem() || Memory.OffsetRegNum != 0 ||
1034        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1035      return false;
1036    // Immediate offset, multiple of 4 in range [0, 1020].
1037    if (!Memory.OffsetImm) return true;
1038    int64_t Val = Memory.OffsetImm->getValue();
1039    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1040  }
1041  bool isMemImm8s4Offset() const {
1042    // If we have an immediate that's not a constant, treat it as a label
1043    // reference needing a fixup. If it is a constant, it's something else
1044    // and we reject it.
1045    if (isImm() && !isa<MCConstantExpr>(getImm()))
1046      return true;
1047    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1048      return false;
1049    // Immediate offset a multiple of 4 in range [-1020, 1020].
1050    if (!Memory.OffsetImm) return true;
1051    int64_t Val = Memory.OffsetImm->getValue();
1052    // Special case, #-0 is INT32_MIN.
1053    return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1054  }
1055  bool isMemImm0_1020s4Offset() const {
1056    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1057      return false;
1058    // Immediate offset a multiple of 4 in range [0, 1020].
1059    if (!Memory.OffsetImm) return true;
1060    int64_t Val = Memory.OffsetImm->getValue();
1061    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1062  }
1063  bool isMemImm8Offset() const {
1064    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1065      return false;
1066    // Base reg of PC isn't allowed for these encodings.
1067    if (Memory.BaseRegNum == ARM::PC) return false;
1068    // Immediate offset in range [-255, 255].
1069    if (!Memory.OffsetImm) return true;
1070    int64_t Val = Memory.OffsetImm->getValue();
1071    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1072  }
1073  bool isMemPosImm8Offset() const {
1074    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1075      return false;
1076    // Immediate offset in range [0, 255].
1077    if (!Memory.OffsetImm) return true;
1078    int64_t Val = Memory.OffsetImm->getValue();
1079    return Val >= 0 && Val < 256;
1080  }
1081  bool isMemNegImm8Offset() const {
1082    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1083      return false;
1084    // Base reg of PC isn't allowed for these encodings.
1085    if (Memory.BaseRegNum == ARM::PC) return false;
1086    // Immediate offset in range [-255, -1].
1087    if (!Memory.OffsetImm) return false;
1088    int64_t Val = Memory.OffsetImm->getValue();
1089    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1090  }
1091  bool isMemUImm12Offset() const {
1092    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1093      return false;
1094    // Immediate offset in range [0, 4095].
1095    if (!Memory.OffsetImm) return true;
1096    int64_t Val = Memory.OffsetImm->getValue();
1097    return (Val >= 0 && Val < 4096);
1098  }
1099  bool isMemImm12Offset() const {
1100    // If we have an immediate that's not a constant, treat it as a label
1101    // reference needing a fixup. If it is a constant, it's something else
1102    // and we reject it.
1103    if (isImm() && !isa<MCConstantExpr>(getImm()))
1104      return true;
1105
1106    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1107      return false;
1108    // Immediate offset in range [-4095, 4095].
1109    if (!Memory.OffsetImm) return true;
1110    int64_t Val = Memory.OffsetImm->getValue();
1111    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1112  }
1113  bool isPostIdxImm8() const {
1114    if (!isImm()) return false;
1115    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1116    if (!CE) return false;
1117    int64_t Val = CE->getValue();
1118    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1119  }
1120  bool isPostIdxImm8s4() const {
1121    if (!isImm()) return false;
1122    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1123    if (!CE) return false;
1124    int64_t Val = CE->getValue();
1125    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1126      (Val == INT32_MIN);
1127  }
1128
1129  bool isMSRMask() const { return Kind == k_MSRMask; }
1130  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1131
1132  // NEON operands.
1133  bool isSingleSpacedVectorList() const {
1134    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1135  }
1136  bool isDoubleSpacedVectorList() const {
1137    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1138  }
1139  bool isVecListOneD() const {
1140    if (!isSingleSpacedVectorList()) return false;
1141    return VectorList.Count == 1;
1142  }
1143
1144  bool isVecListDPair() const {
1145    if (!isSingleSpacedVectorList()) return false;
1146    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1147              .contains(VectorList.RegNum));
1148  }
1149
1150  bool isVecListThreeD() const {
1151    if (!isSingleSpacedVectorList()) return false;
1152    return VectorList.Count == 3;
1153  }
1154
1155  bool isVecListFourD() const {
1156    if (!isSingleSpacedVectorList()) return false;
1157    return VectorList.Count == 4;
1158  }
1159
1160  bool isVecListDPairSpaced() const {
1161    if (isSingleSpacedVectorList()) return false;
1162    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1163              .contains(VectorList.RegNum));
1164  }
1165
1166  bool isVecListThreeQ() const {
1167    if (!isDoubleSpacedVectorList()) return false;
1168    return VectorList.Count == 3;
1169  }
1170
1171  bool isVecListFourQ() const {
1172    if (!isDoubleSpacedVectorList()) return false;
1173    return VectorList.Count == 4;
1174  }
1175
1176  bool isSingleSpacedVectorAllLanes() const {
1177    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1178  }
1179  bool isDoubleSpacedVectorAllLanes() const {
1180    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1181  }
1182  bool isVecListOneDAllLanes() const {
1183    if (!isSingleSpacedVectorAllLanes()) return false;
1184    return VectorList.Count == 1;
1185  }
1186
1187  bool isVecListDPairAllLanes() const {
1188    if (!isSingleSpacedVectorAllLanes()) return false;
1189    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1190              .contains(VectorList.RegNum));
1191  }
1192
1193  bool isVecListDPairSpacedAllLanes() const {
1194    if (!isDoubleSpacedVectorAllLanes()) return false;
1195    return VectorList.Count == 2;
1196  }
1197
1198  bool isVecListThreeDAllLanes() const {
1199    if (!isSingleSpacedVectorAllLanes()) return false;
1200    return VectorList.Count == 3;
1201  }
1202
1203  bool isVecListThreeQAllLanes() const {
1204    if (!isDoubleSpacedVectorAllLanes()) return false;
1205    return VectorList.Count == 3;
1206  }
1207
1208  bool isVecListFourDAllLanes() const {
1209    if (!isSingleSpacedVectorAllLanes()) return false;
1210    return VectorList.Count == 4;
1211  }
1212
1213  bool isVecListFourQAllLanes() const {
1214    if (!isDoubleSpacedVectorAllLanes()) return false;
1215    return VectorList.Count == 4;
1216  }
1217
1218  bool isSingleSpacedVectorIndexed() const {
1219    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1220  }
1221  bool isDoubleSpacedVectorIndexed() const {
1222    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1223  }
1224  bool isVecListOneDByteIndexed() const {
1225    if (!isSingleSpacedVectorIndexed()) return false;
1226    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1227  }
1228
1229  bool isVecListOneDHWordIndexed() const {
1230    if (!isSingleSpacedVectorIndexed()) return false;
1231    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1232  }
1233
1234  bool isVecListOneDWordIndexed() const {
1235    if (!isSingleSpacedVectorIndexed()) return false;
1236    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1237  }
1238
1239  bool isVecListTwoDByteIndexed() const {
1240    if (!isSingleSpacedVectorIndexed()) return false;
1241    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1242  }
1243
1244  bool isVecListTwoDHWordIndexed() const {
1245    if (!isSingleSpacedVectorIndexed()) return false;
1246    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1247  }
1248
1249  bool isVecListTwoQWordIndexed() const {
1250    if (!isDoubleSpacedVectorIndexed()) return false;
1251    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1252  }
1253
1254  bool isVecListTwoQHWordIndexed() const {
1255    if (!isDoubleSpacedVectorIndexed()) return false;
1256    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1257  }
1258
1259  bool isVecListTwoDWordIndexed() const {
1260    if (!isSingleSpacedVectorIndexed()) return false;
1261    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1262  }
1263
1264  bool isVecListThreeDByteIndexed() const {
1265    if (!isSingleSpacedVectorIndexed()) return false;
1266    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1267  }
1268
1269  bool isVecListThreeDHWordIndexed() const {
1270    if (!isSingleSpacedVectorIndexed()) return false;
1271    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1272  }
1273
1274  bool isVecListThreeQWordIndexed() const {
1275    if (!isDoubleSpacedVectorIndexed()) return false;
1276    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1277  }
1278
1279  bool isVecListThreeQHWordIndexed() const {
1280    if (!isDoubleSpacedVectorIndexed()) return false;
1281    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1282  }
1283
1284  bool isVecListThreeDWordIndexed() const {
1285    if (!isSingleSpacedVectorIndexed()) return false;
1286    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1287  }
1288
1289  bool isVecListFourDByteIndexed() const {
1290    if (!isSingleSpacedVectorIndexed()) return false;
1291    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1292  }
1293
1294  bool isVecListFourDHWordIndexed() const {
1295    if (!isSingleSpacedVectorIndexed()) return false;
1296    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1297  }
1298
1299  bool isVecListFourQWordIndexed() const {
1300    if (!isDoubleSpacedVectorIndexed()) return false;
1301    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1302  }
1303
1304  bool isVecListFourQHWordIndexed() const {
1305    if (!isDoubleSpacedVectorIndexed()) return false;
1306    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1307  }
1308
1309  bool isVecListFourDWordIndexed() const {
1310    if (!isSingleSpacedVectorIndexed()) return false;
1311    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1312  }
1313
1314  bool isVectorIndex8() const {
1315    if (Kind != k_VectorIndex) return false;
1316    return VectorIndex.Val < 8;
1317  }
1318  bool isVectorIndex16() const {
1319    if (Kind != k_VectorIndex) return false;
1320    return VectorIndex.Val < 4;
1321  }
1322  bool isVectorIndex32() const {
1323    if (Kind != k_VectorIndex) return false;
1324    return VectorIndex.Val < 2;
1325  }
1326
1327  bool isNEONi8splat() const {
1328    if (!isImm()) return false;
1329    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1330    // Must be a constant.
1331    if (!CE) return false;
1332    int64_t Value = CE->getValue();
1333    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1334    // value.
1335    return Value >= 0 && Value < 256;
1336  }
1337
1338  bool isNEONi16splat() const {
1339    if (!isImm()) return false;
1340    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1341    // Must be a constant.
1342    if (!CE) return false;
1343    int64_t Value = CE->getValue();
1344    // i16 value in the range [0,255] or [0x0100, 0xff00]
1345    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1346  }
1347
1348  bool isNEONi32splat() const {
1349    if (!isImm()) return false;
1350    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1351    // Must be a constant.
1352    if (!CE) return false;
1353    int64_t Value = CE->getValue();
1354    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1355    return (Value >= 0 && Value < 256) ||
1356      (Value >= 0x0100 && Value <= 0xff00) ||
1357      (Value >= 0x010000 && Value <= 0xff0000) ||
1358      (Value >= 0x01000000 && Value <= 0xff000000);
1359  }
1360
1361  bool isNEONi32vmov() const {
1362    if (!isImm()) return false;
1363    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1364    // Must be a constant.
1365    if (!CE) return false;
1366    int64_t Value = CE->getValue();
1367    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1368    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1369    return (Value >= 0 && Value < 256) ||
1370      (Value >= 0x0100 && Value <= 0xff00) ||
1371      (Value >= 0x010000 && Value <= 0xff0000) ||
1372      (Value >= 0x01000000 && Value <= 0xff000000) ||
1373      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1374      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1375  }
1376  bool isNEONi32vmovNeg() const {
1377    if (!isImm()) return false;
1378    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1379    // Must be a constant.
1380    if (!CE) return false;
1381    int64_t Value = ~CE->getValue();
1382    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1383    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1384    return (Value >= 0 && Value < 256) ||
1385      (Value >= 0x0100 && Value <= 0xff00) ||
1386      (Value >= 0x010000 && Value <= 0xff0000) ||
1387      (Value >= 0x01000000 && Value <= 0xff000000) ||
1388      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1389      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1390  }
1391
1392  bool isNEONi64splat() const {
1393    if (!isImm()) return false;
1394    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1395    // Must be a constant.
1396    if (!CE) return false;
1397    uint64_t Value = CE->getValue();
1398    // i64 value with each byte being either 0 or 0xff.
1399    for (unsigned i = 0; i < 8; ++i)
1400      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1401    return true;
1402  }
1403
1404  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1405    // Add as immediates when possible.  Null MCExpr = 0.
1406    if (Expr == 0)
1407      Inst.addOperand(MCOperand::CreateImm(0));
1408    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1409      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1410    else
1411      Inst.addOperand(MCOperand::CreateExpr(Expr));
1412  }
1413
1414  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1415    assert(N == 2 && "Invalid number of operands!");
1416    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1417    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1418    Inst.addOperand(MCOperand::CreateReg(RegNum));
1419  }
1420
1421  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1422    assert(N == 1 && "Invalid number of operands!");
1423    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1424  }
1425
1426  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1427    assert(N == 1 && "Invalid number of operands!");
1428    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1429  }
1430
1431  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1432    assert(N == 1 && "Invalid number of operands!");
1433    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1434  }
1435
1436  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1437    assert(N == 1 && "Invalid number of operands!");
1438    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1439  }
1440
1441  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1442    assert(N == 1 && "Invalid number of operands!");
1443    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1444  }
1445
1446  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1447    assert(N == 1 && "Invalid number of operands!");
1448    Inst.addOperand(MCOperand::CreateReg(getReg()));
1449  }
1450
1451  void addRegOperands(MCInst &Inst, unsigned N) const {
1452    assert(N == 1 && "Invalid number of operands!");
1453    Inst.addOperand(MCOperand::CreateReg(getReg()));
1454  }
1455
1456  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1457    assert(N == 3 && "Invalid number of operands!");
1458    assert(isRegShiftedReg() &&
1459           "addRegShiftedRegOperands() on non RegShiftedReg!");
1460    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1461    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1462    Inst.addOperand(MCOperand::CreateImm(
1463      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1464  }
1465
1466  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1467    assert(N == 2 && "Invalid number of operands!");
1468    assert(isRegShiftedImm() &&
1469           "addRegShiftedImmOperands() on non RegShiftedImm!");
1470    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1471    // Shift of #32 is encoded as 0 where permitted
1472    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1473    Inst.addOperand(MCOperand::CreateImm(
1474      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1475  }
1476
1477  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1478    assert(N == 1 && "Invalid number of operands!");
1479    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1480                                         ShifterImm.Imm));
1481  }
1482
1483  void addRegListOperands(MCInst &Inst, unsigned N) const {
1484    assert(N == 1 && "Invalid number of operands!");
1485    const SmallVectorImpl<unsigned> &RegList = getRegList();
1486    for (SmallVectorImpl<unsigned>::const_iterator
1487           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1488      Inst.addOperand(MCOperand::CreateReg(*I));
1489  }
1490
1491  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1492    addRegListOperands(Inst, N);
1493  }
1494
1495  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1496    addRegListOperands(Inst, N);
1497  }
1498
1499  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1500    assert(N == 1 && "Invalid number of operands!");
1501    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1502    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1503  }
1504
1505  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1506    assert(N == 1 && "Invalid number of operands!");
1507    // Munge the lsb/width into a bitfield mask.
1508    unsigned lsb = Bitfield.LSB;
1509    unsigned width = Bitfield.Width;
1510    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1511    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1512                      (32 - (lsb + width)));
1513    Inst.addOperand(MCOperand::CreateImm(Mask));
1514  }
1515
1516  void addImmOperands(MCInst &Inst, unsigned N) const {
1517    assert(N == 1 && "Invalid number of operands!");
1518    addExpr(Inst, getImm());
1519  }
1520
1521  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1522    assert(N == 1 && "Invalid number of operands!");
1523    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1524    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1525  }
1526
1527  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1528    assert(N == 1 && "Invalid number of operands!");
1529    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1530    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1531  }
1532
1533  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1534    assert(N == 1 && "Invalid number of operands!");
1535    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1536    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1537    Inst.addOperand(MCOperand::CreateImm(Val));
1538  }
1539
1540  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1541    assert(N == 1 && "Invalid number of operands!");
1542    // FIXME: We really want to scale the value here, but the LDRD/STRD
1543    // instruction don't encode operands that way yet.
1544    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1545    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1546  }
1547
1548  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1549    assert(N == 1 && "Invalid number of operands!");
1550    // The immediate is scaled by four in the encoding and is stored
1551    // in the MCInst as such. Lop off the low two bits here.
1552    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1553    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1554  }
1555
1556  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1557    assert(N == 1 && "Invalid number of operands!");
1558    // The immediate is scaled by four in the encoding and is stored
1559    // in the MCInst as such. Lop off the low two bits here.
1560    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1561    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1562  }
1563
1564  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1565    assert(N == 1 && "Invalid number of operands!");
1566    // The immediate is scaled by four in the encoding and is stored
1567    // in the MCInst as such. Lop off the low two bits here.
1568    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1569    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1570  }
1571
1572  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1573    assert(N == 1 && "Invalid number of operands!");
1574    // The constant encodes as the immediate-1, and we store in the instruction
1575    // the bits as encoded, so subtract off one here.
1576    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1577    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1578  }
1579
1580  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1581    assert(N == 1 && "Invalid number of operands!");
1582    // The constant encodes as the immediate-1, and we store in the instruction
1583    // the bits as encoded, so subtract off one here.
1584    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1585    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1586  }
1587
1588  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1589    assert(N == 1 && "Invalid number of operands!");
1590    // The constant encodes as the immediate, except for 32, which encodes as
1591    // zero.
1592    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1593    unsigned Imm = CE->getValue();
1594    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1595  }
1596
1597  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1598    assert(N == 1 && "Invalid number of operands!");
1599    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1600    // the instruction as well.
1601    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1602    int Val = CE->getValue();
1603    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1604  }
1605
1606  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1607    assert(N == 1 && "Invalid number of operands!");
1608    // The operand is actually a t2_so_imm, but we have its bitwise
1609    // negation in the assembly source, so twiddle it here.
1610    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1611    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1612  }
1613
1614  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1615    assert(N == 1 && "Invalid number of operands!");
1616    // The operand is actually a t2_so_imm, but we have its
1617    // negation in the assembly source, so twiddle it here.
1618    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1619    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1620  }
1621
1622  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1623    assert(N == 1 && "Invalid number of operands!");
1624    // The operand is actually an imm0_4095, but we have its
1625    // negation in the assembly source, so twiddle it here.
1626    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1627    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1628  }
1629
1630  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1631    assert(N == 1 && "Invalid number of operands!");
1632    // The operand is actually a so_imm, but we have its bitwise
1633    // negation in the assembly source, so twiddle it here.
1634    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1635    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1636  }
1637
1638  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1639    assert(N == 1 && "Invalid number of operands!");
1640    // The operand is actually a so_imm, but we have its
1641    // negation in the assembly source, so twiddle it here.
1642    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1643    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1644  }
1645
1646  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1647    assert(N == 1 && "Invalid number of operands!");
1648    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1649  }
1650
1651  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1652    assert(N == 1 && "Invalid number of operands!");
1653    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1654  }
1655
1656  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1657    assert(N == 1 && "Invalid number of operands!");
1658    int32_t Imm = Memory.OffsetImm->getValue();
1659    // FIXME: Handle #-0
1660    if (Imm == INT32_MIN) Imm = 0;
1661    Inst.addOperand(MCOperand::CreateImm(Imm));
1662  }
1663
1664  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1665    assert(N == 1 && "Invalid number of operands!");
1666    assert(isImm() && "Not an immediate!");
1667
1668    // If we have an immediate that's not a constant, treat it as a label
1669    // reference needing a fixup.
1670    if (!isa<MCConstantExpr>(getImm())) {
1671      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1672      return;
1673    }
1674
1675    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1676    int Val = CE->getValue();
1677    Inst.addOperand(MCOperand::CreateImm(Val));
1678  }
1679
1680  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1681    assert(N == 2 && "Invalid number of operands!");
1682    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1683    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1684  }
1685
1686  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1687    assert(N == 3 && "Invalid number of operands!");
1688    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1689    if (!Memory.OffsetRegNum) {
1690      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1691      // Special case for #-0
1692      if (Val == INT32_MIN) Val = 0;
1693      if (Val < 0) Val = -Val;
1694      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1695    } else {
1696      // For register offset, we encode the shift type and negation flag
1697      // here.
1698      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1699                              Memory.ShiftImm, Memory.ShiftType);
1700    }
1701    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1702    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1703    Inst.addOperand(MCOperand::CreateImm(Val));
1704  }
1705
1706  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1707    assert(N == 2 && "Invalid number of operands!");
1708    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1709    assert(CE && "non-constant AM2OffsetImm operand!");
1710    int32_t Val = CE->getValue();
1711    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1712    // Special case for #-0
1713    if (Val == INT32_MIN) Val = 0;
1714    if (Val < 0) Val = -Val;
1715    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1716    Inst.addOperand(MCOperand::CreateReg(0));
1717    Inst.addOperand(MCOperand::CreateImm(Val));
1718  }
1719
1720  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1721    assert(N == 3 && "Invalid number of operands!");
1722    // If we have an immediate that's not a constant, treat it as a label
1723    // reference needing a fixup. If it is a constant, it's something else
1724    // and we reject it.
1725    if (isImm()) {
1726      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1727      Inst.addOperand(MCOperand::CreateReg(0));
1728      Inst.addOperand(MCOperand::CreateImm(0));
1729      return;
1730    }
1731
1732    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1733    if (!Memory.OffsetRegNum) {
1734      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1735      // Special case for #-0
1736      if (Val == INT32_MIN) Val = 0;
1737      if (Val < 0) Val = -Val;
1738      Val = ARM_AM::getAM3Opc(AddSub, Val);
1739    } else {
1740      // For register offset, we encode the shift type and negation flag
1741      // here.
1742      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1743    }
1744    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1745    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1746    Inst.addOperand(MCOperand::CreateImm(Val));
1747  }
1748
1749  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1750    assert(N == 2 && "Invalid number of operands!");
1751    if (Kind == k_PostIndexRegister) {
1752      int32_t Val =
1753        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1754      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1755      Inst.addOperand(MCOperand::CreateImm(Val));
1756      return;
1757    }
1758
1759    // Constant offset.
1760    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1761    int32_t Val = CE->getValue();
1762    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1763    // Special case for #-0
1764    if (Val == INT32_MIN) Val = 0;
1765    if (Val < 0) Val = -Val;
1766    Val = ARM_AM::getAM3Opc(AddSub, Val);
1767    Inst.addOperand(MCOperand::CreateReg(0));
1768    Inst.addOperand(MCOperand::CreateImm(Val));
1769  }
1770
1771  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1772    assert(N == 2 && "Invalid number of operands!");
1773    // If we have an immediate that's not a constant, treat it as a label
1774    // reference needing a fixup. If it is a constant, it's something else
1775    // and we reject it.
1776    if (isImm()) {
1777      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1778      Inst.addOperand(MCOperand::CreateImm(0));
1779      return;
1780    }
1781
1782    // The lower two bits are always zero and as such are not encoded.
1783    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1784    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1785    // Special case for #-0
1786    if (Val == INT32_MIN) Val = 0;
1787    if (Val < 0) Val = -Val;
1788    Val = ARM_AM::getAM5Opc(AddSub, Val);
1789    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1790    Inst.addOperand(MCOperand::CreateImm(Val));
1791  }
1792
1793  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1794    assert(N == 2 && "Invalid number of operands!");
1795    // If we have an immediate that's not a constant, treat it as a label
1796    // reference needing a fixup. If it is a constant, it's something else
1797    // and we reject it.
1798    if (isImm()) {
1799      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1800      Inst.addOperand(MCOperand::CreateImm(0));
1801      return;
1802    }
1803
1804    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1805    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1806    Inst.addOperand(MCOperand::CreateImm(Val));
1807  }
1808
1809  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1810    assert(N == 2 && "Invalid number of operands!");
1811    // The lower two bits are always zero and as such are not encoded.
1812    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1813    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1814    Inst.addOperand(MCOperand::CreateImm(Val));
1815  }
1816
1817  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1818    assert(N == 2 && "Invalid number of operands!");
1819    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1820    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1821    Inst.addOperand(MCOperand::CreateImm(Val));
1822  }
1823
1824  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1825    addMemImm8OffsetOperands(Inst, N);
1826  }
1827
1828  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1829    addMemImm8OffsetOperands(Inst, N);
1830  }
1831
1832  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1833    assert(N == 2 && "Invalid number of operands!");
1834    // If this is an immediate, it's a label reference.
1835    if (isImm()) {
1836      addExpr(Inst, getImm());
1837      Inst.addOperand(MCOperand::CreateImm(0));
1838      return;
1839    }
1840
1841    // Otherwise, it's a normal memory reg+offset.
1842    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1843    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1844    Inst.addOperand(MCOperand::CreateImm(Val));
1845  }
1846
1847  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1848    assert(N == 2 && "Invalid number of operands!");
1849    // If this is an immediate, it's a label reference.
1850    if (isImm()) {
1851      addExpr(Inst, getImm());
1852      Inst.addOperand(MCOperand::CreateImm(0));
1853      return;
1854    }
1855
1856    // Otherwise, it's a normal memory reg+offset.
1857    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1858    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1859    Inst.addOperand(MCOperand::CreateImm(Val));
1860  }
1861
1862  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1863    assert(N == 2 && "Invalid number of operands!");
1864    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1865    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1866  }
1867
1868  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1869    assert(N == 2 && "Invalid number of operands!");
1870    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1871    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1872  }
1873
1874  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1875    assert(N == 3 && "Invalid number of operands!");
1876    unsigned Val =
1877      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1878                        Memory.ShiftImm, Memory.ShiftType);
1879    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1880    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1881    Inst.addOperand(MCOperand::CreateImm(Val));
1882  }
1883
1884  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1885    assert(N == 3 && "Invalid number of operands!");
1886    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1887    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1888    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1889  }
1890
1891  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1892    assert(N == 2 && "Invalid number of operands!");
1893    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1894    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1895  }
1896
1897  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1898    assert(N == 2 && "Invalid number of operands!");
1899    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1900    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1901    Inst.addOperand(MCOperand::CreateImm(Val));
1902  }
1903
1904  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1905    assert(N == 2 && "Invalid number of operands!");
1906    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1907    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1908    Inst.addOperand(MCOperand::CreateImm(Val));
1909  }
1910
1911  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1912    assert(N == 2 && "Invalid number of operands!");
1913    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1914    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1915    Inst.addOperand(MCOperand::CreateImm(Val));
1916  }
1917
1918  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1919    assert(N == 2 && "Invalid number of operands!");
1920    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1921    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1922    Inst.addOperand(MCOperand::CreateImm(Val));
1923  }
1924
1925  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1926    assert(N == 1 && "Invalid number of operands!");
1927    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1928    assert(CE && "non-constant post-idx-imm8 operand!");
1929    int Imm = CE->getValue();
1930    bool isAdd = Imm >= 0;
1931    if (Imm == INT32_MIN) Imm = 0;
1932    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1933    Inst.addOperand(MCOperand::CreateImm(Imm));
1934  }
1935
1936  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1937    assert(N == 1 && "Invalid number of operands!");
1938    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1939    assert(CE && "non-constant post-idx-imm8s4 operand!");
1940    int Imm = CE->getValue();
1941    bool isAdd = Imm >= 0;
1942    if (Imm == INT32_MIN) Imm = 0;
1943    // Immediate is scaled by 4.
1944    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1945    Inst.addOperand(MCOperand::CreateImm(Imm));
1946  }
1947
1948  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1949    assert(N == 2 && "Invalid number of operands!");
1950    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1951    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1952  }
1953
1954  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1955    assert(N == 2 && "Invalid number of operands!");
1956    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1957    // The sign, shift type, and shift amount are encoded in a single operand
1958    // using the AM2 encoding helpers.
1959    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1960    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1961                                     PostIdxReg.ShiftTy);
1962    Inst.addOperand(MCOperand::CreateImm(Imm));
1963  }
1964
1965  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1966    assert(N == 1 && "Invalid number of operands!");
1967    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1968  }
1969
1970  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1971    assert(N == 1 && "Invalid number of operands!");
1972    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1973  }
1974
1975  void addVecListOperands(MCInst &Inst, unsigned N) const {
1976    assert(N == 1 && "Invalid number of operands!");
1977    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1978  }
1979
1980  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1981    assert(N == 2 && "Invalid number of operands!");
1982    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1983    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1984  }
1985
1986  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1987    assert(N == 1 && "Invalid number of operands!");
1988    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1989  }
1990
1991  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1992    assert(N == 1 && "Invalid number of operands!");
1993    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1994  }
1995
1996  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1997    assert(N == 1 && "Invalid number of operands!");
1998    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1999  }
2000
2001  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2002    assert(N == 1 && "Invalid number of operands!");
2003    // The immediate encodes the type of constant as well as the value.
2004    // Mask in that this is an i8 splat.
2005    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2006    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2007  }
2008
2009  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2010    assert(N == 1 && "Invalid number of operands!");
2011    // The immediate encodes the type of constant as well as the value.
2012    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2013    unsigned Value = CE->getValue();
2014    if (Value >= 256)
2015      Value = (Value >> 8) | 0xa00;
2016    else
2017      Value |= 0x800;
2018    Inst.addOperand(MCOperand::CreateImm(Value));
2019  }
2020
2021  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2022    assert(N == 1 && "Invalid number of operands!");
2023    // The immediate encodes the type of constant as well as the value.
2024    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2025    unsigned Value = CE->getValue();
2026    if (Value >= 256 && Value <= 0xff00)
2027      Value = (Value >> 8) | 0x200;
2028    else if (Value > 0xffff && Value <= 0xff0000)
2029      Value = (Value >> 16) | 0x400;
2030    else if (Value > 0xffffff)
2031      Value = (Value >> 24) | 0x600;
2032    Inst.addOperand(MCOperand::CreateImm(Value));
2033  }
2034
2035  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2036    assert(N == 1 && "Invalid number of operands!");
2037    // The immediate encodes the type of constant as well as the value.
2038    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2039    unsigned Value = CE->getValue();
2040    if (Value >= 256 && Value <= 0xffff)
2041      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2042    else if (Value > 0xffff && Value <= 0xffffff)
2043      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2044    else if (Value > 0xffffff)
2045      Value = (Value >> 24) | 0x600;
2046    Inst.addOperand(MCOperand::CreateImm(Value));
2047  }
2048
2049  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2050    assert(N == 1 && "Invalid number of operands!");
2051    // The immediate encodes the type of constant as well as the value.
2052    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2053    unsigned Value = ~CE->getValue();
2054    if (Value >= 256 && Value <= 0xffff)
2055      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2056    else if (Value > 0xffff && Value <= 0xffffff)
2057      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2058    else if (Value > 0xffffff)
2059      Value = (Value >> 24) | 0x600;
2060    Inst.addOperand(MCOperand::CreateImm(Value));
2061  }
2062
2063  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2064    assert(N == 1 && "Invalid number of operands!");
2065    // The immediate encodes the type of constant as well as the value.
2066    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2067    uint64_t Value = CE->getValue();
2068    unsigned Imm = 0;
2069    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2070      Imm |= (Value & 1) << i;
2071    }
2072    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2073  }
2074
2075  virtual void print(raw_ostream &OS) const;
2076
2077  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2078    ARMOperand *Op = new ARMOperand(k_ITCondMask);
2079    Op->ITMask.Mask = Mask;
2080    Op->StartLoc = S;
2081    Op->EndLoc = S;
2082    return Op;
2083  }
2084
2085  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2086    ARMOperand *Op = new ARMOperand(k_CondCode);
2087    Op->CC.Val = CC;
2088    Op->StartLoc = S;
2089    Op->EndLoc = S;
2090    return Op;
2091  }
2092
2093  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2094    ARMOperand *Op = new ARMOperand(k_CoprocNum);
2095    Op->Cop.Val = CopVal;
2096    Op->StartLoc = S;
2097    Op->EndLoc = S;
2098    return Op;
2099  }
2100
2101  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2102    ARMOperand *Op = new ARMOperand(k_CoprocReg);
2103    Op->Cop.Val = CopVal;
2104    Op->StartLoc = S;
2105    Op->EndLoc = S;
2106    return Op;
2107  }
2108
2109  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2110    ARMOperand *Op = new ARMOperand(k_CoprocOption);
2111    Op->Cop.Val = Val;
2112    Op->StartLoc = S;
2113    Op->EndLoc = E;
2114    return Op;
2115  }
2116
2117  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2118    ARMOperand *Op = new ARMOperand(k_CCOut);
2119    Op->Reg.RegNum = RegNum;
2120    Op->StartLoc = S;
2121    Op->EndLoc = S;
2122    return Op;
2123  }
2124
2125  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2126    ARMOperand *Op = new ARMOperand(k_Token);
2127    Op->Tok.Data = Str.data();
2128    Op->Tok.Length = Str.size();
2129    Op->StartLoc = S;
2130    Op->EndLoc = S;
2131    return Op;
2132  }
2133
2134  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2135    ARMOperand *Op = new ARMOperand(k_Register);
2136    Op->Reg.RegNum = RegNum;
2137    Op->StartLoc = S;
2138    Op->EndLoc = E;
2139    return Op;
2140  }
2141
2142  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2143                                           unsigned SrcReg,
2144                                           unsigned ShiftReg,
2145                                           unsigned ShiftImm,
2146                                           SMLoc S, SMLoc E) {
2147    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2148    Op->RegShiftedReg.ShiftTy = ShTy;
2149    Op->RegShiftedReg.SrcReg = SrcReg;
2150    Op->RegShiftedReg.ShiftReg = ShiftReg;
2151    Op->RegShiftedReg.ShiftImm = ShiftImm;
2152    Op->StartLoc = S;
2153    Op->EndLoc = E;
2154    return Op;
2155  }
2156
2157  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2158                                            unsigned SrcReg,
2159                                            unsigned ShiftImm,
2160                                            SMLoc S, SMLoc E) {
2161    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2162    Op->RegShiftedImm.ShiftTy = ShTy;
2163    Op->RegShiftedImm.SrcReg = SrcReg;
2164    Op->RegShiftedImm.ShiftImm = ShiftImm;
2165    Op->StartLoc = S;
2166    Op->EndLoc = E;
2167    return Op;
2168  }
2169
2170  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2171                                   SMLoc S, SMLoc E) {
2172    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2173    Op->ShifterImm.isASR = isASR;
2174    Op->ShifterImm.Imm = Imm;
2175    Op->StartLoc = S;
2176    Op->EndLoc = E;
2177    return Op;
2178  }
2179
2180  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2181    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2182    Op->RotImm.Imm = Imm;
2183    Op->StartLoc = S;
2184    Op->EndLoc = E;
2185    return Op;
2186  }
2187
2188  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2189                                    SMLoc S, SMLoc E) {
2190    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2191    Op->Bitfield.LSB = LSB;
2192    Op->Bitfield.Width = Width;
2193    Op->StartLoc = S;
2194    Op->EndLoc = E;
2195    return Op;
2196  }
2197
2198  static ARMOperand *
2199  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2200                SMLoc StartLoc, SMLoc EndLoc) {
2201    KindTy Kind = k_RegisterList;
2202
2203    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2204      Kind = k_DPRRegisterList;
2205    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2206             contains(Regs.front().first))
2207      Kind = k_SPRRegisterList;
2208
2209    ARMOperand *Op = new ARMOperand(Kind);
2210    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2211           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2212      Op->Registers.push_back(I->first);
2213    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2214    Op->StartLoc = StartLoc;
2215    Op->EndLoc = EndLoc;
2216    return Op;
2217  }
2218
2219  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2220                                      bool isDoubleSpaced, SMLoc S, SMLoc E) {
2221    ARMOperand *Op = new ARMOperand(k_VectorList);
2222    Op->VectorList.RegNum = RegNum;
2223    Op->VectorList.Count = Count;
2224    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2225    Op->StartLoc = S;
2226    Op->EndLoc = E;
2227    return Op;
2228  }
2229
2230  static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2231                                              bool isDoubleSpaced,
2232                                              SMLoc S, SMLoc E) {
2233    ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2234    Op->VectorList.RegNum = RegNum;
2235    Op->VectorList.Count = Count;
2236    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2237    Op->StartLoc = S;
2238    Op->EndLoc = E;
2239    return Op;
2240  }
2241
2242  static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2243                                             unsigned Index,
2244                                             bool isDoubleSpaced,
2245                                             SMLoc S, SMLoc E) {
2246    ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2247    Op->VectorList.RegNum = RegNum;
2248    Op->VectorList.Count = Count;
2249    Op->VectorList.LaneIndex = Index;
2250    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2251    Op->StartLoc = S;
2252    Op->EndLoc = E;
2253    return Op;
2254  }
2255
2256  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2257                                       MCContext &Ctx) {
2258    ARMOperand *Op = new ARMOperand(k_VectorIndex);
2259    Op->VectorIndex.Val = Idx;
2260    Op->StartLoc = S;
2261    Op->EndLoc = E;
2262    return Op;
2263  }
2264
2265  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2266    ARMOperand *Op = new ARMOperand(k_Immediate);
2267    Op->Imm.Val = Val;
2268    Op->StartLoc = S;
2269    Op->EndLoc = E;
2270    return Op;
2271  }
2272
2273  static ARMOperand *CreateMem(unsigned BaseRegNum,
2274                               const MCConstantExpr *OffsetImm,
2275                               unsigned OffsetRegNum,
2276                               ARM_AM::ShiftOpc ShiftType,
2277                               unsigned ShiftImm,
2278                               unsigned Alignment,
2279                               bool isNegative,
2280                               SMLoc S, SMLoc E) {
2281    ARMOperand *Op = new ARMOperand(k_Memory);
2282    Op->Memory.BaseRegNum = BaseRegNum;
2283    Op->Memory.OffsetImm = OffsetImm;
2284    Op->Memory.OffsetRegNum = OffsetRegNum;
2285    Op->Memory.ShiftType = ShiftType;
2286    Op->Memory.ShiftImm = ShiftImm;
2287    Op->Memory.Alignment = Alignment;
2288    Op->Memory.isNegative = isNegative;
2289    Op->StartLoc = S;
2290    Op->EndLoc = E;
2291    return Op;
2292  }
2293
2294  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2295                                      ARM_AM::ShiftOpc ShiftTy,
2296                                      unsigned ShiftImm,
2297                                      SMLoc S, SMLoc E) {
2298    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2299    Op->PostIdxReg.RegNum = RegNum;
2300    Op->PostIdxReg.isAdd = isAdd;
2301    Op->PostIdxReg.ShiftTy = ShiftTy;
2302    Op->PostIdxReg.ShiftImm = ShiftImm;
2303    Op->StartLoc = S;
2304    Op->EndLoc = E;
2305    return Op;
2306  }
2307
2308  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2309    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2310    Op->MBOpt.Val = Opt;
2311    Op->StartLoc = S;
2312    Op->EndLoc = S;
2313    return Op;
2314  }
2315
2316  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2317    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2318    Op->IFlags.Val = IFlags;
2319    Op->StartLoc = S;
2320    Op->EndLoc = S;
2321    return Op;
2322  }
2323
2324  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2325    ARMOperand *Op = new ARMOperand(k_MSRMask);
2326    Op->MMask.Val = MMask;
2327    Op->StartLoc = S;
2328    Op->EndLoc = S;
2329    return Op;
2330  }
2331};
2332
2333} // end anonymous namespace.
2334
2335void ARMOperand::print(raw_ostream &OS) const {
2336  switch (Kind) {
2337  case k_CondCode:
2338    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2339    break;
2340  case k_CCOut:
2341    OS << "<ccout " << getReg() << ">";
2342    break;
2343  case k_ITCondMask: {
2344    static const char *const MaskStr[] = {
2345      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2346      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2347    };
2348    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2349    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2350    break;
2351  }
2352  case k_CoprocNum:
2353    OS << "<coprocessor number: " << getCoproc() << ">";
2354    break;
2355  case k_CoprocReg:
2356    OS << "<coprocessor register: " << getCoproc() << ">";
2357    break;
2358  case k_CoprocOption:
2359    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2360    break;
2361  case k_MSRMask:
2362    OS << "<mask: " << getMSRMask() << ">";
2363    break;
2364  case k_Immediate:
2365    getImm()->print(OS);
2366    break;
2367  case k_MemBarrierOpt:
2368    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2369    break;
2370  case k_Memory:
2371    OS << "<memory "
2372       << " base:" << Memory.BaseRegNum;
2373    OS << ">";
2374    break;
2375  case k_PostIndexRegister:
2376    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2377       << PostIdxReg.RegNum;
2378    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2379      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2380         << PostIdxReg.ShiftImm;
2381    OS << ">";
2382    break;
2383  case k_ProcIFlags: {
2384    OS << "<ARM_PROC::";
2385    unsigned IFlags = getProcIFlags();
2386    for (int i=2; i >= 0; --i)
2387      if (IFlags & (1 << i))
2388        OS << ARM_PROC::IFlagsToString(1 << i);
2389    OS << ">";
2390    break;
2391  }
2392  case k_Register:
2393    OS << "<register " << getReg() << ">";
2394    break;
2395  case k_ShifterImmediate:
2396    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2397       << " #" << ShifterImm.Imm << ">";
2398    break;
2399  case k_ShiftedRegister:
2400    OS << "<so_reg_reg "
2401       << RegShiftedReg.SrcReg << " "
2402       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2403       << " " << RegShiftedReg.ShiftReg << ">";
2404    break;
2405  case k_ShiftedImmediate:
2406    OS << "<so_reg_imm "
2407       << RegShiftedImm.SrcReg << " "
2408       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2409       << " #" << RegShiftedImm.ShiftImm << ">";
2410    break;
2411  case k_RotateImmediate:
2412    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2413    break;
2414  case k_BitfieldDescriptor:
2415    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2416       << ", width: " << Bitfield.Width << ">";
2417    break;
2418  case k_RegisterList:
2419  case k_DPRRegisterList:
2420  case k_SPRRegisterList: {
2421    OS << "<register_list ";
2422
2423    const SmallVectorImpl<unsigned> &RegList = getRegList();
2424    for (SmallVectorImpl<unsigned>::const_iterator
2425           I = RegList.begin(), E = RegList.end(); I != E; ) {
2426      OS << *I;
2427      if (++I < E) OS << ", ";
2428    }
2429
2430    OS << ">";
2431    break;
2432  }
2433  case k_VectorList:
2434    OS << "<vector_list " << VectorList.Count << " * "
2435       << VectorList.RegNum << ">";
2436    break;
2437  case k_VectorListAllLanes:
2438    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2439       << VectorList.RegNum << ">";
2440    break;
2441  case k_VectorListIndexed:
2442    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2443       << VectorList.Count << " * " << VectorList.RegNum << ">";
2444    break;
2445  case k_Token:
2446    OS << "'" << getToken() << "'";
2447    break;
2448  case k_VectorIndex:
2449    OS << "<vectorindex " << getVectorIndex() << ">";
2450    break;
2451  }
2452}
2453
2454/// @name Auto-generated Match Functions
2455/// {
2456
2457static unsigned MatchRegisterName(StringRef Name);
2458
2459/// }
2460
2461bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2462                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2463  StartLoc = Parser.getTok().getLoc();
2464  EndLoc = Parser.getTok().getEndLoc();
2465  RegNo = tryParseRegister();
2466
2467  return (RegNo == (unsigned)-1);
2468}
2469
2470/// Try to parse a register name.  The token must be an Identifier when called,
2471/// and if it is a register name the token is eaten and the register number is
2472/// returned.  Otherwise return -1.
2473///
2474int ARMAsmParser::tryParseRegister() {
2475  const AsmToken &Tok = Parser.getTok();
2476  if (Tok.isNot(AsmToken::Identifier)) return -1;
2477
2478  std::string lowerCase = Tok.getString().lower();
2479  unsigned RegNum = MatchRegisterName(lowerCase);
2480  if (!RegNum) {
2481    RegNum = StringSwitch<unsigned>(lowerCase)
2482      .Case("r13", ARM::SP)
2483      .Case("r14", ARM::LR)
2484      .Case("r15", ARM::PC)
2485      .Case("ip", ARM::R12)
2486      // Additional register name aliases for 'gas' compatibility.
2487      .Case("a1", ARM::R0)
2488      .Case("a2", ARM::R1)
2489      .Case("a3", ARM::R2)
2490      .Case("a4", ARM::R3)
2491      .Case("v1", ARM::R4)
2492      .Case("v2", ARM::R5)
2493      .Case("v3", ARM::R6)
2494      .Case("v4", ARM::R7)
2495      .Case("v5", ARM::R8)
2496      .Case("v6", ARM::R9)
2497      .Case("v7", ARM::R10)
2498      .Case("v8", ARM::R11)
2499      .Case("sb", ARM::R9)
2500      .Case("sl", ARM::R10)
2501      .Case("fp", ARM::R11)
2502      .Default(0);
2503  }
2504  if (!RegNum) {
2505    // Check for aliases registered via .req. Canonicalize to lower case.
2506    // That's more consistent since register names are case insensitive, and
2507    // it's how the original entry was passed in from MC/MCParser/AsmParser.
2508    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2509    // If no match, return failure.
2510    if (Entry == RegisterReqs.end())
2511      return -1;
2512    Parser.Lex(); // Eat identifier token.
2513    return Entry->getValue();
2514  }
2515
2516  Parser.Lex(); // Eat identifier token.
2517
2518  return RegNum;
2519}
2520
2521// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2522// If a recoverable error occurs, return 1. If an irrecoverable error
2523// occurs, return -1. An irrecoverable error is one where tokens have been
2524// consumed in the process of trying to parse the shifter (i.e., when it is
2525// indeed a shifter operand, but malformed).
2526int ARMAsmParser::tryParseShiftRegister(
2527                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2528  SMLoc S = Parser.getTok().getLoc();
2529  const AsmToken &Tok = Parser.getTok();
2530  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2531
2532  std::string lowerCase = Tok.getString().lower();
2533  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2534      .Case("asl", ARM_AM::lsl)
2535      .Case("lsl", ARM_AM::lsl)
2536      .Case("lsr", ARM_AM::lsr)
2537      .Case("asr", ARM_AM::asr)
2538      .Case("ror", ARM_AM::ror)
2539      .Case("rrx", ARM_AM::rrx)
2540      .Default(ARM_AM::no_shift);
2541
2542  if (ShiftTy == ARM_AM::no_shift)
2543    return 1;
2544
2545  Parser.Lex(); // Eat the operator.
2546
2547  // The source register for the shift has already been added to the
2548  // operand list, so we need to pop it off and combine it into the shifted
2549  // register operand instead.
2550  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2551  if (!PrevOp->isReg())
2552    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2553  int SrcReg = PrevOp->getReg();
2554
2555  SMLoc EndLoc;
2556  int64_t Imm = 0;
2557  int ShiftReg = 0;
2558  if (ShiftTy == ARM_AM::rrx) {
2559    // RRX Doesn't have an explicit shift amount. The encoder expects
2560    // the shift register to be the same as the source register. Seems odd,
2561    // but OK.
2562    ShiftReg = SrcReg;
2563  } else {
2564    // Figure out if this is shifted by a constant or a register (for non-RRX).
2565    if (Parser.getTok().is(AsmToken::Hash) ||
2566        Parser.getTok().is(AsmToken::Dollar)) {
2567      Parser.Lex(); // Eat hash.
2568      SMLoc ImmLoc = Parser.getTok().getLoc();
2569      const MCExpr *ShiftExpr = 0;
2570      if (getParser().ParseExpression(ShiftExpr, EndLoc)) {
2571        Error(ImmLoc, "invalid immediate shift value");
2572        return -1;
2573      }
2574      // The expression must be evaluatable as an immediate.
2575      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2576      if (!CE) {
2577        Error(ImmLoc, "invalid immediate shift value");
2578        return -1;
2579      }
2580      // Range check the immediate.
2581      // lsl, ror: 0 <= imm <= 31
2582      // lsr, asr: 0 <= imm <= 32
2583      Imm = CE->getValue();
2584      if (Imm < 0 ||
2585          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2586          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2587        Error(ImmLoc, "immediate shift value out of range");
2588        return -1;
2589      }
2590      // shift by zero is a nop. Always send it through as lsl.
2591      // ('as' compatibility)
2592      if (Imm == 0)
2593        ShiftTy = ARM_AM::lsl;
2594    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2595      SMLoc L = Parser.getTok().getLoc();
2596      EndLoc = Parser.getTok().getEndLoc();
2597      ShiftReg = tryParseRegister();
2598      if (ShiftReg == -1) {
2599        Error (L, "expected immediate or register in shift operand");
2600        return -1;
2601      }
2602    } else {
2603      Error (Parser.getTok().getLoc(),
2604                    "expected immediate or register in shift operand");
2605      return -1;
2606    }
2607  }
2608
2609  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2610    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2611                                                         ShiftReg, Imm,
2612                                                         S, EndLoc));
2613  else
2614    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2615                                                          S, EndLoc));
2616
2617  return 0;
2618}
2619
2620
2621/// Try to parse a register name.  The token must be an Identifier when called.
2622/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2623/// if there is a "writeback". 'true' if it's not a register.
2624///
2625/// TODO this is likely to change to allow different register types and or to
2626/// parse for a specific register type.
2627bool ARMAsmParser::
2628tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2629  const AsmToken &RegTok = Parser.getTok();
2630  int RegNo = tryParseRegister();
2631  if (RegNo == -1)
2632    return true;
2633
2634  Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2635                                           RegTok.getEndLoc()));
2636
2637  const AsmToken &ExclaimTok = Parser.getTok();
2638  if (ExclaimTok.is(AsmToken::Exclaim)) {
2639    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2640                                               ExclaimTok.getLoc()));
2641    Parser.Lex(); // Eat exclaim token
2642    return false;
2643  }
2644
2645  // Also check for an index operand. This is only legal for vector registers,
2646  // but that'll get caught OK in operand matching, so we don't need to
2647  // explicitly filter everything else out here.
2648  if (Parser.getTok().is(AsmToken::LBrac)) {
2649    SMLoc SIdx = Parser.getTok().getLoc();
2650    Parser.Lex(); // Eat left bracket token.
2651
2652    const MCExpr *ImmVal;
2653    if (getParser().ParseExpression(ImmVal))
2654      return true;
2655    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2656    if (!MCE)
2657      return TokError("immediate value expected for vector index");
2658
2659    if (Parser.getTok().isNot(AsmToken::RBrac))
2660      return Error(Parser.getTok().getLoc(), "']' expected");
2661
2662    SMLoc E = Parser.getTok().getEndLoc();
2663    Parser.Lex(); // Eat right bracket token.
2664
2665    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2666                                                     SIdx, E,
2667                                                     getContext()));
2668  }
2669
2670  return false;
2671}
2672
2673/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2674/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2675/// "c5", ...
2676static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2677  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2678  // but efficient.
2679  switch (Name.size()) {
2680  default: return -1;
2681  case 2:
2682    if (Name[0] != CoprocOp)
2683      return -1;
2684    switch (Name[1]) {
2685    default:  return -1;
2686    case '0': return 0;
2687    case '1': return 1;
2688    case '2': return 2;
2689    case '3': return 3;
2690    case '4': return 4;
2691    case '5': return 5;
2692    case '6': return 6;
2693    case '7': return 7;
2694    case '8': return 8;
2695    case '9': return 9;
2696    }
2697  case 3:
2698    if (Name[0] != CoprocOp || Name[1] != '1')
2699      return -1;
2700    switch (Name[2]) {
2701    default:  return -1;
2702    case '0': return 10;
2703    case '1': return 11;
2704    case '2': return 12;
2705    case '3': return 13;
2706    case '4': return 14;
2707    case '5': return 15;
2708    }
2709  }
2710}
2711
2712/// parseITCondCode - Try to parse a condition code for an IT instruction.
2713ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2714parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2715  SMLoc S = Parser.getTok().getLoc();
2716  const AsmToken &Tok = Parser.getTok();
2717  if (!Tok.is(AsmToken::Identifier))
2718    return MatchOperand_NoMatch;
2719  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2720    .Case("eq", ARMCC::EQ)
2721    .Case("ne", ARMCC::NE)
2722    .Case("hs", ARMCC::HS)
2723    .Case("cs", ARMCC::HS)
2724    .Case("lo", ARMCC::LO)
2725    .Case("cc", ARMCC::LO)
2726    .Case("mi", ARMCC::MI)
2727    .Case("pl", ARMCC::PL)
2728    .Case("vs", ARMCC::VS)
2729    .Case("vc", ARMCC::VC)
2730    .Case("hi", ARMCC::HI)
2731    .Case("ls", ARMCC::LS)
2732    .Case("ge", ARMCC::GE)
2733    .Case("lt", ARMCC::LT)
2734    .Case("gt", ARMCC::GT)
2735    .Case("le", ARMCC::LE)
2736    .Case("al", ARMCC::AL)
2737    .Default(~0U);
2738  if (CC == ~0U)
2739    return MatchOperand_NoMatch;
2740  Parser.Lex(); // Eat the token.
2741
2742  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2743
2744  return MatchOperand_Success;
2745}
2746
2747/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2748/// token must be an Identifier when called, and if it is a coprocessor
2749/// number, the token is eaten and the operand is added to the operand list.
2750ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2751parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2752  SMLoc S = Parser.getTok().getLoc();
2753  const AsmToken &Tok = Parser.getTok();
2754  if (Tok.isNot(AsmToken::Identifier))
2755    return MatchOperand_NoMatch;
2756
2757  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2758  if (Num == -1)
2759    return MatchOperand_NoMatch;
2760
2761  Parser.Lex(); // Eat identifier token.
2762  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2763  return MatchOperand_Success;
2764}
2765
2766/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2767/// token must be an Identifier when called, and if it is a coprocessor
2768/// number, the token is eaten and the operand is added to the operand list.
2769ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2770parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2771  SMLoc S = Parser.getTok().getLoc();
2772  const AsmToken &Tok = Parser.getTok();
2773  if (Tok.isNot(AsmToken::Identifier))
2774    return MatchOperand_NoMatch;
2775
2776  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2777  if (Reg == -1)
2778    return MatchOperand_NoMatch;
2779
2780  Parser.Lex(); // Eat identifier token.
2781  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2782  return MatchOperand_Success;
2783}
2784
2785/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2786/// coproc_option : '{' imm0_255 '}'
2787ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2788parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2789  SMLoc S = Parser.getTok().getLoc();
2790
2791  // If this isn't a '{', this isn't a coprocessor immediate operand.
2792  if (Parser.getTok().isNot(AsmToken::LCurly))
2793    return MatchOperand_NoMatch;
2794  Parser.Lex(); // Eat the '{'
2795
2796  const MCExpr *Expr;
2797  SMLoc Loc = Parser.getTok().getLoc();
2798  if (getParser().ParseExpression(Expr)) {
2799    Error(Loc, "illegal expression");
2800    return MatchOperand_ParseFail;
2801  }
2802  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2803  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2804    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2805    return MatchOperand_ParseFail;
2806  }
2807  int Val = CE->getValue();
2808
2809  // Check for and consume the closing '}'
2810  if (Parser.getTok().isNot(AsmToken::RCurly))
2811    return MatchOperand_ParseFail;
2812  SMLoc E = Parser.getTok().getEndLoc();
2813  Parser.Lex(); // Eat the '}'
2814
2815  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2816  return MatchOperand_Success;
2817}
2818
2819// For register list parsing, we need to map from raw GPR register numbering
2820// to the enumeration values. The enumeration values aren't sorted by
2821// register number due to our using "sp", "lr" and "pc" as canonical names.
2822static unsigned getNextRegister(unsigned Reg) {
2823  // If this is a GPR, we need to do it manually, otherwise we can rely
2824  // on the sort ordering of the enumeration since the other reg-classes
2825  // are sane.
2826  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2827    return Reg + 1;
2828  switch(Reg) {
2829  default: llvm_unreachable("Invalid GPR number!");
2830  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2831  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2832  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2833  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2834  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2835  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2836  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2837  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2838  }
2839}
2840
2841// Return the low-subreg of a given Q register.
2842static unsigned getDRegFromQReg(unsigned QReg) {
2843  switch (QReg) {
2844  default: llvm_unreachable("expected a Q register!");
2845  case ARM::Q0:  return ARM::D0;
2846  case ARM::Q1:  return ARM::D2;
2847  case ARM::Q2:  return ARM::D4;
2848  case ARM::Q3:  return ARM::D6;
2849  case ARM::Q4:  return ARM::D8;
2850  case ARM::Q5:  return ARM::D10;
2851  case ARM::Q6:  return ARM::D12;
2852  case ARM::Q7:  return ARM::D14;
2853  case ARM::Q8:  return ARM::D16;
2854  case ARM::Q9:  return ARM::D18;
2855  case ARM::Q10: return ARM::D20;
2856  case ARM::Q11: return ARM::D22;
2857  case ARM::Q12: return ARM::D24;
2858  case ARM::Q13: return ARM::D26;
2859  case ARM::Q14: return ARM::D28;
2860  case ARM::Q15: return ARM::D30;
2861  }
2862}
2863
2864/// Parse a register list.
2865bool ARMAsmParser::
2866parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2867  assert(Parser.getTok().is(AsmToken::LCurly) &&
2868         "Token is not a Left Curly Brace");
2869  SMLoc S = Parser.getTok().getLoc();
2870  Parser.Lex(); // Eat '{' token.
2871  SMLoc RegLoc = Parser.getTok().getLoc();
2872
2873  // Check the first register in the list to see what register class
2874  // this is a list of.
2875  int Reg = tryParseRegister();
2876  if (Reg == -1)
2877    return Error(RegLoc, "register expected");
2878
2879  // The reglist instructions have at most 16 registers, so reserve
2880  // space for that many.
2881  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2882
2883  // Allow Q regs and just interpret them as the two D sub-registers.
2884  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2885    Reg = getDRegFromQReg(Reg);
2886    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2887    ++Reg;
2888  }
2889  const MCRegisterClass *RC;
2890  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2891    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2892  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2893    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2894  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2895    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2896  else
2897    return Error(RegLoc, "invalid register in register list");
2898
2899  // Store the register.
2900  Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2901
2902  // This starts immediately after the first register token in the list,
2903  // so we can see either a comma or a minus (range separator) as a legal
2904  // next token.
2905  while (Parser.getTok().is(AsmToken::Comma) ||
2906         Parser.getTok().is(AsmToken::Minus)) {
2907    if (Parser.getTok().is(AsmToken::Minus)) {
2908      Parser.Lex(); // Eat the minus.
2909      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
2910      int EndReg = tryParseRegister();
2911      if (EndReg == -1)
2912        return Error(AfterMinusLoc, "register expected");
2913      // Allow Q regs and just interpret them as the two D sub-registers.
2914      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2915        EndReg = getDRegFromQReg(EndReg) + 1;
2916      // If the register is the same as the start reg, there's nothing
2917      // more to do.
2918      if (Reg == EndReg)
2919        continue;
2920      // The register must be in the same register class as the first.
2921      if (!RC->contains(EndReg))
2922        return Error(AfterMinusLoc, "invalid register in register list");
2923      // Ranges must go from low to high.
2924      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
2925        return Error(AfterMinusLoc, "bad range in register list");
2926
2927      // Add all the registers in the range to the register list.
2928      while (Reg != EndReg) {
2929        Reg = getNextRegister(Reg);
2930        Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2931      }
2932      continue;
2933    }
2934    Parser.Lex(); // Eat the comma.
2935    RegLoc = Parser.getTok().getLoc();
2936    int OldReg = Reg;
2937    const AsmToken RegTok = Parser.getTok();
2938    Reg = tryParseRegister();
2939    if (Reg == -1)
2940      return Error(RegLoc, "register expected");
2941    // Allow Q regs and just interpret them as the two D sub-registers.
2942    bool isQReg = false;
2943    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2944      Reg = getDRegFromQReg(Reg);
2945      isQReg = true;
2946    }
2947    // The register must be in the same register class as the first.
2948    if (!RC->contains(Reg))
2949      return Error(RegLoc, "invalid register in register list");
2950    // List must be monotonically increasing.
2951    if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
2952      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2953        Warning(RegLoc, "register list not in ascending order");
2954      else
2955        return Error(RegLoc, "register list not in ascending order");
2956    }
2957    if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
2958      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2959              ") in register list");
2960      continue;
2961    }
2962    // VFP register lists must also be contiguous.
2963    // It's OK to use the enumeration values directly here rather, as the
2964    // VFP register classes have the enum sorted properly.
2965    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2966        Reg != OldReg + 1)
2967      return Error(RegLoc, "non-contiguous register range");
2968    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2969    if (isQReg)
2970      Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2971  }
2972
2973  if (Parser.getTok().isNot(AsmToken::RCurly))
2974    return Error(Parser.getTok().getLoc(), "'}' expected");
2975  SMLoc E = Parser.getTok().getEndLoc();
2976  Parser.Lex(); // Eat '}' token.
2977
2978  // Push the register list operand.
2979  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2980
2981  // The ARM system instruction variants for LDM/STM have a '^' token here.
2982  if (Parser.getTok().is(AsmToken::Caret)) {
2983    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2984    Parser.Lex(); // Eat '^' token.
2985  }
2986
2987  return false;
2988}
2989
2990// Helper function to parse the lane index for vector lists.
2991ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2992parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
2993  Index = 0; // Always return a defined index value.
2994  if (Parser.getTok().is(AsmToken::LBrac)) {
2995    Parser.Lex(); // Eat the '['.
2996    if (Parser.getTok().is(AsmToken::RBrac)) {
2997      // "Dn[]" is the 'all lanes' syntax.
2998      LaneKind = AllLanes;
2999      EndLoc = Parser.getTok().getEndLoc();
3000      Parser.Lex(); // Eat the ']'.
3001      return MatchOperand_Success;
3002    }
3003
3004    // There's an optional '#' token here. Normally there wouldn't be, but
3005    // inline assemble puts one in, and it's friendly to accept that.
3006    if (Parser.getTok().is(AsmToken::Hash))
3007      Parser.Lex(); // Eat the '#'
3008
3009    const MCExpr *LaneIndex;
3010    SMLoc Loc = Parser.getTok().getLoc();
3011    if (getParser().ParseExpression(LaneIndex)) {
3012      Error(Loc, "illegal expression");
3013      return MatchOperand_ParseFail;
3014    }
3015    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3016    if (!CE) {
3017      Error(Loc, "lane index must be empty or an integer");
3018      return MatchOperand_ParseFail;
3019    }
3020    if (Parser.getTok().isNot(AsmToken::RBrac)) {
3021      Error(Parser.getTok().getLoc(), "']' expected");
3022      return MatchOperand_ParseFail;
3023    }
3024    EndLoc = Parser.getTok().getEndLoc();
3025    Parser.Lex(); // Eat the ']'.
3026    int64_t Val = CE->getValue();
3027
3028    // FIXME: Make this range check context sensitive for .8, .16, .32.
3029    if (Val < 0 || Val > 7) {
3030      Error(Parser.getTok().getLoc(), "lane index out of range");
3031      return MatchOperand_ParseFail;
3032    }
3033    Index = Val;
3034    LaneKind = IndexedLane;
3035    return MatchOperand_Success;
3036  }
3037  LaneKind = NoLanes;
3038  return MatchOperand_Success;
3039}
3040
3041// parse a vector register list
3042ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3043parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3044  VectorLaneTy LaneKind;
3045  unsigned LaneIndex;
3046  SMLoc S = Parser.getTok().getLoc();
3047  // As an extension (to match gas), support a plain D register or Q register
3048  // (without encosing curly braces) as a single or double entry list,
3049  // respectively.
3050  if (Parser.getTok().is(AsmToken::Identifier)) {
3051    SMLoc E = Parser.getTok().getEndLoc();
3052    int Reg = tryParseRegister();
3053    if (Reg == -1)
3054      return MatchOperand_NoMatch;
3055    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3056      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3057      if (Res != MatchOperand_Success)
3058        return Res;
3059      switch (LaneKind) {
3060      case NoLanes:
3061        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3062        break;
3063      case AllLanes:
3064        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3065                                                                S, E));
3066        break;
3067      case IndexedLane:
3068        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3069                                                               LaneIndex,
3070                                                               false, S, E));
3071        break;
3072      }
3073      return MatchOperand_Success;
3074    }
3075    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3076      Reg = getDRegFromQReg(Reg);
3077      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3078      if (Res != MatchOperand_Success)
3079        return Res;
3080      switch (LaneKind) {
3081      case NoLanes:
3082        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3083                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3084        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3085        break;
3086      case AllLanes:
3087        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3088                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3089        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3090                                                                S, E));
3091        break;
3092      case IndexedLane:
3093        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3094                                                               LaneIndex,
3095                                                               false, S, E));
3096        break;
3097      }
3098      return MatchOperand_Success;
3099    }
3100    Error(S, "vector register expected");
3101    return MatchOperand_ParseFail;
3102  }
3103
3104  if (Parser.getTok().isNot(AsmToken::LCurly))
3105    return MatchOperand_NoMatch;
3106
3107  Parser.Lex(); // Eat '{' token.
3108  SMLoc RegLoc = Parser.getTok().getLoc();
3109
3110  int Reg = tryParseRegister();
3111  if (Reg == -1) {
3112    Error(RegLoc, "register expected");
3113    return MatchOperand_ParseFail;
3114  }
3115  unsigned Count = 1;
3116  int Spacing = 0;
3117  unsigned FirstReg = Reg;
3118  // The list is of D registers, but we also allow Q regs and just interpret
3119  // them as the two D sub-registers.
3120  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3121    FirstReg = Reg = getDRegFromQReg(Reg);
3122    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3123                 // it's ambiguous with four-register single spaced.
3124    ++Reg;
3125    ++Count;
3126  }
3127
3128  SMLoc E;
3129  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3130    return MatchOperand_ParseFail;
3131
3132  while (Parser.getTok().is(AsmToken::Comma) ||
3133         Parser.getTok().is(AsmToken::Minus)) {
3134    if (Parser.getTok().is(AsmToken::Minus)) {
3135      if (!Spacing)
3136        Spacing = 1; // Register range implies a single spaced list.
3137      else if (Spacing == 2) {
3138        Error(Parser.getTok().getLoc(),
3139              "sequential registers in double spaced list");
3140        return MatchOperand_ParseFail;
3141      }
3142      Parser.Lex(); // Eat the minus.
3143      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3144      int EndReg = tryParseRegister();
3145      if (EndReg == -1) {
3146        Error(AfterMinusLoc, "register expected");
3147        return MatchOperand_ParseFail;
3148      }
3149      // Allow Q regs and just interpret them as the two D sub-registers.
3150      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3151        EndReg = getDRegFromQReg(EndReg) + 1;
3152      // If the register is the same as the start reg, there's nothing
3153      // more to do.
3154      if (Reg == EndReg)
3155        continue;
3156      // The register must be in the same register class as the first.
3157      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3158        Error(AfterMinusLoc, "invalid register in register list");
3159        return MatchOperand_ParseFail;
3160      }
3161      // Ranges must go from low to high.
3162      if (Reg > EndReg) {
3163        Error(AfterMinusLoc, "bad range in register list");
3164        return MatchOperand_ParseFail;
3165      }
3166      // Parse the lane specifier if present.
3167      VectorLaneTy NextLaneKind;
3168      unsigned NextLaneIndex;
3169      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3170          MatchOperand_Success)
3171        return MatchOperand_ParseFail;
3172      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3173        Error(AfterMinusLoc, "mismatched lane index in register list");
3174        return MatchOperand_ParseFail;
3175      }
3176
3177      // Add all the registers in the range to the register list.
3178      Count += EndReg - Reg;
3179      Reg = EndReg;
3180      continue;
3181    }
3182    Parser.Lex(); // Eat the comma.
3183    RegLoc = Parser.getTok().getLoc();
3184    int OldReg = Reg;
3185    Reg = tryParseRegister();
3186    if (Reg == -1) {
3187      Error(RegLoc, "register expected");
3188      return MatchOperand_ParseFail;
3189    }
3190    // vector register lists must be contiguous.
3191    // It's OK to use the enumeration values directly here rather, as the
3192    // VFP register classes have the enum sorted properly.
3193    //
3194    // The list is of D registers, but we also allow Q regs and just interpret
3195    // them as the two D sub-registers.
3196    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3197      if (!Spacing)
3198        Spacing = 1; // Register range implies a single spaced list.
3199      else if (Spacing == 2) {
3200        Error(RegLoc,
3201              "invalid register in double-spaced list (must be 'D' register')");
3202        return MatchOperand_ParseFail;
3203      }
3204      Reg = getDRegFromQReg(Reg);
3205      if (Reg != OldReg + 1) {
3206        Error(RegLoc, "non-contiguous register range");
3207        return MatchOperand_ParseFail;
3208      }
3209      ++Reg;
3210      Count += 2;
3211      // Parse the lane specifier if present.
3212      VectorLaneTy NextLaneKind;
3213      unsigned NextLaneIndex;
3214      SMLoc LaneLoc = Parser.getTok().getLoc();
3215      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3216          MatchOperand_Success)
3217        return MatchOperand_ParseFail;
3218      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3219        Error(LaneLoc, "mismatched lane index in register list");
3220        return MatchOperand_ParseFail;
3221      }
3222      continue;
3223    }
3224    // Normal D register.
3225    // Figure out the register spacing (single or double) of the list if
3226    // we don't know it already.
3227    if (!Spacing)
3228      Spacing = 1 + (Reg == OldReg + 2);
3229
3230    // Just check that it's contiguous and keep going.
3231    if (Reg != OldReg + Spacing) {
3232      Error(RegLoc, "non-contiguous register range");
3233      return MatchOperand_ParseFail;
3234    }
3235    ++Count;
3236    // Parse the lane specifier if present.
3237    VectorLaneTy NextLaneKind;
3238    unsigned NextLaneIndex;
3239    SMLoc EndLoc = Parser.getTok().getLoc();
3240    if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3241      return MatchOperand_ParseFail;
3242    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3243      Error(EndLoc, "mismatched lane index in register list");
3244      return MatchOperand_ParseFail;
3245    }
3246  }
3247
3248  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3249    Error(Parser.getTok().getLoc(), "'}' expected");
3250    return MatchOperand_ParseFail;
3251  }
3252  E = Parser.getTok().getEndLoc();
3253  Parser.Lex(); // Eat '}' token.
3254
3255  switch (LaneKind) {
3256  case NoLanes:
3257    // Two-register operands have been converted to the
3258    // composite register classes.
3259    if (Count == 2) {
3260      const MCRegisterClass *RC = (Spacing == 1) ?
3261        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3262        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3263      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3264    }
3265
3266    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3267                                                    (Spacing == 2), S, E));
3268    break;
3269  case AllLanes:
3270    // Two-register operands have been converted to the
3271    // composite register classes.
3272    if (Count == 2) {
3273      const MCRegisterClass *RC = (Spacing == 1) ?
3274        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3275        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3276      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3277    }
3278    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3279                                                            (Spacing == 2),
3280                                                            S, E));
3281    break;
3282  case IndexedLane:
3283    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3284                                                           LaneIndex,
3285                                                           (Spacing == 2),
3286                                                           S, E));
3287    break;
3288  }
3289  return MatchOperand_Success;
3290}
3291
3292/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3293ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3294parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3295  SMLoc S = Parser.getTok().getLoc();
3296  const AsmToken &Tok = Parser.getTok();
3297  unsigned Opt;
3298
3299  if (Tok.is(AsmToken::Identifier)) {
3300    StringRef OptStr = Tok.getString();
3301
3302    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3303      .Case("sy",    ARM_MB::SY)
3304      .Case("st",    ARM_MB::ST)
3305      .Case("sh",    ARM_MB::ISH)
3306      .Case("ish",   ARM_MB::ISH)
3307      .Case("shst",  ARM_MB::ISHST)
3308      .Case("ishst", ARM_MB::ISHST)
3309      .Case("nsh",   ARM_MB::NSH)
3310      .Case("un",    ARM_MB::NSH)
3311      .Case("nshst", ARM_MB::NSHST)
3312      .Case("unst",  ARM_MB::NSHST)
3313      .Case("osh",   ARM_MB::OSH)
3314      .Case("oshst", ARM_MB::OSHST)
3315      .Default(~0U);
3316
3317    if (Opt == ~0U)
3318      return MatchOperand_NoMatch;
3319
3320    Parser.Lex(); // Eat identifier token.
3321  } else if (Tok.is(AsmToken::Hash) ||
3322             Tok.is(AsmToken::Dollar) ||
3323             Tok.is(AsmToken::Integer)) {
3324    if (Parser.getTok().isNot(AsmToken::Integer))
3325      Parser.Lex(); // Eat the '#'.
3326    SMLoc Loc = Parser.getTok().getLoc();
3327
3328    const MCExpr *MemBarrierID;
3329    if (getParser().ParseExpression(MemBarrierID)) {
3330      Error(Loc, "illegal expression");
3331      return MatchOperand_ParseFail;
3332    }
3333
3334    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3335    if (!CE) {
3336      Error(Loc, "constant expression expected");
3337      return MatchOperand_ParseFail;
3338    }
3339
3340    int Val = CE->getValue();
3341    if (Val & ~0xf) {
3342      Error(Loc, "immediate value out of range");
3343      return MatchOperand_ParseFail;
3344    }
3345
3346    Opt = ARM_MB::RESERVED_0 + Val;
3347  } else
3348    return MatchOperand_ParseFail;
3349
3350  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3351  return MatchOperand_Success;
3352}
3353
3354/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3355ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3356parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3357  SMLoc S = Parser.getTok().getLoc();
3358  const AsmToken &Tok = Parser.getTok();
3359  if (!Tok.is(AsmToken::Identifier))
3360    return MatchOperand_NoMatch;
3361  StringRef IFlagsStr = Tok.getString();
3362
3363  // An iflags string of "none" is interpreted to mean that none of the AIF
3364  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3365  unsigned IFlags = 0;
3366  if (IFlagsStr != "none") {
3367        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3368      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3369        .Case("a", ARM_PROC::A)
3370        .Case("i", ARM_PROC::I)
3371        .Case("f", ARM_PROC::F)
3372        .Default(~0U);
3373
3374      // If some specific iflag is already set, it means that some letter is
3375      // present more than once, this is not acceptable.
3376      if (Flag == ~0U || (IFlags & Flag))
3377        return MatchOperand_NoMatch;
3378
3379      IFlags |= Flag;
3380    }
3381  }
3382
3383  Parser.Lex(); // Eat identifier token.
3384  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3385  return MatchOperand_Success;
3386}
3387
3388/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3389ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3390parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3391  SMLoc S = Parser.getTok().getLoc();
3392  const AsmToken &Tok = Parser.getTok();
3393  if (!Tok.is(AsmToken::Identifier))
3394    return MatchOperand_NoMatch;
3395  StringRef Mask = Tok.getString();
3396
3397  if (isMClass()) {
3398    // See ARMv6-M 10.1.1
3399    std::string Name = Mask.lower();
3400    unsigned FlagsVal = StringSwitch<unsigned>(Name)
3401      // Note: in the documentation:
3402      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3403      //  for MSR APSR_nzcvq.
3404      // but we do make it an alias here.  This is so to get the "mask encoding"
3405      // bits correct on MSR APSR writes.
3406      //
3407      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3408      // should really only be allowed when writing a special register.  Note
3409      // they get dropped in the MRS instruction reading a special register as
3410      // the SYSm field is only 8 bits.
3411      //
3412      // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3413      // includes the DSP extension but that is not checked.
3414      .Case("apsr", 0x800)
3415      .Case("apsr_nzcvq", 0x800)
3416      .Case("apsr_g", 0x400)
3417      .Case("apsr_nzcvqg", 0xc00)
3418      .Case("iapsr", 0x801)
3419      .Case("iapsr_nzcvq", 0x801)
3420      .Case("iapsr_g", 0x401)
3421      .Case("iapsr_nzcvqg", 0xc01)
3422      .Case("eapsr", 0x802)
3423      .Case("eapsr_nzcvq", 0x802)
3424      .Case("eapsr_g", 0x402)
3425      .Case("eapsr_nzcvqg", 0xc02)
3426      .Case("xpsr", 0x803)
3427      .Case("xpsr_nzcvq", 0x803)
3428      .Case("xpsr_g", 0x403)
3429      .Case("xpsr_nzcvqg", 0xc03)
3430      .Case("ipsr", 0x805)
3431      .Case("epsr", 0x806)
3432      .Case("iepsr", 0x807)
3433      .Case("msp", 0x808)
3434      .Case("psp", 0x809)
3435      .Case("primask", 0x810)
3436      .Case("basepri", 0x811)
3437      .Case("basepri_max", 0x812)
3438      .Case("faultmask", 0x813)
3439      .Case("control", 0x814)
3440      .Default(~0U);
3441
3442    if (FlagsVal == ~0U)
3443      return MatchOperand_NoMatch;
3444
3445    if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3446      // basepri, basepri_max and faultmask only valid for V7m.
3447      return MatchOperand_NoMatch;
3448
3449    Parser.Lex(); // Eat identifier token.
3450    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3451    return MatchOperand_Success;
3452  }
3453
3454  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3455  size_t Start = 0, Next = Mask.find('_');
3456  StringRef Flags = "";
3457  std::string SpecReg = Mask.slice(Start, Next).lower();
3458  if (Next != StringRef::npos)
3459    Flags = Mask.slice(Next+1, Mask.size());
3460
3461  // FlagsVal contains the complete mask:
3462  // 3-0: Mask
3463  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3464  unsigned FlagsVal = 0;
3465
3466  if (SpecReg == "apsr") {
3467    FlagsVal = StringSwitch<unsigned>(Flags)
3468    .Case("nzcvq",  0x8) // same as CPSR_f
3469    .Case("g",      0x4) // same as CPSR_s
3470    .Case("nzcvqg", 0xc) // same as CPSR_fs
3471    .Default(~0U);
3472
3473    if (FlagsVal == ~0U) {
3474      if (!Flags.empty())
3475        return MatchOperand_NoMatch;
3476      else
3477        FlagsVal = 8; // No flag
3478    }
3479  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3480    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3481    if (Flags == "all" || Flags == "")
3482      Flags = "fc";
3483    for (int i = 0, e = Flags.size(); i != e; ++i) {
3484      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3485      .Case("c", 1)
3486      .Case("x", 2)
3487      .Case("s", 4)
3488      .Case("f", 8)
3489      .Default(~0U);
3490
3491      // If some specific flag is already set, it means that some letter is
3492      // present more than once, this is not acceptable.
3493      if (FlagsVal == ~0U || (FlagsVal & Flag))
3494        return MatchOperand_NoMatch;
3495      FlagsVal |= Flag;
3496    }
3497  } else // No match for special register.
3498    return MatchOperand_NoMatch;
3499
3500  // Special register without flags is NOT equivalent to "fc" flags.
3501  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3502  // two lines would enable gas compatibility at the expense of breaking
3503  // round-tripping.
3504  //
3505  // if (!FlagsVal)
3506  //  FlagsVal = 0x9;
3507
3508  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3509  if (SpecReg == "spsr")
3510    FlagsVal |= 16;
3511
3512  Parser.Lex(); // Eat identifier token.
3513  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3514  return MatchOperand_Success;
3515}
3516
3517ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3518parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3519            int Low, int High) {
3520  const AsmToken &Tok = Parser.getTok();
3521  if (Tok.isNot(AsmToken::Identifier)) {
3522    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3523    return MatchOperand_ParseFail;
3524  }
3525  StringRef ShiftName = Tok.getString();
3526  std::string LowerOp = Op.lower();
3527  std::string UpperOp = Op.upper();
3528  if (ShiftName != LowerOp && ShiftName != UpperOp) {
3529    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3530    return MatchOperand_ParseFail;
3531  }
3532  Parser.Lex(); // Eat shift type token.
3533
3534  // There must be a '#' and a shift amount.
3535  if (Parser.getTok().isNot(AsmToken::Hash) &&
3536      Parser.getTok().isNot(AsmToken::Dollar)) {
3537    Error(Parser.getTok().getLoc(), "'#' expected");
3538    return MatchOperand_ParseFail;
3539  }
3540  Parser.Lex(); // Eat hash token.
3541
3542  const MCExpr *ShiftAmount;
3543  SMLoc Loc = Parser.getTok().getLoc();
3544  SMLoc EndLoc;
3545  if (getParser().ParseExpression(ShiftAmount, EndLoc)) {
3546    Error(Loc, "illegal expression");
3547    return MatchOperand_ParseFail;
3548  }
3549  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3550  if (!CE) {
3551    Error(Loc, "constant expression expected");
3552    return MatchOperand_ParseFail;
3553  }
3554  int Val = CE->getValue();
3555  if (Val < Low || Val > High) {
3556    Error(Loc, "immediate value out of range");
3557    return MatchOperand_ParseFail;
3558  }
3559
3560  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3561
3562  return MatchOperand_Success;
3563}
3564
3565ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3566parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3567  const AsmToken &Tok = Parser.getTok();
3568  SMLoc S = Tok.getLoc();
3569  if (Tok.isNot(AsmToken::Identifier)) {
3570    Error(S, "'be' or 'le' operand expected");
3571    return MatchOperand_ParseFail;
3572  }
3573  int Val = StringSwitch<int>(Tok.getString())
3574    .Case("be", 1)
3575    .Case("le", 0)
3576    .Default(-1);
3577  Parser.Lex(); // Eat the token.
3578
3579  if (Val == -1) {
3580    Error(S, "'be' or 'le' operand expected");
3581    return MatchOperand_ParseFail;
3582  }
3583  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3584                                                                  getContext()),
3585                                           S, Tok.getEndLoc()));
3586  return MatchOperand_Success;
3587}
3588
3589/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3590/// instructions. Legal values are:
3591///     lsl #n  'n' in [0,31]
3592///     asr #n  'n' in [1,32]
3593///             n == 32 encoded as n == 0.
3594ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3595parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3596  const AsmToken &Tok = Parser.getTok();
3597  SMLoc S = Tok.getLoc();
3598  if (Tok.isNot(AsmToken::Identifier)) {
3599    Error(S, "shift operator 'asr' or 'lsl' expected");
3600    return MatchOperand_ParseFail;
3601  }
3602  StringRef ShiftName = Tok.getString();
3603  bool isASR;
3604  if (ShiftName == "lsl" || ShiftName == "LSL")
3605    isASR = false;
3606  else if (ShiftName == "asr" || ShiftName == "ASR")
3607    isASR = true;
3608  else {
3609    Error(S, "shift operator 'asr' or 'lsl' expected");
3610    return MatchOperand_ParseFail;
3611  }
3612  Parser.Lex(); // Eat the operator.
3613
3614  // A '#' and a shift amount.
3615  if (Parser.getTok().isNot(AsmToken::Hash) &&
3616      Parser.getTok().isNot(AsmToken::Dollar)) {
3617    Error(Parser.getTok().getLoc(), "'#' expected");
3618    return MatchOperand_ParseFail;
3619  }
3620  Parser.Lex(); // Eat hash token.
3621  SMLoc ExLoc = Parser.getTok().getLoc();
3622
3623  const MCExpr *ShiftAmount;
3624  SMLoc EndLoc;
3625  if (getParser().ParseExpression(ShiftAmount, EndLoc)) {
3626    Error(ExLoc, "malformed shift expression");
3627    return MatchOperand_ParseFail;
3628  }
3629  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3630  if (!CE) {
3631    Error(ExLoc, "shift amount must be an immediate");
3632    return MatchOperand_ParseFail;
3633  }
3634
3635  int64_t Val = CE->getValue();
3636  if (isASR) {
3637    // Shift amount must be in [1,32]
3638    if (Val < 1 || Val > 32) {
3639      Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3640      return MatchOperand_ParseFail;
3641    }
3642    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3643    if (isThumb() && Val == 32) {
3644      Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3645      return MatchOperand_ParseFail;
3646    }
3647    if (Val == 32) Val = 0;
3648  } else {
3649    // Shift amount must be in [1,32]
3650    if (Val < 0 || Val > 31) {
3651      Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3652      return MatchOperand_ParseFail;
3653    }
3654  }
3655
3656  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3657
3658  return MatchOperand_Success;
3659}
3660
3661/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3662/// of instructions. Legal values are:
3663///     ror #n  'n' in {0, 8, 16, 24}
3664ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3665parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3666  const AsmToken &Tok = Parser.getTok();
3667  SMLoc S = Tok.getLoc();
3668  if (Tok.isNot(AsmToken::Identifier))
3669    return MatchOperand_NoMatch;
3670  StringRef ShiftName = Tok.getString();
3671  if (ShiftName != "ror" && ShiftName != "ROR")
3672    return MatchOperand_NoMatch;
3673  Parser.Lex(); // Eat the operator.
3674
3675  // A '#' and a rotate amount.
3676  if (Parser.getTok().isNot(AsmToken::Hash) &&
3677      Parser.getTok().isNot(AsmToken::Dollar)) {
3678    Error(Parser.getTok().getLoc(), "'#' expected");
3679    return MatchOperand_ParseFail;
3680  }
3681  Parser.Lex(); // Eat hash token.
3682  SMLoc ExLoc = Parser.getTok().getLoc();
3683
3684  const MCExpr *ShiftAmount;
3685  SMLoc EndLoc;
3686  if (getParser().ParseExpression(ShiftAmount, EndLoc)) {
3687    Error(ExLoc, "malformed rotate expression");
3688    return MatchOperand_ParseFail;
3689  }
3690  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3691  if (!CE) {
3692    Error(ExLoc, "rotate amount must be an immediate");
3693    return MatchOperand_ParseFail;
3694  }
3695
3696  int64_t Val = CE->getValue();
3697  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3698  // normally, zero is represented in asm by omitting the rotate operand
3699  // entirely.
3700  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3701    Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3702    return MatchOperand_ParseFail;
3703  }
3704
3705  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3706
3707  return MatchOperand_Success;
3708}
3709
3710ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3711parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3712  SMLoc S = Parser.getTok().getLoc();
3713  // The bitfield descriptor is really two operands, the LSB and the width.
3714  if (Parser.getTok().isNot(AsmToken::Hash) &&
3715      Parser.getTok().isNot(AsmToken::Dollar)) {
3716    Error(Parser.getTok().getLoc(), "'#' expected");
3717    return MatchOperand_ParseFail;
3718  }
3719  Parser.Lex(); // Eat hash token.
3720
3721  const MCExpr *LSBExpr;
3722  SMLoc E = Parser.getTok().getLoc();
3723  if (getParser().ParseExpression(LSBExpr)) {
3724    Error(E, "malformed immediate expression");
3725    return MatchOperand_ParseFail;
3726  }
3727  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3728  if (!CE) {
3729    Error(E, "'lsb' operand must be an immediate");
3730    return MatchOperand_ParseFail;
3731  }
3732
3733  int64_t LSB = CE->getValue();
3734  // The LSB must be in the range [0,31]
3735  if (LSB < 0 || LSB > 31) {
3736    Error(E, "'lsb' operand must be in the range [0,31]");
3737    return MatchOperand_ParseFail;
3738  }
3739  E = Parser.getTok().getLoc();
3740
3741  // Expect another immediate operand.
3742  if (Parser.getTok().isNot(AsmToken::Comma)) {
3743    Error(Parser.getTok().getLoc(), "too few operands");
3744    return MatchOperand_ParseFail;
3745  }
3746  Parser.Lex(); // Eat hash token.
3747  if (Parser.getTok().isNot(AsmToken::Hash) &&
3748      Parser.getTok().isNot(AsmToken::Dollar)) {
3749    Error(Parser.getTok().getLoc(), "'#' expected");
3750    return MatchOperand_ParseFail;
3751  }
3752  Parser.Lex(); // Eat hash token.
3753
3754  const MCExpr *WidthExpr;
3755  SMLoc EndLoc;
3756  if (getParser().ParseExpression(WidthExpr, EndLoc)) {
3757    Error(E, "malformed immediate expression");
3758    return MatchOperand_ParseFail;
3759  }
3760  CE = dyn_cast<MCConstantExpr>(WidthExpr);
3761  if (!CE) {
3762    Error(E, "'width' operand must be an immediate");
3763    return MatchOperand_ParseFail;
3764  }
3765
3766  int64_t Width = CE->getValue();
3767  // The LSB must be in the range [1,32-lsb]
3768  if (Width < 1 || Width > 32 - LSB) {
3769    Error(E, "'width' operand must be in the range [1,32-lsb]");
3770    return MatchOperand_ParseFail;
3771  }
3772
3773  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3774
3775  return MatchOperand_Success;
3776}
3777
3778ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3779parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3780  // Check for a post-index addressing register operand. Specifically:
3781  // postidx_reg := '+' register {, shift}
3782  //              | '-' register {, shift}
3783  //              | register {, shift}
3784
3785  // This method must return MatchOperand_NoMatch without consuming any tokens
3786  // in the case where there is no match, as other alternatives take other
3787  // parse methods.
3788  AsmToken Tok = Parser.getTok();
3789  SMLoc S = Tok.getLoc();
3790  bool haveEaten = false;
3791  bool isAdd = true;
3792  if (Tok.is(AsmToken::Plus)) {
3793    Parser.Lex(); // Eat the '+' token.
3794    haveEaten = true;
3795  } else if (Tok.is(AsmToken::Minus)) {
3796    Parser.Lex(); // Eat the '-' token.
3797    isAdd = false;
3798    haveEaten = true;
3799  }
3800
3801  SMLoc E = Parser.getTok().getEndLoc();
3802  int Reg = tryParseRegister();
3803  if (Reg == -1) {
3804    if (!haveEaten)
3805      return MatchOperand_NoMatch;
3806    Error(Parser.getTok().getLoc(), "register expected");
3807    return MatchOperand_ParseFail;
3808  }
3809
3810  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3811  unsigned ShiftImm = 0;
3812  if (Parser.getTok().is(AsmToken::Comma)) {
3813    Parser.Lex(); // Eat the ','.
3814    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3815      return MatchOperand_ParseFail;
3816
3817    // FIXME: Only approximates end...may include intervening whitespace.
3818    E = Parser.getTok().getLoc();
3819  }
3820
3821  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3822                                                  ShiftImm, S, E));
3823
3824  return MatchOperand_Success;
3825}
3826
3827ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3828parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3829  // Check for a post-index addressing register operand. Specifically:
3830  // am3offset := '+' register
3831  //              | '-' register
3832  //              | register
3833  //              | # imm
3834  //              | # + imm
3835  //              | # - imm
3836
3837  // This method must return MatchOperand_NoMatch without consuming any tokens
3838  // in the case where there is no match, as other alternatives take other
3839  // parse methods.
3840  AsmToken Tok = Parser.getTok();
3841  SMLoc S = Tok.getLoc();
3842
3843  // Do immediates first, as we always parse those if we have a '#'.
3844  if (Parser.getTok().is(AsmToken::Hash) ||
3845      Parser.getTok().is(AsmToken::Dollar)) {
3846    Parser.Lex(); // Eat the '#'.
3847    // Explicitly look for a '-', as we need to encode negative zero
3848    // differently.
3849    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3850    const MCExpr *Offset;
3851    SMLoc E;
3852    if (getParser().ParseExpression(Offset, E))
3853      return MatchOperand_ParseFail;
3854    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3855    if (!CE) {
3856      Error(S, "constant expression expected");
3857      return MatchOperand_ParseFail;
3858    }
3859    // Negative zero is encoded as the flag value INT32_MIN.
3860    int32_t Val = CE->getValue();
3861    if (isNegative && Val == 0)
3862      Val = INT32_MIN;
3863
3864    Operands.push_back(
3865      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3866
3867    return MatchOperand_Success;
3868  }
3869
3870
3871  bool haveEaten = false;
3872  bool isAdd = true;
3873  if (Tok.is(AsmToken::Plus)) {
3874    Parser.Lex(); // Eat the '+' token.
3875    haveEaten = true;
3876  } else if (Tok.is(AsmToken::Minus)) {
3877    Parser.Lex(); // Eat the '-' token.
3878    isAdd = false;
3879    haveEaten = true;
3880  }
3881
3882  Tok = Parser.getTok();
3883  int Reg = tryParseRegister();
3884  if (Reg == -1) {
3885    if (!haveEaten)
3886      return MatchOperand_NoMatch;
3887    Error(Tok.getLoc(), "register expected");
3888    return MatchOperand_ParseFail;
3889  }
3890
3891  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3892                                                  0, S, Tok.getEndLoc()));
3893
3894  return MatchOperand_Success;
3895}
3896
3897/// cvtT2LdrdPre - Convert parsed operands to MCInst.
3898/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3899/// when they refer multiple MIOperands inside a single one.
3900void ARMAsmParser::
3901cvtT2LdrdPre(MCInst &Inst,
3902             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3903  // Rt, Rt2
3904  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3905  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3906  // Create a writeback register dummy placeholder.
3907  Inst.addOperand(MCOperand::CreateReg(0));
3908  // addr
3909  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3910  // pred
3911  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3912}
3913
3914/// cvtT2StrdPre - Convert parsed operands to MCInst.
3915/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3916/// when they refer multiple MIOperands inside a single one.
3917void ARMAsmParser::
3918cvtT2StrdPre(MCInst &Inst,
3919             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3920  // Create a writeback register dummy placeholder.
3921  Inst.addOperand(MCOperand::CreateReg(0));
3922  // Rt, Rt2
3923  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3924  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3925  // addr
3926  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3927  // pred
3928  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3929}
3930
3931/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3932/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3933/// when they refer multiple MIOperands inside a single one.
3934void ARMAsmParser::
3935cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
3936                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3937  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3938
3939  // Create a writeback register dummy placeholder.
3940  Inst.addOperand(MCOperand::CreateImm(0));
3941
3942  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3943  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3944}
3945
3946/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3947/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3948/// when they refer multiple MIOperands inside a single one.
3949void ARMAsmParser::
3950cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
3951                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3952  // Create a writeback register dummy placeholder.
3953  Inst.addOperand(MCOperand::CreateImm(0));
3954  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3955  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3956  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3957}
3958
3959/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3960/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3961/// when they refer multiple MIOperands inside a single one.
3962void ARMAsmParser::
3963cvtLdWriteBackRegAddrMode2(MCInst &Inst,
3964                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3965  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3966
3967  // Create a writeback register dummy placeholder.
3968  Inst.addOperand(MCOperand::CreateImm(0));
3969
3970  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3971  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3972}
3973
3974/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3975/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3976/// when they refer multiple MIOperands inside a single one.
3977void ARMAsmParser::
3978cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
3979                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3980  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3981
3982  // Create a writeback register dummy placeholder.
3983  Inst.addOperand(MCOperand::CreateImm(0));
3984
3985  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3986  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3987}
3988
3989
3990/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3991/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3992/// when they refer multiple MIOperands inside a single one.
3993void ARMAsmParser::
3994cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
3995                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3996  // Create a writeback register dummy placeholder.
3997  Inst.addOperand(MCOperand::CreateImm(0));
3998  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3999  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4000  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4001}
4002
4003/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
4004/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4005/// when they refer multiple MIOperands inside a single one.
4006void ARMAsmParser::
4007cvtStWriteBackRegAddrMode2(MCInst &Inst,
4008                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4009  // Create a writeback register dummy placeholder.
4010  Inst.addOperand(MCOperand::CreateImm(0));
4011  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4012  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4013  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4014}
4015
4016/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4017/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4018/// when they refer multiple MIOperands inside a single one.
4019void ARMAsmParser::
4020cvtStWriteBackRegAddrMode3(MCInst &Inst,
4021                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4022  // Create a writeback register dummy placeholder.
4023  Inst.addOperand(MCOperand::CreateImm(0));
4024  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4025  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4026  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4027}
4028
4029/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4030/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4031/// when they refer multiple MIOperands inside a single one.
4032void ARMAsmParser::
4033cvtLdExtTWriteBackImm(MCInst &Inst,
4034                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4035  // Rt
4036  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4037  // Create a writeback register dummy placeholder.
4038  Inst.addOperand(MCOperand::CreateImm(0));
4039  // addr
4040  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4041  // offset
4042  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4043  // pred
4044  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4045}
4046
4047/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4048/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4049/// when they refer multiple MIOperands inside a single one.
4050void ARMAsmParser::
4051cvtLdExtTWriteBackReg(MCInst &Inst,
4052                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4053  // Rt
4054  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4055  // Create a writeback register dummy placeholder.
4056  Inst.addOperand(MCOperand::CreateImm(0));
4057  // addr
4058  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4059  // offset
4060  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4061  // pred
4062  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4063}
4064
4065/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4066/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4067/// when they refer multiple MIOperands inside a single one.
4068void ARMAsmParser::
4069cvtStExtTWriteBackImm(MCInst &Inst,
4070                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4071  // Create a writeback register dummy placeholder.
4072  Inst.addOperand(MCOperand::CreateImm(0));
4073  // Rt
4074  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4075  // addr
4076  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4077  // offset
4078  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4079  // pred
4080  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4081}
4082
4083/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4084/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4085/// when they refer multiple MIOperands inside a single one.
4086void ARMAsmParser::
4087cvtStExtTWriteBackReg(MCInst &Inst,
4088                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4089  // Create a writeback register dummy placeholder.
4090  Inst.addOperand(MCOperand::CreateImm(0));
4091  // Rt
4092  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4093  // addr
4094  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4095  // offset
4096  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4097  // pred
4098  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4099}
4100
4101/// cvtLdrdPre - Convert parsed operands to MCInst.
4102/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4103/// when they refer multiple MIOperands inside a single one.
4104void ARMAsmParser::
4105cvtLdrdPre(MCInst &Inst,
4106           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4107  // Rt, Rt2
4108  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4109  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4110  // Create a writeback register dummy placeholder.
4111  Inst.addOperand(MCOperand::CreateImm(0));
4112  // addr
4113  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4114  // pred
4115  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4116}
4117
4118/// cvtStrdPre - Convert parsed operands to MCInst.
4119/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4120/// when they refer multiple MIOperands inside a single one.
4121void ARMAsmParser::
4122cvtStrdPre(MCInst &Inst,
4123           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4124  // Create a writeback register dummy placeholder.
4125  Inst.addOperand(MCOperand::CreateImm(0));
4126  // Rt, Rt2
4127  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4128  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4129  // addr
4130  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4131  // pred
4132  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4133}
4134
4135/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4136/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4137/// when they refer multiple MIOperands inside a single one.
4138void ARMAsmParser::
4139cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4140                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4141  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4142  // Create a writeback register dummy placeholder.
4143  Inst.addOperand(MCOperand::CreateImm(0));
4144  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4145  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4146}
4147
4148/// cvtThumbMultiply - Convert parsed operands to MCInst.
4149/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4150/// when they refer multiple MIOperands inside a single one.
4151void ARMAsmParser::
4152cvtThumbMultiply(MCInst &Inst,
4153           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4154  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4155  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4156  // If we have a three-operand form, make sure to set Rn to be the operand
4157  // that isn't the same as Rd.
4158  unsigned RegOp = 4;
4159  if (Operands.size() == 6 &&
4160      ((ARMOperand*)Operands[4])->getReg() ==
4161        ((ARMOperand*)Operands[3])->getReg())
4162    RegOp = 5;
4163  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4164  Inst.addOperand(Inst.getOperand(0));
4165  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4166}
4167
4168void ARMAsmParser::
4169cvtVLDwbFixed(MCInst &Inst,
4170              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4171  // Vd
4172  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4173  // Create a writeback register dummy placeholder.
4174  Inst.addOperand(MCOperand::CreateImm(0));
4175  // Vn
4176  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4177  // pred
4178  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4179}
4180
4181void ARMAsmParser::
4182cvtVLDwbRegister(MCInst &Inst,
4183                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4184  // Vd
4185  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4186  // Create a writeback register dummy placeholder.
4187  Inst.addOperand(MCOperand::CreateImm(0));
4188  // Vn
4189  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4190  // Vm
4191  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4192  // pred
4193  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4194}
4195
4196void ARMAsmParser::
4197cvtVSTwbFixed(MCInst &Inst,
4198              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4199  // Create a writeback register dummy placeholder.
4200  Inst.addOperand(MCOperand::CreateImm(0));
4201  // Vn
4202  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4203  // Vt
4204  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4205  // pred
4206  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4207}
4208
4209void ARMAsmParser::
4210cvtVSTwbRegister(MCInst &Inst,
4211                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4212  // Create a writeback register dummy placeholder.
4213  Inst.addOperand(MCOperand::CreateImm(0));
4214  // Vn
4215  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4216  // Vm
4217  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4218  // Vt
4219  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4220  // pred
4221  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4222}
4223
4224/// Parse an ARM memory expression, return false if successful else return true
4225/// or an error.  The first token must be a '[' when called.
4226bool ARMAsmParser::
4227parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4228  SMLoc S, E;
4229  assert(Parser.getTok().is(AsmToken::LBrac) &&
4230         "Token is not a Left Bracket");
4231  S = Parser.getTok().getLoc();
4232  Parser.Lex(); // Eat left bracket token.
4233
4234  const AsmToken &BaseRegTok = Parser.getTok();
4235  int BaseRegNum = tryParseRegister();
4236  if (BaseRegNum == -1)
4237    return Error(BaseRegTok.getLoc(), "register expected");
4238
4239  // The next token must either be a comma or a closing bracket.
4240  const AsmToken &Tok = Parser.getTok();
4241  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4242    return Error(Tok.getLoc(), "malformed memory operand");
4243
4244  if (Tok.is(AsmToken::RBrac)) {
4245    E = Tok.getEndLoc();
4246    Parser.Lex(); // Eat right bracket token.
4247
4248    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4249                                             0, 0, false, S, E));
4250
4251    // If there's a pre-indexing writeback marker, '!', just add it as a token
4252    // operand. It's rather odd, but syntactically valid.
4253    if (Parser.getTok().is(AsmToken::Exclaim)) {
4254      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4255      Parser.Lex(); // Eat the '!'.
4256    }
4257
4258    return false;
4259  }
4260
4261  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4262  Parser.Lex(); // Eat the comma.
4263
4264  // If we have a ':', it's an alignment specifier.
4265  if (Parser.getTok().is(AsmToken::Colon)) {
4266    Parser.Lex(); // Eat the ':'.
4267    E = Parser.getTok().getLoc();
4268
4269    const MCExpr *Expr;
4270    if (getParser().ParseExpression(Expr))
4271     return true;
4272
4273    // The expression has to be a constant. Memory references with relocations
4274    // don't come through here, as they use the <label> forms of the relevant
4275    // instructions.
4276    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4277    if (!CE)
4278      return Error (E, "constant expression expected");
4279
4280    unsigned Align = 0;
4281    switch (CE->getValue()) {
4282    default:
4283      return Error(E,
4284                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4285    case 16:  Align = 2; break;
4286    case 32:  Align = 4; break;
4287    case 64:  Align = 8; break;
4288    case 128: Align = 16; break;
4289    case 256: Align = 32; break;
4290    }
4291
4292    // Now we should have the closing ']'
4293    if (Parser.getTok().isNot(AsmToken::RBrac))
4294      return Error(Parser.getTok().getLoc(), "']' expected");
4295    E = Parser.getTok().getEndLoc();
4296    Parser.Lex(); // Eat right bracket token.
4297
4298    // Don't worry about range checking the value here. That's handled by
4299    // the is*() predicates.
4300    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4301                                             ARM_AM::no_shift, 0, Align,
4302                                             false, S, E));
4303
4304    // If there's a pre-indexing writeback marker, '!', just add it as a token
4305    // operand.
4306    if (Parser.getTok().is(AsmToken::Exclaim)) {
4307      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4308      Parser.Lex(); // Eat the '!'.
4309    }
4310
4311    return false;
4312  }
4313
4314  // If we have a '#', it's an immediate offset, else assume it's a register
4315  // offset. Be friendly and also accept a plain integer (without a leading
4316  // hash) for gas compatibility.
4317  if (Parser.getTok().is(AsmToken::Hash) ||
4318      Parser.getTok().is(AsmToken::Dollar) ||
4319      Parser.getTok().is(AsmToken::Integer)) {
4320    if (Parser.getTok().isNot(AsmToken::Integer))
4321      Parser.Lex(); // Eat the '#'.
4322    E = Parser.getTok().getLoc();
4323
4324    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4325    const MCExpr *Offset;
4326    if (getParser().ParseExpression(Offset))
4327     return true;
4328
4329    // The expression has to be a constant. Memory references with relocations
4330    // don't come through here, as they use the <label> forms of the relevant
4331    // instructions.
4332    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4333    if (!CE)
4334      return Error (E, "constant expression expected");
4335
4336    // If the constant was #-0, represent it as INT32_MIN.
4337    int32_t Val = CE->getValue();
4338    if (isNegative && Val == 0)
4339      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4340
4341    // Now we should have the closing ']'
4342    if (Parser.getTok().isNot(AsmToken::RBrac))
4343      return Error(Parser.getTok().getLoc(), "']' expected");
4344    E = Parser.getTok().getEndLoc();
4345    Parser.Lex(); // Eat right bracket token.
4346
4347    // Don't worry about range checking the value here. That's handled by
4348    // the is*() predicates.
4349    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4350                                             ARM_AM::no_shift, 0, 0,
4351                                             false, S, E));
4352
4353    // If there's a pre-indexing writeback marker, '!', just add it as a token
4354    // operand.
4355    if (Parser.getTok().is(AsmToken::Exclaim)) {
4356      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4357      Parser.Lex(); // Eat the '!'.
4358    }
4359
4360    return false;
4361  }
4362
4363  // The register offset is optionally preceded by a '+' or '-'
4364  bool isNegative = false;
4365  if (Parser.getTok().is(AsmToken::Minus)) {
4366    isNegative = true;
4367    Parser.Lex(); // Eat the '-'.
4368  } else if (Parser.getTok().is(AsmToken::Plus)) {
4369    // Nothing to do.
4370    Parser.Lex(); // Eat the '+'.
4371  }
4372
4373  E = Parser.getTok().getLoc();
4374  int OffsetRegNum = tryParseRegister();
4375  if (OffsetRegNum == -1)
4376    return Error(E, "register expected");
4377
4378  // If there's a shift operator, handle it.
4379  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4380  unsigned ShiftImm = 0;
4381  if (Parser.getTok().is(AsmToken::Comma)) {
4382    Parser.Lex(); // Eat the ','.
4383    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4384      return true;
4385  }
4386
4387  // Now we should have the closing ']'
4388  if (Parser.getTok().isNot(AsmToken::RBrac))
4389    return Error(Parser.getTok().getLoc(), "']' expected");
4390  E = Parser.getTok().getEndLoc();
4391  Parser.Lex(); // Eat right bracket token.
4392
4393  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4394                                           ShiftType, ShiftImm, 0, isNegative,
4395                                           S, E));
4396
4397  // If there's a pre-indexing writeback marker, '!', just add it as a token
4398  // operand.
4399  if (Parser.getTok().is(AsmToken::Exclaim)) {
4400    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4401    Parser.Lex(); // Eat the '!'.
4402  }
4403
4404  return false;
4405}
4406
4407/// parseMemRegOffsetShift - one of these two:
4408///   ( lsl | lsr | asr | ror ) , # shift_amount
4409///   rrx
4410/// return true if it parses a shift otherwise it returns false.
4411bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4412                                          unsigned &Amount) {
4413  SMLoc Loc = Parser.getTok().getLoc();
4414  const AsmToken &Tok = Parser.getTok();
4415  if (Tok.isNot(AsmToken::Identifier))
4416    return true;
4417  StringRef ShiftName = Tok.getString();
4418  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4419      ShiftName == "asl" || ShiftName == "ASL")
4420    St = ARM_AM::lsl;
4421  else if (ShiftName == "lsr" || ShiftName == "LSR")
4422    St = ARM_AM::lsr;
4423  else if (ShiftName == "asr" || ShiftName == "ASR")
4424    St = ARM_AM::asr;
4425  else if (ShiftName == "ror" || ShiftName == "ROR")
4426    St = ARM_AM::ror;
4427  else if (ShiftName == "rrx" || ShiftName == "RRX")
4428    St = ARM_AM::rrx;
4429  else
4430    return Error(Loc, "illegal shift operator");
4431  Parser.Lex(); // Eat shift type token.
4432
4433  // rrx stands alone.
4434  Amount = 0;
4435  if (St != ARM_AM::rrx) {
4436    Loc = Parser.getTok().getLoc();
4437    // A '#' and a shift amount.
4438    const AsmToken &HashTok = Parser.getTok();
4439    if (HashTok.isNot(AsmToken::Hash) &&
4440        HashTok.isNot(AsmToken::Dollar))
4441      return Error(HashTok.getLoc(), "'#' expected");
4442    Parser.Lex(); // Eat hash token.
4443
4444    const MCExpr *Expr;
4445    if (getParser().ParseExpression(Expr))
4446      return true;
4447    // Range check the immediate.
4448    // lsl, ror: 0 <= imm <= 31
4449    // lsr, asr: 0 <= imm <= 32
4450    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4451    if (!CE)
4452      return Error(Loc, "shift amount must be an immediate");
4453    int64_t Imm = CE->getValue();
4454    if (Imm < 0 ||
4455        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4456        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4457      return Error(Loc, "immediate shift value out of range");
4458    // If <ShiftTy> #0, turn it into a no_shift.
4459    if (Imm == 0)
4460      St = ARM_AM::lsl;
4461    // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4462    if (Imm == 32)
4463      Imm = 0;
4464    Amount = Imm;
4465  }
4466
4467  return false;
4468}
4469
4470/// parseFPImm - A floating point immediate expression operand.
4471ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4472parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4473  // Anything that can accept a floating point constant as an operand
4474  // needs to go through here, as the regular ParseExpression is
4475  // integer only.
4476  //
4477  // This routine still creates a generic Immediate operand, containing
4478  // a bitcast of the 64-bit floating point value. The various operands
4479  // that accept floats can check whether the value is valid for them
4480  // via the standard is*() predicates.
4481
4482  SMLoc S = Parser.getTok().getLoc();
4483
4484  if (Parser.getTok().isNot(AsmToken::Hash) &&
4485      Parser.getTok().isNot(AsmToken::Dollar))
4486    return MatchOperand_NoMatch;
4487
4488  // Disambiguate the VMOV forms that can accept an FP immediate.
4489  // vmov.f32 <sreg>, #imm
4490  // vmov.f64 <dreg>, #imm
4491  // vmov.f32 <dreg>, #imm  @ vector f32x2
4492  // vmov.f32 <qreg>, #imm  @ vector f32x4
4493  //
4494  // There are also the NEON VMOV instructions which expect an
4495  // integer constant. Make sure we don't try to parse an FPImm
4496  // for these:
4497  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4498  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4499  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4500                           TyOp->getToken() != ".f64"))
4501    return MatchOperand_NoMatch;
4502
4503  Parser.Lex(); // Eat the '#'.
4504
4505  // Handle negation, as that still comes through as a separate token.
4506  bool isNegative = false;
4507  if (Parser.getTok().is(AsmToken::Minus)) {
4508    isNegative = true;
4509    Parser.Lex();
4510  }
4511  const AsmToken &Tok = Parser.getTok();
4512  SMLoc Loc = Tok.getLoc();
4513  if (Tok.is(AsmToken::Real)) {
4514    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4515    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4516    // If we had a '-' in front, toggle the sign bit.
4517    IntVal ^= (uint64_t)isNegative << 31;
4518    Parser.Lex(); // Eat the token.
4519    Operands.push_back(ARMOperand::CreateImm(
4520          MCConstantExpr::Create(IntVal, getContext()),
4521          S, Parser.getTok().getLoc()));
4522    return MatchOperand_Success;
4523  }
4524  // Also handle plain integers. Instructions which allow floating point
4525  // immediates also allow a raw encoded 8-bit value.
4526  if (Tok.is(AsmToken::Integer)) {
4527    int64_t Val = Tok.getIntVal();
4528    Parser.Lex(); // Eat the token.
4529    if (Val > 255 || Val < 0) {
4530      Error(Loc, "encoded floating point value out of range");
4531      return MatchOperand_ParseFail;
4532    }
4533    double RealVal = ARM_AM::getFPImmFloat(Val);
4534    Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4535    Operands.push_back(ARMOperand::CreateImm(
4536        MCConstantExpr::Create(Val, getContext()), S,
4537        Parser.getTok().getLoc()));
4538    return MatchOperand_Success;
4539  }
4540
4541  Error(Loc, "invalid floating point immediate");
4542  return MatchOperand_ParseFail;
4543}
4544
4545/// Parse a arm instruction operand.  For now this parses the operand regardless
4546/// of the mnemonic.
4547bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4548                                StringRef Mnemonic) {
4549  SMLoc S, E;
4550
4551  // Check if the current operand has a custom associated parser, if so, try to
4552  // custom parse the operand, or fallback to the general approach.
4553  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4554  if (ResTy == MatchOperand_Success)
4555    return false;
4556  // If there wasn't a custom match, try the generic matcher below. Otherwise,
4557  // there was a match, but an error occurred, in which case, just return that
4558  // the operand parsing failed.
4559  if (ResTy == MatchOperand_ParseFail)
4560    return true;
4561
4562  switch (getLexer().getKind()) {
4563  default:
4564    Error(Parser.getTok().getLoc(), "unexpected token in operand");
4565    return true;
4566  case AsmToken::Identifier: {
4567    if (!tryParseRegisterWithWriteBack(Operands))
4568      return false;
4569    int Res = tryParseShiftRegister(Operands);
4570    if (Res == 0) // success
4571      return false;
4572    else if (Res == -1) // irrecoverable error
4573      return true;
4574    // If this is VMRS, check for the apsr_nzcv operand.
4575    if (Mnemonic == "vmrs" &&
4576        Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4577      S = Parser.getTok().getLoc();
4578      Parser.Lex();
4579      Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4580      return false;
4581    }
4582
4583    // Fall though for the Identifier case that is not a register or a
4584    // special name.
4585  }
4586  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4587  case AsmToken::Integer: // things like 1f and 2b as a branch targets
4588  case AsmToken::String:  // quoted label names.
4589  case AsmToken::Dot: {   // . as a branch target
4590    // This was not a register so parse other operands that start with an
4591    // identifier (like labels) as expressions and create them as immediates.
4592    const MCExpr *IdVal;
4593    S = Parser.getTok().getLoc();
4594    if (getParser().ParseExpression(IdVal))
4595      return true;
4596    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4597    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4598    return false;
4599  }
4600  case AsmToken::LBrac:
4601    return parseMemory(Operands);
4602  case AsmToken::LCurly:
4603    return parseRegisterList(Operands);
4604  case AsmToken::Dollar:
4605  case AsmToken::Hash: {
4606    // #42 -> immediate.
4607    S = Parser.getTok().getLoc();
4608    Parser.Lex();
4609
4610    if (Parser.getTok().isNot(AsmToken::Colon)) {
4611      bool isNegative = Parser.getTok().is(AsmToken::Minus);
4612      const MCExpr *ImmVal;
4613      if (getParser().ParseExpression(ImmVal))
4614        return true;
4615      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4616      if (CE) {
4617        int32_t Val = CE->getValue();
4618        if (isNegative && Val == 0)
4619          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4620      }
4621      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4622      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4623      return false;
4624    }
4625    // w/ a ':' after the '#', it's just like a plain ':'.
4626    // FALLTHROUGH
4627  }
4628  case AsmToken::Colon: {
4629    // ":lower16:" and ":upper16:" expression prefixes
4630    // FIXME: Check it's an expression prefix,
4631    // e.g. (FOO - :lower16:BAR) isn't legal.
4632    ARMMCExpr::VariantKind RefKind;
4633    if (parsePrefix(RefKind))
4634      return true;
4635
4636    const MCExpr *SubExprVal;
4637    if (getParser().ParseExpression(SubExprVal))
4638      return true;
4639
4640    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4641                                              getContext());
4642    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4643    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4644    return false;
4645  }
4646  }
4647}
4648
4649// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4650//  :lower16: and :upper16:.
4651bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4652  RefKind = ARMMCExpr::VK_ARM_None;
4653
4654  // :lower16: and :upper16: modifiers
4655  assert(getLexer().is(AsmToken::Colon) && "expected a :");
4656  Parser.Lex(); // Eat ':'
4657
4658  if (getLexer().isNot(AsmToken::Identifier)) {
4659    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4660    return true;
4661  }
4662
4663  StringRef IDVal = Parser.getTok().getIdentifier();
4664  if (IDVal == "lower16") {
4665    RefKind = ARMMCExpr::VK_ARM_LO16;
4666  } else if (IDVal == "upper16") {
4667    RefKind = ARMMCExpr::VK_ARM_HI16;
4668  } else {
4669    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4670    return true;
4671  }
4672  Parser.Lex();
4673
4674  if (getLexer().isNot(AsmToken::Colon)) {
4675    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4676    return true;
4677  }
4678  Parser.Lex(); // Eat the last ':'
4679  return false;
4680}
4681
4682/// \brief Given a mnemonic, split out possible predication code and carry
4683/// setting letters to form a canonical mnemonic and flags.
4684//
4685// FIXME: Would be nice to autogen this.
4686// FIXME: This is a bit of a maze of special cases.
4687StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4688                                      unsigned &PredicationCode,
4689                                      bool &CarrySetting,
4690                                      unsigned &ProcessorIMod,
4691                                      StringRef &ITMask) {
4692  PredicationCode = ARMCC::AL;
4693  CarrySetting = false;
4694  ProcessorIMod = 0;
4695
4696  // Ignore some mnemonics we know aren't predicated forms.
4697  //
4698  // FIXME: Would be nice to autogen this.
4699  if ((Mnemonic == "movs" && isThumb()) ||
4700      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4701      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4702      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4703      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4704      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4705      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4706      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4707      Mnemonic == "fmuls")
4708    return Mnemonic;
4709
4710  // First, split out any predication code. Ignore mnemonics we know aren't
4711  // predicated but do have a carry-set and so weren't caught above.
4712  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4713      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4714      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4715      Mnemonic != "sbcs" && Mnemonic != "rscs") {
4716    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4717      .Case("eq", ARMCC::EQ)
4718      .Case("ne", ARMCC::NE)
4719      .Case("hs", ARMCC::HS)
4720      .Case("cs", ARMCC::HS)
4721      .Case("lo", ARMCC::LO)
4722      .Case("cc", ARMCC::LO)
4723      .Case("mi", ARMCC::MI)
4724      .Case("pl", ARMCC::PL)
4725      .Case("vs", ARMCC::VS)
4726      .Case("vc", ARMCC::VC)
4727      .Case("hi", ARMCC::HI)
4728      .Case("ls", ARMCC::LS)
4729      .Case("ge", ARMCC::GE)
4730      .Case("lt", ARMCC::LT)
4731      .Case("gt", ARMCC::GT)
4732      .Case("le", ARMCC::LE)
4733      .Case("al", ARMCC::AL)
4734      .Default(~0U);
4735    if (CC != ~0U) {
4736      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4737      PredicationCode = CC;
4738    }
4739  }
4740
4741  // Next, determine if we have a carry setting bit. We explicitly ignore all
4742  // the instructions we know end in 's'.
4743  if (Mnemonic.endswith("s") &&
4744      !(Mnemonic == "cps" || Mnemonic == "mls" ||
4745        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4746        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4747        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4748        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4749        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4750        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4751        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4752        Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4753        (Mnemonic == "movs" && isThumb()))) {
4754    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4755    CarrySetting = true;
4756  }
4757
4758  // The "cps" instruction can have a interrupt mode operand which is glued into
4759  // the mnemonic. Check if this is the case, split it and parse the imod op
4760  if (Mnemonic.startswith("cps")) {
4761    // Split out any imod code.
4762    unsigned IMod =
4763      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4764      .Case("ie", ARM_PROC::IE)
4765      .Case("id", ARM_PROC::ID)
4766      .Default(~0U);
4767    if (IMod != ~0U) {
4768      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4769      ProcessorIMod = IMod;
4770    }
4771  }
4772
4773  // The "it" instruction has the condition mask on the end of the mnemonic.
4774  if (Mnemonic.startswith("it")) {
4775    ITMask = Mnemonic.slice(2, Mnemonic.size());
4776    Mnemonic = Mnemonic.slice(0, 2);
4777  }
4778
4779  return Mnemonic;
4780}
4781
4782/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4783/// inclusion of carry set or predication code operands.
4784//
4785// FIXME: It would be nice to autogen this.
4786void ARMAsmParser::
4787getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4788                      bool &CanAcceptPredicationCode) {
4789  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4790      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4791      Mnemonic == "add" || Mnemonic == "adc" ||
4792      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4793      Mnemonic == "orr" || Mnemonic == "mvn" ||
4794      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4795      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4796      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4797      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4798                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4799                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4800    CanAcceptCarrySet = true;
4801  } else
4802    CanAcceptCarrySet = false;
4803
4804  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4805      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4806      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4807      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4808      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4809      (Mnemonic == "clrex" && !isThumb()) ||
4810      (Mnemonic == "nop" && isThumbOne()) ||
4811      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4812        Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4813        Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4814      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4815       !isThumb()) ||
4816      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4817    CanAcceptPredicationCode = false;
4818  } else
4819    CanAcceptPredicationCode = true;
4820
4821  if (isThumb()) {
4822    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4823        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4824      CanAcceptPredicationCode = false;
4825  }
4826}
4827
4828bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4829                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4830  // FIXME: This is all horribly hacky. We really need a better way to deal
4831  // with optional operands like this in the matcher table.
4832
4833  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4834  // another does not. Specifically, the MOVW instruction does not. So we
4835  // special case it here and remove the defaulted (non-setting) cc_out
4836  // operand if that's the instruction we're trying to match.
4837  //
4838  // We do this as post-processing of the explicit operands rather than just
4839  // conditionally adding the cc_out in the first place because we need
4840  // to check the type of the parsed immediate operand.
4841  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4842      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4843      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4844      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4845    return true;
4846
4847  // Register-register 'add' for thumb does not have a cc_out operand
4848  // when there are only two register operands.
4849  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4850      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4851      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4852      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4853    return true;
4854  // Register-register 'add' for thumb does not have a cc_out operand
4855  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4856  // have to check the immediate range here since Thumb2 has a variant
4857  // that can handle a different range and has a cc_out operand.
4858  if (((isThumb() && Mnemonic == "add") ||
4859       (isThumbTwo() && Mnemonic == "sub")) &&
4860      Operands.size() == 6 &&
4861      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4862      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4863      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4864      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4865      ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4866       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4867    return true;
4868  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4869  // imm0_4095 variant. That's the least-preferred variant when
4870  // selecting via the generic "add" mnemonic, so to know that we
4871  // should remove the cc_out operand, we have to explicitly check that
4872  // it's not one of the other variants. Ugh.
4873  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4874      Operands.size() == 6 &&
4875      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4876      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4877      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4878    // Nest conditions rather than one big 'if' statement for readability.
4879    //
4880    // If either register is a high reg, it's either one of the SP
4881    // variants (handled above) or a 32-bit encoding, so we just
4882    // check against T3. If the second register is the PC, this is an
4883    // alternate form of ADR, which uses encoding T4, so check for that too.
4884    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4885         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4886        static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4887        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4888      return false;
4889    // If both registers are low, we're in an IT block, and the immediate is
4890    // in range, we should use encoding T1 instead, which has a cc_out.
4891    if (inITBlock() &&
4892        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4893        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4894        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4895      return false;
4896
4897    // Otherwise, we use encoding T4, which does not have a cc_out
4898    // operand.
4899    return true;
4900  }
4901
4902  // The thumb2 multiply instruction doesn't have a CCOut register, so
4903  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4904  // use the 16-bit encoding or not.
4905  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4906      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4907      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4908      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4909      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4910      // If the registers aren't low regs, the destination reg isn't the
4911      // same as one of the source regs, or the cc_out operand is zero
4912      // outside of an IT block, we have to use the 32-bit encoding, so
4913      // remove the cc_out operand.
4914      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4915       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4916       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4917       !inITBlock() ||
4918       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4919        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4920        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4921        static_cast<ARMOperand*>(Operands[4])->getReg())))
4922    return true;
4923
4924  // Also check the 'mul' syntax variant that doesn't specify an explicit
4925  // destination register.
4926  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4927      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4928      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4929      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4930      // If the registers aren't low regs  or the cc_out operand is zero
4931      // outside of an IT block, we have to use the 32-bit encoding, so
4932      // remove the cc_out operand.
4933      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4934       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4935       !inITBlock()))
4936    return true;
4937
4938
4939
4940  // Register-register 'add/sub' for thumb does not have a cc_out operand
4941  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4942  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4943  // right, this will result in better diagnostics (which operand is off)
4944  // anyway.
4945  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4946      (Operands.size() == 5 || Operands.size() == 6) &&
4947      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4948      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4949      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4950      (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4951       (Operands.size() == 6 &&
4952        static_cast<ARMOperand*>(Operands[5])->isImm())))
4953    return true;
4954
4955  return false;
4956}
4957
4958static bool isDataTypeToken(StringRef Tok) {
4959  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4960    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4961    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4962    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4963    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4964    Tok == ".f" || Tok == ".d";
4965}
4966
4967// FIXME: This bit should probably be handled via an explicit match class
4968// in the .td files that matches the suffix instead of having it be
4969// a literal string token the way it is now.
4970static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4971  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4972}
4973
4974static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4975/// Parse an arm instruction mnemonic followed by its operands.
4976bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
4977                                    SMLoc NameLoc,
4978                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4979  // Apply mnemonic aliases before doing anything else, as the destination
4980  // mnemnonic may include suffices and we want to handle them normally.
4981  // The generic tblgen'erated code does this later, at the start of
4982  // MatchInstructionImpl(), but that's too late for aliases that include
4983  // any sort of suffix.
4984  unsigned AvailableFeatures = getAvailableFeatures();
4985  applyMnemonicAliases(Name, AvailableFeatures);
4986
4987  // First check for the ARM-specific .req directive.
4988  if (Parser.getTok().is(AsmToken::Identifier) &&
4989      Parser.getTok().getIdentifier() == ".req") {
4990    parseDirectiveReq(Name, NameLoc);
4991    // We always return 'error' for this, as we're done with this
4992    // statement and don't need to match the 'instruction."
4993    return true;
4994  }
4995
4996  // Create the leading tokens for the mnemonic, split by '.' characters.
4997  size_t Start = 0, Next = Name.find('.');
4998  StringRef Mnemonic = Name.slice(Start, Next);
4999
5000  // Split out the predication code and carry setting flag from the mnemonic.
5001  unsigned PredicationCode;
5002  unsigned ProcessorIMod;
5003  bool CarrySetting;
5004  StringRef ITMask;
5005  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5006                           ProcessorIMod, ITMask);
5007
5008  // In Thumb1, only the branch (B) instruction can be predicated.
5009  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5010    Parser.EatToEndOfStatement();
5011    return Error(NameLoc, "conditional execution not supported in Thumb1");
5012  }
5013
5014  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5015
5016  // Handle the IT instruction ITMask. Convert it to a bitmask. This
5017  // is the mask as it will be for the IT encoding if the conditional
5018  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5019  // where the conditional bit0 is zero, the instruction post-processing
5020  // will adjust the mask accordingly.
5021  if (Mnemonic == "it") {
5022    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5023    if (ITMask.size() > 3) {
5024      Parser.EatToEndOfStatement();
5025      return Error(Loc, "too many conditions on IT instruction");
5026    }
5027    unsigned Mask = 8;
5028    for (unsigned i = ITMask.size(); i != 0; --i) {
5029      char pos = ITMask[i - 1];
5030      if (pos != 't' && pos != 'e') {
5031        Parser.EatToEndOfStatement();
5032        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5033      }
5034      Mask >>= 1;
5035      if (ITMask[i - 1] == 't')
5036        Mask |= 8;
5037    }
5038    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5039  }
5040
5041  // FIXME: This is all a pretty gross hack. We should automatically handle
5042  // optional operands like this via tblgen.
5043
5044  // Next, add the CCOut and ConditionCode operands, if needed.
5045  //
5046  // For mnemonics which can ever incorporate a carry setting bit or predication
5047  // code, our matching model involves us always generating CCOut and
5048  // ConditionCode operands to match the mnemonic "as written" and then we let
5049  // the matcher deal with finding the right instruction or generating an
5050  // appropriate error.
5051  bool CanAcceptCarrySet, CanAcceptPredicationCode;
5052  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5053
5054  // If we had a carry-set on an instruction that can't do that, issue an
5055  // error.
5056  if (!CanAcceptCarrySet && CarrySetting) {
5057    Parser.EatToEndOfStatement();
5058    return Error(NameLoc, "instruction '" + Mnemonic +
5059                 "' can not set flags, but 's' suffix specified");
5060  }
5061  // If we had a predication code on an instruction that can't do that, issue an
5062  // error.
5063  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5064    Parser.EatToEndOfStatement();
5065    return Error(NameLoc, "instruction '" + Mnemonic +
5066                 "' is not predicable, but condition code specified");
5067  }
5068
5069  // Add the carry setting operand, if necessary.
5070  if (CanAcceptCarrySet) {
5071    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5072    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5073                                               Loc));
5074  }
5075
5076  // Add the predication code operand, if necessary.
5077  if (CanAcceptPredicationCode) {
5078    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5079                                      CarrySetting);
5080    Operands.push_back(ARMOperand::CreateCondCode(
5081                         ARMCC::CondCodes(PredicationCode), Loc));
5082  }
5083
5084  // Add the processor imod operand, if necessary.
5085  if (ProcessorIMod) {
5086    Operands.push_back(ARMOperand::CreateImm(
5087          MCConstantExpr::Create(ProcessorIMod, getContext()),
5088                                 NameLoc, NameLoc));
5089  }
5090
5091  // Add the remaining tokens in the mnemonic.
5092  while (Next != StringRef::npos) {
5093    Start = Next;
5094    Next = Name.find('.', Start + 1);
5095    StringRef ExtraToken = Name.slice(Start, Next);
5096
5097    // Some NEON instructions have an optional datatype suffix that is
5098    // completely ignored. Check for that.
5099    if (isDataTypeToken(ExtraToken) &&
5100        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5101      continue;
5102
5103    if (ExtraToken != ".n") {
5104      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5105      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5106    }
5107  }
5108
5109  // Read the remaining operands.
5110  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5111    // Read the first operand.
5112    if (parseOperand(Operands, Mnemonic)) {
5113      Parser.EatToEndOfStatement();
5114      return true;
5115    }
5116
5117    while (getLexer().is(AsmToken::Comma)) {
5118      Parser.Lex();  // Eat the comma.
5119
5120      // Parse and remember the operand.
5121      if (parseOperand(Operands, Mnemonic)) {
5122        Parser.EatToEndOfStatement();
5123        return true;
5124      }
5125    }
5126  }
5127
5128  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5129    SMLoc Loc = getLexer().getLoc();
5130    Parser.EatToEndOfStatement();
5131    return Error(Loc, "unexpected token in argument list");
5132  }
5133
5134  Parser.Lex(); // Consume the EndOfStatement
5135
5136  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5137  // do and don't have a cc_out optional-def operand. With some spot-checks
5138  // of the operand list, we can figure out which variant we're trying to
5139  // parse and adjust accordingly before actually matching. We shouldn't ever
5140  // try to remove a cc_out operand that was explicitly set on the the
5141  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5142  // table driven matcher doesn't fit well with the ARM instruction set.
5143  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5144    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5145    Operands.erase(Operands.begin() + 1);
5146    delete Op;
5147  }
5148
5149  // ARM mode 'blx' need special handling, as the register operand version
5150  // is predicable, but the label operand version is not. So, we can't rely
5151  // on the Mnemonic based checking to correctly figure out when to put
5152  // a k_CondCode operand in the list. If we're trying to match the label
5153  // version, remove the k_CondCode operand here.
5154  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5155      static_cast<ARMOperand*>(Operands[2])->isImm()) {
5156    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5157    Operands.erase(Operands.begin() + 1);
5158    delete Op;
5159  }
5160
5161  // The vector-compare-to-zero instructions have a literal token "#0" at
5162  // the end that comes to here as an immediate operand. Convert it to a
5163  // token to play nicely with the matcher.
5164  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5165      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5166      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5167    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5168    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5169    if (CE && CE->getValue() == 0) {
5170      Operands.erase(Operands.begin() + 5);
5171      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5172      delete Op;
5173    }
5174  }
5175  // VCMP{E} does the same thing, but with a different operand count.
5176  if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5177      static_cast<ARMOperand*>(Operands[4])->isImm()) {
5178    ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5179    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5180    if (CE && CE->getValue() == 0) {
5181      Operands.erase(Operands.begin() + 4);
5182      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5183      delete Op;
5184    }
5185  }
5186  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5187  // end. Convert it to a token here. Take care not to convert those
5188  // that should hit the Thumb2 encoding.
5189  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5190      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5191      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5192      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5193    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5194    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5195    if (CE && CE->getValue() == 0 &&
5196        (isThumbOne() ||
5197         // The cc_out operand matches the IT block.
5198         ((inITBlock() != CarrySetting) &&
5199         // Neither register operand is a high register.
5200         (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5201          isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5202      Operands.erase(Operands.begin() + 5);
5203      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5204      delete Op;
5205    }
5206  }
5207
5208  // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5209  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5210  // a single GPRPair reg operand is used in the .td file to replace the two
5211  // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5212  // expressed as a GPRPair, so we have to manually merge them.
5213  // FIXME: We would really like to be able to tablegen'erate this.
5214  if (!isThumb() && Operands.size() > 4 &&
5215      (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5216    bool isLoad = (Mnemonic == "ldrexd");
5217    unsigned Idx = isLoad ? 2 : 3;
5218    ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5219    ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5220
5221    const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5222    // Adjust only if Op1 and Op2 are GPRs.
5223    if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5224        MRC.contains(Op2->getReg())) {
5225      unsigned Reg1 = Op1->getReg();
5226      unsigned Reg2 = Op2->getReg();
5227      unsigned Rt = MRI->getEncodingValue(Reg1);
5228      unsigned Rt2 = MRI->getEncodingValue(Reg2);
5229
5230      // Rt2 must be Rt + 1 and Rt must be even.
5231      if (Rt + 1 != Rt2 || (Rt & 1)) {
5232        Error(Op2->getStartLoc(), isLoad ?
5233            "destination operands must be sequential" :
5234            "source operands must be sequential");
5235        return true;
5236      }
5237      unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5238          &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5239      Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5240      Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5241            NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5242      delete Op1;
5243      delete Op2;
5244    }
5245  }
5246
5247  return false;
5248}
5249
5250// Validate context-sensitive operand constraints.
5251
5252// return 'true' if register list contains non-low GPR registers,
5253// 'false' otherwise. If Reg is in the register list or is HiReg, set
5254// 'containsReg' to true.
5255static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5256                                 unsigned HiReg, bool &containsReg) {
5257  containsReg = false;
5258  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5259    unsigned OpReg = Inst.getOperand(i).getReg();
5260    if (OpReg == Reg)
5261      containsReg = true;
5262    // Anything other than a low register isn't legal here.
5263    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5264      return true;
5265  }
5266  return false;
5267}
5268
5269// Check if the specified regisgter is in the register list of the inst,
5270// starting at the indicated operand number.
5271static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5272  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5273    unsigned OpReg = Inst.getOperand(i).getReg();
5274    if (OpReg == Reg)
5275      return true;
5276  }
5277  return false;
5278}
5279
5280// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5281// the ARMInsts array) instead. Getting that here requires awkward
5282// API changes, though. Better way?
5283namespace llvm {
5284extern const MCInstrDesc ARMInsts[];
5285}
5286static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5287  return ARMInsts[Opcode];
5288}
5289
5290// FIXME: We would really like to be able to tablegen'erate this.
5291bool ARMAsmParser::
5292validateInstruction(MCInst &Inst,
5293                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5294  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5295  SMLoc Loc = Operands[0]->getStartLoc();
5296  // Check the IT block state first.
5297  // NOTE: BKPT instruction has the interesting property of being
5298  // allowed in IT blocks, but not being predicable.  It just always
5299  // executes.
5300  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5301      Inst.getOpcode() != ARM::BKPT) {
5302    unsigned bit = 1;
5303    if (ITState.FirstCond)
5304      ITState.FirstCond = false;
5305    else
5306      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5307    // The instruction must be predicable.
5308    if (!MCID.isPredicable())
5309      return Error(Loc, "instructions in IT block must be predicable");
5310    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5311    unsigned ITCond = bit ? ITState.Cond :
5312      ARMCC::getOppositeCondition(ITState.Cond);
5313    if (Cond != ITCond) {
5314      // Find the condition code Operand to get its SMLoc information.
5315      SMLoc CondLoc;
5316      for (unsigned i = 1; i < Operands.size(); ++i)
5317        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5318          CondLoc = Operands[i]->getStartLoc();
5319      return Error(CondLoc, "incorrect condition in IT block; got '" +
5320                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5321                   "', but expected '" +
5322                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5323    }
5324  // Check for non-'al' condition codes outside of the IT block.
5325  } else if (isThumbTwo() && MCID.isPredicable() &&
5326             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5327             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5328             Inst.getOpcode() != ARM::t2B)
5329    return Error(Loc, "predicated instructions must be in IT block");
5330
5331  switch (Inst.getOpcode()) {
5332  case ARM::LDRD:
5333  case ARM::LDRD_PRE:
5334  case ARM::LDRD_POST: {
5335    // Rt2 must be Rt + 1.
5336    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5337    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5338    if (Rt2 != Rt + 1)
5339      return Error(Operands[3]->getStartLoc(),
5340                   "destination operands must be sequential");
5341    return false;
5342  }
5343  case ARM::STRD: {
5344    // Rt2 must be Rt + 1.
5345    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5346    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5347    if (Rt2 != Rt + 1)
5348      return Error(Operands[3]->getStartLoc(),
5349                   "source operands must be sequential");
5350    return false;
5351  }
5352  case ARM::STRD_PRE:
5353  case ARM::STRD_POST: {
5354    // Rt2 must be Rt + 1.
5355    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5356    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5357    if (Rt2 != Rt + 1)
5358      return Error(Operands[3]->getStartLoc(),
5359                   "source operands must be sequential");
5360    return false;
5361  }
5362  case ARM::SBFX:
5363  case ARM::UBFX: {
5364    // width must be in range [1, 32-lsb]
5365    unsigned lsb = Inst.getOperand(2).getImm();
5366    unsigned widthm1 = Inst.getOperand(3).getImm();
5367    if (widthm1 >= 32 - lsb)
5368      return Error(Operands[5]->getStartLoc(),
5369                   "bitfield width must be in range [1,32-lsb]");
5370    return false;
5371  }
5372  case ARM::tLDMIA: {
5373    // If we're parsing Thumb2, the .w variant is available and handles
5374    // most cases that are normally illegal for a Thumb1 LDM
5375    // instruction. We'll make the transformation in processInstruction()
5376    // if necessary.
5377    //
5378    // Thumb LDM instructions are writeback iff the base register is not
5379    // in the register list.
5380    unsigned Rn = Inst.getOperand(0).getReg();
5381    bool hasWritebackToken =
5382      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5383       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5384    bool listContainsBase;
5385    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5386      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5387                   "registers must be in range r0-r7");
5388    // If we should have writeback, then there should be a '!' token.
5389    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5390      return Error(Operands[2]->getStartLoc(),
5391                   "writeback operator '!' expected");
5392    // If we should not have writeback, there must not be a '!'. This is
5393    // true even for the 32-bit wide encodings.
5394    if (listContainsBase && hasWritebackToken)
5395      return Error(Operands[3]->getStartLoc(),
5396                   "writeback operator '!' not allowed when base register "
5397                   "in register list");
5398
5399    break;
5400  }
5401  case ARM::t2LDMIA_UPD: {
5402    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5403      return Error(Operands[4]->getStartLoc(),
5404                   "writeback operator '!' not allowed when base register "
5405                   "in register list");
5406    break;
5407  }
5408  case ARM::tMUL: {
5409    // The second source operand must be the same register as the destination
5410    // operand.
5411    //
5412    // In this case, we must directly check the parsed operands because the
5413    // cvtThumbMultiply() function is written in such a way that it guarantees
5414    // this first statement is always true for the new Inst.  Essentially, the
5415    // destination is unconditionally copied into the second source operand
5416    // without checking to see if it matches what we actually parsed.
5417    if (Operands.size() == 6 &&
5418        (((ARMOperand*)Operands[3])->getReg() !=
5419         ((ARMOperand*)Operands[5])->getReg()) &&
5420        (((ARMOperand*)Operands[3])->getReg() !=
5421         ((ARMOperand*)Operands[4])->getReg())) {
5422      return Error(Operands[3]->getStartLoc(),
5423                   "destination register must match source register");
5424    }
5425    break;
5426  }
5427  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5428  // so only issue a diagnostic for thumb1. The instructions will be
5429  // switched to the t2 encodings in processInstruction() if necessary.
5430  case ARM::tPOP: {
5431    bool listContainsBase;
5432    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5433        !isThumbTwo())
5434      return Error(Operands[2]->getStartLoc(),
5435                   "registers must be in range r0-r7 or pc");
5436    break;
5437  }
5438  case ARM::tPUSH: {
5439    bool listContainsBase;
5440    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5441        !isThumbTwo())
5442      return Error(Operands[2]->getStartLoc(),
5443                   "registers must be in range r0-r7 or lr");
5444    break;
5445  }
5446  case ARM::tSTMIA_UPD: {
5447    bool listContainsBase;
5448    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5449      return Error(Operands[4]->getStartLoc(),
5450                   "registers must be in range r0-r7");
5451    break;
5452  }
5453  case ARM::tADDrSP: {
5454    // If the non-SP source operand and the destination operand are not the
5455    // same, we need thumb2 (for the wide encoding), or we have an error.
5456    if (!isThumbTwo() &&
5457        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5458      return Error(Operands[4]->getStartLoc(),
5459                   "source register must be the same as destination");
5460    }
5461    break;
5462  }
5463  }
5464
5465  return false;
5466}
5467
5468static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5469  switch(Opc) {
5470  default: llvm_unreachable("unexpected opcode!");
5471  // VST1LN
5472  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5473  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5474  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5475  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5476  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5477  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5478  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5479  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5480  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5481
5482  // VST2LN
5483  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5484  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5485  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5486  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5487  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5488
5489  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5490  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5491  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5492  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5493  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5494
5495  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5496  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5497  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5498  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5499  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5500
5501  // VST3LN
5502  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5503  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5504  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5505  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5506  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5507  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5508  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5509  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5510  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5511  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5512  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5513  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5514  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5515  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5516  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5517
5518  // VST3
5519  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5520  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5521  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5522  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5523  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5524  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5525  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5526  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5527  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5528  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5529  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5530  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5531  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5532  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5533  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5534  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5535  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5536  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5537
5538  // VST4LN
5539  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5540  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5541  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5542  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5543  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5544  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5545  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5546  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5547  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5548  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5549  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5550  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5551  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5552  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5553  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5554
5555  // VST4
5556  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5557  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5558  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5559  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5560  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5561  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5562  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5563  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5564  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5565  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5566  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5567  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5568  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5569  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5570  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5571  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5572  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5573  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5574  }
5575}
5576
5577static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5578  switch(Opc) {
5579  default: llvm_unreachable("unexpected opcode!");
5580  // VLD1LN
5581  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5582  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5583  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5584  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5585  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5586  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5587  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5588  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5589  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5590
5591  // VLD2LN
5592  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5593  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5594  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5595  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5596  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5597  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5598  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5599  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5600  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5601  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5602  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5603  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5604  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5605  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5606  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5607
5608  // VLD3DUP
5609  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5610  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5611  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5612  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5613  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5614  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5615  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5616  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5617  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5618  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5619  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5620  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5621  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5622  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5623  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5624  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5625  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5626  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5627
5628  // VLD3LN
5629  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5630  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5631  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5632  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5633  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5634  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5635  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5636  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5637  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5638  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5639  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5640  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5641  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5642  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5643  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5644
5645  // VLD3
5646  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5647  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5648  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5649  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5650  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5651  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5652  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5653  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5654  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5655  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5656  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5657  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5658  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5659  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5660  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5661  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5662  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5663  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5664
5665  // VLD4LN
5666  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5667  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5668  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5669  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5670  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5671  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5672  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5673  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5674  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5675  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5676  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5677  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5678  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5679  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5680  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5681
5682  // VLD4DUP
5683  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5684  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5685  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5686  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5687  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5688  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5689  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5690  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5691  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5692  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5693  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5694  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5695  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5696  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5697  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5698  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5699  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5700  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5701
5702  // VLD4
5703  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5704  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5705  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5706  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5707  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5708  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5709  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5710  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5711  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5712  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5713  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5714  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5715  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5716  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5717  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5718  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5719  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5720  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5721  }
5722}
5723
5724bool ARMAsmParser::
5725processInstruction(MCInst &Inst,
5726                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5727  switch (Inst.getOpcode()) {
5728  // Alias for alternate form of 'ADR Rd, #imm' instruction.
5729  case ARM::ADDri: {
5730    if (Inst.getOperand(1).getReg() != ARM::PC ||
5731        Inst.getOperand(5).getReg() != 0)
5732      return false;
5733    MCInst TmpInst;
5734    TmpInst.setOpcode(ARM::ADR);
5735    TmpInst.addOperand(Inst.getOperand(0));
5736    TmpInst.addOperand(Inst.getOperand(2));
5737    TmpInst.addOperand(Inst.getOperand(3));
5738    TmpInst.addOperand(Inst.getOperand(4));
5739    Inst = TmpInst;
5740    return true;
5741  }
5742  // Aliases for alternate PC+imm syntax of LDR instructions.
5743  case ARM::t2LDRpcrel:
5744    // Select the narrow version if the immediate will fit.
5745    if (Inst.getOperand(1).getImm() > 0 &&
5746        Inst.getOperand(1).getImm() <= 0xff)
5747      Inst.setOpcode(ARM::tLDRpci);
5748    else
5749      Inst.setOpcode(ARM::t2LDRpci);
5750    return true;
5751  case ARM::t2LDRBpcrel:
5752    Inst.setOpcode(ARM::t2LDRBpci);
5753    return true;
5754  case ARM::t2LDRHpcrel:
5755    Inst.setOpcode(ARM::t2LDRHpci);
5756    return true;
5757  case ARM::t2LDRSBpcrel:
5758    Inst.setOpcode(ARM::t2LDRSBpci);
5759    return true;
5760  case ARM::t2LDRSHpcrel:
5761    Inst.setOpcode(ARM::t2LDRSHpci);
5762    return true;
5763  // Handle NEON VST complex aliases.
5764  case ARM::VST1LNdWB_register_Asm_8:
5765  case ARM::VST1LNdWB_register_Asm_16:
5766  case ARM::VST1LNdWB_register_Asm_32: {
5767    MCInst TmpInst;
5768    // Shuffle the operands around so the lane index operand is in the
5769    // right place.
5770    unsigned Spacing;
5771    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5772    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5773    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5774    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5775    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5776    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5777    TmpInst.addOperand(Inst.getOperand(1)); // lane
5778    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5779    TmpInst.addOperand(Inst.getOperand(6));
5780    Inst = TmpInst;
5781    return true;
5782  }
5783
5784  case ARM::VST2LNdWB_register_Asm_8:
5785  case ARM::VST2LNdWB_register_Asm_16:
5786  case ARM::VST2LNdWB_register_Asm_32:
5787  case ARM::VST2LNqWB_register_Asm_16:
5788  case ARM::VST2LNqWB_register_Asm_32: {
5789    MCInst TmpInst;
5790    // Shuffle the operands around so the lane index operand is in the
5791    // right place.
5792    unsigned Spacing;
5793    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5794    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5795    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5796    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5797    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5798    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5799    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5800                                            Spacing));
5801    TmpInst.addOperand(Inst.getOperand(1)); // lane
5802    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5803    TmpInst.addOperand(Inst.getOperand(6));
5804    Inst = TmpInst;
5805    return true;
5806  }
5807
5808  case ARM::VST3LNdWB_register_Asm_8:
5809  case ARM::VST3LNdWB_register_Asm_16:
5810  case ARM::VST3LNdWB_register_Asm_32:
5811  case ARM::VST3LNqWB_register_Asm_16:
5812  case ARM::VST3LNqWB_register_Asm_32: {
5813    MCInst TmpInst;
5814    // Shuffle the operands around so the lane index operand is in the
5815    // right place.
5816    unsigned Spacing;
5817    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5818    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5819    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5820    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5821    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5822    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5823    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5824                                            Spacing));
5825    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5826                                            Spacing * 2));
5827    TmpInst.addOperand(Inst.getOperand(1)); // lane
5828    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5829    TmpInst.addOperand(Inst.getOperand(6));
5830    Inst = TmpInst;
5831    return true;
5832  }
5833
5834  case ARM::VST4LNdWB_register_Asm_8:
5835  case ARM::VST4LNdWB_register_Asm_16:
5836  case ARM::VST4LNdWB_register_Asm_32:
5837  case ARM::VST4LNqWB_register_Asm_16:
5838  case ARM::VST4LNqWB_register_Asm_32: {
5839    MCInst TmpInst;
5840    // Shuffle the operands around so the lane index operand is in the
5841    // right place.
5842    unsigned Spacing;
5843    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5844    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5845    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5846    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5847    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5848    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5849    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5850                                            Spacing));
5851    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5852                                            Spacing * 2));
5853    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5854                                            Spacing * 3));
5855    TmpInst.addOperand(Inst.getOperand(1)); // lane
5856    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5857    TmpInst.addOperand(Inst.getOperand(6));
5858    Inst = TmpInst;
5859    return true;
5860  }
5861
5862  case ARM::VST1LNdWB_fixed_Asm_8:
5863  case ARM::VST1LNdWB_fixed_Asm_16:
5864  case ARM::VST1LNdWB_fixed_Asm_32: {
5865    MCInst TmpInst;
5866    // Shuffle the operands around so the lane index operand is in the
5867    // right place.
5868    unsigned Spacing;
5869    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5870    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5871    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5872    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5873    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5874    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5875    TmpInst.addOperand(Inst.getOperand(1)); // lane
5876    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5877    TmpInst.addOperand(Inst.getOperand(5));
5878    Inst = TmpInst;
5879    return true;
5880  }
5881
5882  case ARM::VST2LNdWB_fixed_Asm_8:
5883  case ARM::VST2LNdWB_fixed_Asm_16:
5884  case ARM::VST2LNdWB_fixed_Asm_32:
5885  case ARM::VST2LNqWB_fixed_Asm_16:
5886  case ARM::VST2LNqWB_fixed_Asm_32: {
5887    MCInst TmpInst;
5888    // Shuffle the operands around so the lane index operand is in the
5889    // right place.
5890    unsigned Spacing;
5891    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5892    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5893    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5894    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5895    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5896    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5897    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5898                                            Spacing));
5899    TmpInst.addOperand(Inst.getOperand(1)); // lane
5900    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5901    TmpInst.addOperand(Inst.getOperand(5));
5902    Inst = TmpInst;
5903    return true;
5904  }
5905
5906  case ARM::VST3LNdWB_fixed_Asm_8:
5907  case ARM::VST3LNdWB_fixed_Asm_16:
5908  case ARM::VST3LNdWB_fixed_Asm_32:
5909  case ARM::VST3LNqWB_fixed_Asm_16:
5910  case ARM::VST3LNqWB_fixed_Asm_32: {
5911    MCInst TmpInst;
5912    // Shuffle the operands around so the lane index operand is in the
5913    // right place.
5914    unsigned Spacing;
5915    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5916    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5917    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5918    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5919    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5920    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5921    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5922                                            Spacing));
5923    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5924                                            Spacing * 2));
5925    TmpInst.addOperand(Inst.getOperand(1)); // lane
5926    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5927    TmpInst.addOperand(Inst.getOperand(5));
5928    Inst = TmpInst;
5929    return true;
5930  }
5931
5932  case ARM::VST4LNdWB_fixed_Asm_8:
5933  case ARM::VST4LNdWB_fixed_Asm_16:
5934  case ARM::VST4LNdWB_fixed_Asm_32:
5935  case ARM::VST4LNqWB_fixed_Asm_16:
5936  case ARM::VST4LNqWB_fixed_Asm_32: {
5937    MCInst TmpInst;
5938    // Shuffle the operands around so the lane index operand is in the
5939    // right place.
5940    unsigned Spacing;
5941    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5942    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5943    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5944    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5945    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5946    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5947    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5948                                            Spacing));
5949    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5950                                            Spacing * 2));
5951    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5952                                            Spacing * 3));
5953    TmpInst.addOperand(Inst.getOperand(1)); // lane
5954    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5955    TmpInst.addOperand(Inst.getOperand(5));
5956    Inst = TmpInst;
5957    return true;
5958  }
5959
5960  case ARM::VST1LNdAsm_8:
5961  case ARM::VST1LNdAsm_16:
5962  case ARM::VST1LNdAsm_32: {
5963    MCInst TmpInst;
5964    // Shuffle the operands around so the lane index operand is in the
5965    // right place.
5966    unsigned Spacing;
5967    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5968    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5969    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5970    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5971    TmpInst.addOperand(Inst.getOperand(1)); // lane
5972    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5973    TmpInst.addOperand(Inst.getOperand(5));
5974    Inst = TmpInst;
5975    return true;
5976  }
5977
5978  case ARM::VST2LNdAsm_8:
5979  case ARM::VST2LNdAsm_16:
5980  case ARM::VST2LNdAsm_32:
5981  case ARM::VST2LNqAsm_16:
5982  case ARM::VST2LNqAsm_32: {
5983    MCInst TmpInst;
5984    // Shuffle the operands around so the lane index operand is in the
5985    // right place.
5986    unsigned Spacing;
5987    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5988    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5989    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5990    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5991    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5992                                            Spacing));
5993    TmpInst.addOperand(Inst.getOperand(1)); // lane
5994    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5995    TmpInst.addOperand(Inst.getOperand(5));
5996    Inst = TmpInst;
5997    return true;
5998  }
5999
6000  case ARM::VST3LNdAsm_8:
6001  case ARM::VST3LNdAsm_16:
6002  case ARM::VST3LNdAsm_32:
6003  case ARM::VST3LNqAsm_16:
6004  case ARM::VST3LNqAsm_32: {
6005    MCInst TmpInst;
6006    // Shuffle the operands around so the lane index operand is in the
6007    // right place.
6008    unsigned Spacing;
6009    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6010    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6011    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6012    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6013    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6014                                            Spacing));
6015    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6016                                            Spacing * 2));
6017    TmpInst.addOperand(Inst.getOperand(1)); // lane
6018    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6019    TmpInst.addOperand(Inst.getOperand(5));
6020    Inst = TmpInst;
6021    return true;
6022  }
6023
6024  case ARM::VST4LNdAsm_8:
6025  case ARM::VST4LNdAsm_16:
6026  case ARM::VST4LNdAsm_32:
6027  case ARM::VST4LNqAsm_16:
6028  case ARM::VST4LNqAsm_32: {
6029    MCInst TmpInst;
6030    // Shuffle the operands around so the lane index operand is in the
6031    // right place.
6032    unsigned Spacing;
6033    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6034    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6035    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6036    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6037    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6038                                            Spacing));
6039    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6040                                            Spacing * 2));
6041    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6042                                            Spacing * 3));
6043    TmpInst.addOperand(Inst.getOperand(1)); // lane
6044    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6045    TmpInst.addOperand(Inst.getOperand(5));
6046    Inst = TmpInst;
6047    return true;
6048  }
6049
6050  // Handle NEON VLD complex aliases.
6051  case ARM::VLD1LNdWB_register_Asm_8:
6052  case ARM::VLD1LNdWB_register_Asm_16:
6053  case ARM::VLD1LNdWB_register_Asm_32: {
6054    MCInst TmpInst;
6055    // Shuffle the operands around so the lane index operand is in the
6056    // right place.
6057    unsigned Spacing;
6058    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6059    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6060    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6061    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6062    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6063    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6064    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6065    TmpInst.addOperand(Inst.getOperand(1)); // lane
6066    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6067    TmpInst.addOperand(Inst.getOperand(6));
6068    Inst = TmpInst;
6069    return true;
6070  }
6071
6072  case ARM::VLD2LNdWB_register_Asm_8:
6073  case ARM::VLD2LNdWB_register_Asm_16:
6074  case ARM::VLD2LNdWB_register_Asm_32:
6075  case ARM::VLD2LNqWB_register_Asm_16:
6076  case ARM::VLD2LNqWB_register_Asm_32: {
6077    MCInst TmpInst;
6078    // Shuffle the operands around so the lane index operand is in the
6079    // right place.
6080    unsigned Spacing;
6081    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6082    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6083    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6084                                            Spacing));
6085    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6086    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6087    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6088    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6089    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6090    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6091                                            Spacing));
6092    TmpInst.addOperand(Inst.getOperand(1)); // lane
6093    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6094    TmpInst.addOperand(Inst.getOperand(6));
6095    Inst = TmpInst;
6096    return true;
6097  }
6098
6099  case ARM::VLD3LNdWB_register_Asm_8:
6100  case ARM::VLD3LNdWB_register_Asm_16:
6101  case ARM::VLD3LNdWB_register_Asm_32:
6102  case ARM::VLD3LNqWB_register_Asm_16:
6103  case ARM::VLD3LNqWB_register_Asm_32: {
6104    MCInst TmpInst;
6105    // Shuffle the operands around so the lane index operand is in the
6106    // right place.
6107    unsigned Spacing;
6108    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6109    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6110    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6111                                            Spacing));
6112    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6113                                            Spacing * 2));
6114    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6115    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6116    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6117    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6118    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6119    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6120                                            Spacing));
6121    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6122                                            Spacing * 2));
6123    TmpInst.addOperand(Inst.getOperand(1)); // lane
6124    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6125    TmpInst.addOperand(Inst.getOperand(6));
6126    Inst = TmpInst;
6127    return true;
6128  }
6129
6130  case ARM::VLD4LNdWB_register_Asm_8:
6131  case ARM::VLD4LNdWB_register_Asm_16:
6132  case ARM::VLD4LNdWB_register_Asm_32:
6133  case ARM::VLD4LNqWB_register_Asm_16:
6134  case ARM::VLD4LNqWB_register_Asm_32: {
6135    MCInst TmpInst;
6136    // Shuffle the operands around so the lane index operand is in the
6137    // right place.
6138    unsigned Spacing;
6139    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6140    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6141    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6142                                            Spacing));
6143    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6144                                            Spacing * 2));
6145    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6146                                            Spacing * 3));
6147    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6148    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6149    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6150    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6151    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6152    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6153                                            Spacing));
6154    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6155                                            Spacing * 2));
6156    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6157                                            Spacing * 3));
6158    TmpInst.addOperand(Inst.getOperand(1)); // lane
6159    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6160    TmpInst.addOperand(Inst.getOperand(6));
6161    Inst = TmpInst;
6162    return true;
6163  }
6164
6165  case ARM::VLD1LNdWB_fixed_Asm_8:
6166  case ARM::VLD1LNdWB_fixed_Asm_16:
6167  case ARM::VLD1LNdWB_fixed_Asm_32: {
6168    MCInst TmpInst;
6169    // Shuffle the operands around so the lane index operand is in the
6170    // right place.
6171    unsigned Spacing;
6172    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6173    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6174    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6175    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6176    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6177    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6178    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6179    TmpInst.addOperand(Inst.getOperand(1)); // lane
6180    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6181    TmpInst.addOperand(Inst.getOperand(5));
6182    Inst = TmpInst;
6183    return true;
6184  }
6185
6186  case ARM::VLD2LNdWB_fixed_Asm_8:
6187  case ARM::VLD2LNdWB_fixed_Asm_16:
6188  case ARM::VLD2LNdWB_fixed_Asm_32:
6189  case ARM::VLD2LNqWB_fixed_Asm_16:
6190  case ARM::VLD2LNqWB_fixed_Asm_32: {
6191    MCInst TmpInst;
6192    // Shuffle the operands around so the lane index operand is in the
6193    // right place.
6194    unsigned Spacing;
6195    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6196    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6197    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6198                                            Spacing));
6199    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6200    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6201    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6202    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6203    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6204    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6205                                            Spacing));
6206    TmpInst.addOperand(Inst.getOperand(1)); // lane
6207    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6208    TmpInst.addOperand(Inst.getOperand(5));
6209    Inst = TmpInst;
6210    return true;
6211  }
6212
6213  case ARM::VLD3LNdWB_fixed_Asm_8:
6214  case ARM::VLD3LNdWB_fixed_Asm_16:
6215  case ARM::VLD3LNdWB_fixed_Asm_32:
6216  case ARM::VLD3LNqWB_fixed_Asm_16:
6217  case ARM::VLD3LNqWB_fixed_Asm_32: {
6218    MCInst TmpInst;
6219    // Shuffle the operands around so the lane index operand is in the
6220    // right place.
6221    unsigned Spacing;
6222    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6223    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6224    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6225                                            Spacing));
6226    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6227                                            Spacing * 2));
6228    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6229    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6230    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6231    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6232    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6233    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6234                                            Spacing));
6235    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6236                                            Spacing * 2));
6237    TmpInst.addOperand(Inst.getOperand(1)); // lane
6238    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6239    TmpInst.addOperand(Inst.getOperand(5));
6240    Inst = TmpInst;
6241    return true;
6242  }
6243
6244  case ARM::VLD4LNdWB_fixed_Asm_8:
6245  case ARM::VLD4LNdWB_fixed_Asm_16:
6246  case ARM::VLD4LNdWB_fixed_Asm_32:
6247  case ARM::VLD4LNqWB_fixed_Asm_16:
6248  case ARM::VLD4LNqWB_fixed_Asm_32: {
6249    MCInst TmpInst;
6250    // Shuffle the operands around so the lane index operand is in the
6251    // right place.
6252    unsigned Spacing;
6253    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6254    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6255    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6256                                            Spacing));
6257    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6258                                            Spacing * 2));
6259    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6260                                            Spacing * 3));
6261    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6262    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6263    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6264    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6265    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6266    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6267                                            Spacing));
6268    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6269                                            Spacing * 2));
6270    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6271                                            Spacing * 3));
6272    TmpInst.addOperand(Inst.getOperand(1)); // lane
6273    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6274    TmpInst.addOperand(Inst.getOperand(5));
6275    Inst = TmpInst;
6276    return true;
6277  }
6278
6279  case ARM::VLD1LNdAsm_8:
6280  case ARM::VLD1LNdAsm_16:
6281  case ARM::VLD1LNdAsm_32: {
6282    MCInst TmpInst;
6283    // Shuffle the operands around so the lane index operand is in the
6284    // right place.
6285    unsigned Spacing;
6286    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6287    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6288    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6289    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6290    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6291    TmpInst.addOperand(Inst.getOperand(1)); // lane
6292    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6293    TmpInst.addOperand(Inst.getOperand(5));
6294    Inst = TmpInst;
6295    return true;
6296  }
6297
6298  case ARM::VLD2LNdAsm_8:
6299  case ARM::VLD2LNdAsm_16:
6300  case ARM::VLD2LNdAsm_32:
6301  case ARM::VLD2LNqAsm_16:
6302  case ARM::VLD2LNqAsm_32: {
6303    MCInst TmpInst;
6304    // Shuffle the operands around so the lane index operand is in the
6305    // right place.
6306    unsigned Spacing;
6307    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6308    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6309    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6310                                            Spacing));
6311    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6312    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6313    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6314    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6315                                            Spacing));
6316    TmpInst.addOperand(Inst.getOperand(1)); // lane
6317    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6318    TmpInst.addOperand(Inst.getOperand(5));
6319    Inst = TmpInst;
6320    return true;
6321  }
6322
6323  case ARM::VLD3LNdAsm_8:
6324  case ARM::VLD3LNdAsm_16:
6325  case ARM::VLD3LNdAsm_32:
6326  case ARM::VLD3LNqAsm_16:
6327  case ARM::VLD3LNqAsm_32: {
6328    MCInst TmpInst;
6329    // Shuffle the operands around so the lane index operand is in the
6330    // right place.
6331    unsigned Spacing;
6332    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6333    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6334    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6335                                            Spacing));
6336    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6337                                            Spacing * 2));
6338    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6339    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6340    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6341    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6342                                            Spacing));
6343    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6344                                            Spacing * 2));
6345    TmpInst.addOperand(Inst.getOperand(1)); // lane
6346    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6347    TmpInst.addOperand(Inst.getOperand(5));
6348    Inst = TmpInst;
6349    return true;
6350  }
6351
6352  case ARM::VLD4LNdAsm_8:
6353  case ARM::VLD4LNdAsm_16:
6354  case ARM::VLD4LNdAsm_32:
6355  case ARM::VLD4LNqAsm_16:
6356  case ARM::VLD4LNqAsm_32: {
6357    MCInst TmpInst;
6358    // Shuffle the operands around so the lane index operand is in the
6359    // right place.
6360    unsigned Spacing;
6361    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6362    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6363    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6364                                            Spacing));
6365    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6366                                            Spacing * 2));
6367    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6368                                            Spacing * 3));
6369    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6370    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6371    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6372    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6373                                            Spacing));
6374    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6375                                            Spacing * 2));
6376    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6377                                            Spacing * 3));
6378    TmpInst.addOperand(Inst.getOperand(1)); // lane
6379    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6380    TmpInst.addOperand(Inst.getOperand(5));
6381    Inst = TmpInst;
6382    return true;
6383  }
6384
6385  // VLD3DUP single 3-element structure to all lanes instructions.
6386  case ARM::VLD3DUPdAsm_8:
6387  case ARM::VLD3DUPdAsm_16:
6388  case ARM::VLD3DUPdAsm_32:
6389  case ARM::VLD3DUPqAsm_8:
6390  case ARM::VLD3DUPqAsm_16:
6391  case ARM::VLD3DUPqAsm_32: {
6392    MCInst TmpInst;
6393    unsigned Spacing;
6394    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6395    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6396    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6397                                            Spacing));
6398    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6399                                            Spacing * 2));
6400    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6401    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6402    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6403    TmpInst.addOperand(Inst.getOperand(4));
6404    Inst = TmpInst;
6405    return true;
6406  }
6407
6408  case ARM::VLD3DUPdWB_fixed_Asm_8:
6409  case ARM::VLD3DUPdWB_fixed_Asm_16:
6410  case ARM::VLD3DUPdWB_fixed_Asm_32:
6411  case ARM::VLD3DUPqWB_fixed_Asm_8:
6412  case ARM::VLD3DUPqWB_fixed_Asm_16:
6413  case ARM::VLD3DUPqWB_fixed_Asm_32: {
6414    MCInst TmpInst;
6415    unsigned Spacing;
6416    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6417    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6418    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6419                                            Spacing));
6420    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6421                                            Spacing * 2));
6422    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6423    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6424    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6425    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6426    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6427    TmpInst.addOperand(Inst.getOperand(4));
6428    Inst = TmpInst;
6429    return true;
6430  }
6431
6432  case ARM::VLD3DUPdWB_register_Asm_8:
6433  case ARM::VLD3DUPdWB_register_Asm_16:
6434  case ARM::VLD3DUPdWB_register_Asm_32:
6435  case ARM::VLD3DUPqWB_register_Asm_8:
6436  case ARM::VLD3DUPqWB_register_Asm_16:
6437  case ARM::VLD3DUPqWB_register_Asm_32: {
6438    MCInst TmpInst;
6439    unsigned Spacing;
6440    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6441    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6442    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6443                                            Spacing));
6444    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6445                                            Spacing * 2));
6446    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6447    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6448    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6449    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6450    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6451    TmpInst.addOperand(Inst.getOperand(5));
6452    Inst = TmpInst;
6453    return true;
6454  }
6455
6456  // VLD3 multiple 3-element structure instructions.
6457  case ARM::VLD3dAsm_8:
6458  case ARM::VLD3dAsm_16:
6459  case ARM::VLD3dAsm_32:
6460  case ARM::VLD3qAsm_8:
6461  case ARM::VLD3qAsm_16:
6462  case ARM::VLD3qAsm_32: {
6463    MCInst TmpInst;
6464    unsigned Spacing;
6465    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6466    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6467    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6468                                            Spacing));
6469    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6470                                            Spacing * 2));
6471    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6472    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6473    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6474    TmpInst.addOperand(Inst.getOperand(4));
6475    Inst = TmpInst;
6476    return true;
6477  }
6478
6479  case ARM::VLD3dWB_fixed_Asm_8:
6480  case ARM::VLD3dWB_fixed_Asm_16:
6481  case ARM::VLD3dWB_fixed_Asm_32:
6482  case ARM::VLD3qWB_fixed_Asm_8:
6483  case ARM::VLD3qWB_fixed_Asm_16:
6484  case ARM::VLD3qWB_fixed_Asm_32: {
6485    MCInst TmpInst;
6486    unsigned Spacing;
6487    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6488    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6489    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6490                                            Spacing));
6491    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6492                                            Spacing * 2));
6493    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6494    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6495    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6496    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6497    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6498    TmpInst.addOperand(Inst.getOperand(4));
6499    Inst = TmpInst;
6500    return true;
6501  }
6502
6503  case ARM::VLD3dWB_register_Asm_8:
6504  case ARM::VLD3dWB_register_Asm_16:
6505  case ARM::VLD3dWB_register_Asm_32:
6506  case ARM::VLD3qWB_register_Asm_8:
6507  case ARM::VLD3qWB_register_Asm_16:
6508  case ARM::VLD3qWB_register_Asm_32: {
6509    MCInst TmpInst;
6510    unsigned Spacing;
6511    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6512    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6513    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6514                                            Spacing));
6515    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6516                                            Spacing * 2));
6517    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6518    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6519    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6520    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6521    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6522    TmpInst.addOperand(Inst.getOperand(5));
6523    Inst = TmpInst;
6524    return true;
6525  }
6526
6527  // VLD4DUP single 3-element structure to all lanes instructions.
6528  case ARM::VLD4DUPdAsm_8:
6529  case ARM::VLD4DUPdAsm_16:
6530  case ARM::VLD4DUPdAsm_32:
6531  case ARM::VLD4DUPqAsm_8:
6532  case ARM::VLD4DUPqAsm_16:
6533  case ARM::VLD4DUPqAsm_32: {
6534    MCInst TmpInst;
6535    unsigned Spacing;
6536    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6537    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6538    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6539                                            Spacing));
6540    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6541                                            Spacing * 2));
6542    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6543                                            Spacing * 3));
6544    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6545    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6546    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6547    TmpInst.addOperand(Inst.getOperand(4));
6548    Inst = TmpInst;
6549    return true;
6550  }
6551
6552  case ARM::VLD4DUPdWB_fixed_Asm_8:
6553  case ARM::VLD4DUPdWB_fixed_Asm_16:
6554  case ARM::VLD4DUPdWB_fixed_Asm_32:
6555  case ARM::VLD4DUPqWB_fixed_Asm_8:
6556  case ARM::VLD4DUPqWB_fixed_Asm_16:
6557  case ARM::VLD4DUPqWB_fixed_Asm_32: {
6558    MCInst TmpInst;
6559    unsigned Spacing;
6560    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6561    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6562    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6563                                            Spacing));
6564    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6565                                            Spacing * 2));
6566    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6567                                            Spacing * 3));
6568    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6569    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6570    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6571    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6572    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6573    TmpInst.addOperand(Inst.getOperand(4));
6574    Inst = TmpInst;
6575    return true;
6576  }
6577
6578  case ARM::VLD4DUPdWB_register_Asm_8:
6579  case ARM::VLD4DUPdWB_register_Asm_16:
6580  case ARM::VLD4DUPdWB_register_Asm_32:
6581  case ARM::VLD4DUPqWB_register_Asm_8:
6582  case ARM::VLD4DUPqWB_register_Asm_16:
6583  case ARM::VLD4DUPqWB_register_Asm_32: {
6584    MCInst TmpInst;
6585    unsigned Spacing;
6586    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6587    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6588    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6589                                            Spacing));
6590    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6591                                            Spacing * 2));
6592    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6593                                            Spacing * 3));
6594    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6595    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6596    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6597    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6598    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6599    TmpInst.addOperand(Inst.getOperand(5));
6600    Inst = TmpInst;
6601    return true;
6602  }
6603
6604  // VLD4 multiple 4-element structure instructions.
6605  case ARM::VLD4dAsm_8:
6606  case ARM::VLD4dAsm_16:
6607  case ARM::VLD4dAsm_32:
6608  case ARM::VLD4qAsm_8:
6609  case ARM::VLD4qAsm_16:
6610  case ARM::VLD4qAsm_32: {
6611    MCInst TmpInst;
6612    unsigned Spacing;
6613    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6614    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6615    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6616                                            Spacing));
6617    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6618                                            Spacing * 2));
6619    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6620                                            Spacing * 3));
6621    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6622    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6623    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6624    TmpInst.addOperand(Inst.getOperand(4));
6625    Inst = TmpInst;
6626    return true;
6627  }
6628
6629  case ARM::VLD4dWB_fixed_Asm_8:
6630  case ARM::VLD4dWB_fixed_Asm_16:
6631  case ARM::VLD4dWB_fixed_Asm_32:
6632  case ARM::VLD4qWB_fixed_Asm_8:
6633  case ARM::VLD4qWB_fixed_Asm_16:
6634  case ARM::VLD4qWB_fixed_Asm_32: {
6635    MCInst TmpInst;
6636    unsigned Spacing;
6637    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6638    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6639    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6640                                            Spacing));
6641    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6642                                            Spacing * 2));
6643    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6644                                            Spacing * 3));
6645    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6646    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6647    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6648    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6649    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6650    TmpInst.addOperand(Inst.getOperand(4));
6651    Inst = TmpInst;
6652    return true;
6653  }
6654
6655  case ARM::VLD4dWB_register_Asm_8:
6656  case ARM::VLD4dWB_register_Asm_16:
6657  case ARM::VLD4dWB_register_Asm_32:
6658  case ARM::VLD4qWB_register_Asm_8:
6659  case ARM::VLD4qWB_register_Asm_16:
6660  case ARM::VLD4qWB_register_Asm_32: {
6661    MCInst TmpInst;
6662    unsigned Spacing;
6663    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6664    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6665    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6666                                            Spacing));
6667    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6668                                            Spacing * 2));
6669    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6670                                            Spacing * 3));
6671    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6672    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6673    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6674    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6675    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6676    TmpInst.addOperand(Inst.getOperand(5));
6677    Inst = TmpInst;
6678    return true;
6679  }
6680
6681  // VST3 multiple 3-element structure instructions.
6682  case ARM::VST3dAsm_8:
6683  case ARM::VST3dAsm_16:
6684  case ARM::VST3dAsm_32:
6685  case ARM::VST3qAsm_8:
6686  case ARM::VST3qAsm_16:
6687  case ARM::VST3qAsm_32: {
6688    MCInst TmpInst;
6689    unsigned Spacing;
6690    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6691    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6692    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6693    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6694    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6695                                            Spacing));
6696    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6697                                            Spacing * 2));
6698    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6699    TmpInst.addOperand(Inst.getOperand(4));
6700    Inst = TmpInst;
6701    return true;
6702  }
6703
6704  case ARM::VST3dWB_fixed_Asm_8:
6705  case ARM::VST3dWB_fixed_Asm_16:
6706  case ARM::VST3dWB_fixed_Asm_32:
6707  case ARM::VST3qWB_fixed_Asm_8:
6708  case ARM::VST3qWB_fixed_Asm_16:
6709  case ARM::VST3qWB_fixed_Asm_32: {
6710    MCInst TmpInst;
6711    unsigned Spacing;
6712    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6713    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6714    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6715    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6716    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6717    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6718    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6719                                            Spacing));
6720    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6721                                            Spacing * 2));
6722    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6723    TmpInst.addOperand(Inst.getOperand(4));
6724    Inst = TmpInst;
6725    return true;
6726  }
6727
6728  case ARM::VST3dWB_register_Asm_8:
6729  case ARM::VST3dWB_register_Asm_16:
6730  case ARM::VST3dWB_register_Asm_32:
6731  case ARM::VST3qWB_register_Asm_8:
6732  case ARM::VST3qWB_register_Asm_16:
6733  case ARM::VST3qWB_register_Asm_32: {
6734    MCInst TmpInst;
6735    unsigned Spacing;
6736    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6737    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6738    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6739    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6740    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6741    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6742    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6743                                            Spacing));
6744    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6745                                            Spacing * 2));
6746    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6747    TmpInst.addOperand(Inst.getOperand(5));
6748    Inst = TmpInst;
6749    return true;
6750  }
6751
6752  // VST4 multiple 3-element structure instructions.
6753  case ARM::VST4dAsm_8:
6754  case ARM::VST4dAsm_16:
6755  case ARM::VST4dAsm_32:
6756  case ARM::VST4qAsm_8:
6757  case ARM::VST4qAsm_16:
6758  case ARM::VST4qAsm_32: {
6759    MCInst TmpInst;
6760    unsigned Spacing;
6761    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6762    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6763    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6764    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6765    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6766                                            Spacing));
6767    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6768                                            Spacing * 2));
6769    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6770                                            Spacing * 3));
6771    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6772    TmpInst.addOperand(Inst.getOperand(4));
6773    Inst = TmpInst;
6774    return true;
6775  }
6776
6777  case ARM::VST4dWB_fixed_Asm_8:
6778  case ARM::VST4dWB_fixed_Asm_16:
6779  case ARM::VST4dWB_fixed_Asm_32:
6780  case ARM::VST4qWB_fixed_Asm_8:
6781  case ARM::VST4qWB_fixed_Asm_16:
6782  case ARM::VST4qWB_fixed_Asm_32: {
6783    MCInst TmpInst;
6784    unsigned Spacing;
6785    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6786    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6787    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6788    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6789    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6790    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6791    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6792                                            Spacing));
6793    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6794                                            Spacing * 2));
6795    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6796                                            Spacing * 3));
6797    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6798    TmpInst.addOperand(Inst.getOperand(4));
6799    Inst = TmpInst;
6800    return true;
6801  }
6802
6803  case ARM::VST4dWB_register_Asm_8:
6804  case ARM::VST4dWB_register_Asm_16:
6805  case ARM::VST4dWB_register_Asm_32:
6806  case ARM::VST4qWB_register_Asm_8:
6807  case ARM::VST4qWB_register_Asm_16:
6808  case ARM::VST4qWB_register_Asm_32: {
6809    MCInst TmpInst;
6810    unsigned Spacing;
6811    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6812    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6813    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6814    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6815    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6816    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6817    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6818                                            Spacing));
6819    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6820                                            Spacing * 2));
6821    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6822                                            Spacing * 3));
6823    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6824    TmpInst.addOperand(Inst.getOperand(5));
6825    Inst = TmpInst;
6826    return true;
6827  }
6828
6829  // Handle encoding choice for the shift-immediate instructions.
6830  case ARM::t2LSLri:
6831  case ARM::t2LSRri:
6832  case ARM::t2ASRri: {
6833    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6834        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6835        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6836        !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6837         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6838      unsigned NewOpc;
6839      switch (Inst.getOpcode()) {
6840      default: llvm_unreachable("unexpected opcode");
6841      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6842      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6843      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6844      }
6845      // The Thumb1 operands aren't in the same order. Awesome, eh?
6846      MCInst TmpInst;
6847      TmpInst.setOpcode(NewOpc);
6848      TmpInst.addOperand(Inst.getOperand(0));
6849      TmpInst.addOperand(Inst.getOperand(5));
6850      TmpInst.addOperand(Inst.getOperand(1));
6851      TmpInst.addOperand(Inst.getOperand(2));
6852      TmpInst.addOperand(Inst.getOperand(3));
6853      TmpInst.addOperand(Inst.getOperand(4));
6854      Inst = TmpInst;
6855      return true;
6856    }
6857    return false;
6858  }
6859
6860  // Handle the Thumb2 mode MOV complex aliases.
6861  case ARM::t2MOVsr:
6862  case ARM::t2MOVSsr: {
6863    // Which instruction to expand to depends on the CCOut operand and
6864    // whether we're in an IT block if the register operands are low
6865    // registers.
6866    bool isNarrow = false;
6867    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6868        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6869        isARMLowRegister(Inst.getOperand(2).getReg()) &&
6870        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6871        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6872      isNarrow = true;
6873    MCInst TmpInst;
6874    unsigned newOpc;
6875    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6876    default: llvm_unreachable("unexpected opcode!");
6877    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6878    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6879    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6880    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
6881    }
6882    TmpInst.setOpcode(newOpc);
6883    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6884    if (isNarrow)
6885      TmpInst.addOperand(MCOperand::CreateReg(
6886          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6887    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6888    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6889    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6890    TmpInst.addOperand(Inst.getOperand(5));
6891    if (!isNarrow)
6892      TmpInst.addOperand(MCOperand::CreateReg(
6893          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6894    Inst = TmpInst;
6895    return true;
6896  }
6897  case ARM::t2MOVsi:
6898  case ARM::t2MOVSsi: {
6899    // Which instruction to expand to depends on the CCOut operand and
6900    // whether we're in an IT block if the register operands are low
6901    // registers.
6902    bool isNarrow = false;
6903    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6904        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6905        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6906      isNarrow = true;
6907    MCInst TmpInst;
6908    unsigned newOpc;
6909    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6910    default: llvm_unreachable("unexpected opcode!");
6911    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6912    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6913    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6914    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6915    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6916    }
6917    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6918    if (Amount == 32) Amount = 0;
6919    TmpInst.setOpcode(newOpc);
6920    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6921    if (isNarrow)
6922      TmpInst.addOperand(MCOperand::CreateReg(
6923          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6924    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6925    if (newOpc != ARM::t2RRX)
6926      TmpInst.addOperand(MCOperand::CreateImm(Amount));
6927    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6928    TmpInst.addOperand(Inst.getOperand(4));
6929    if (!isNarrow)
6930      TmpInst.addOperand(MCOperand::CreateReg(
6931          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6932    Inst = TmpInst;
6933    return true;
6934  }
6935  // Handle the ARM mode MOV complex aliases.
6936  case ARM::ASRr:
6937  case ARM::LSRr:
6938  case ARM::LSLr:
6939  case ARM::RORr: {
6940    ARM_AM::ShiftOpc ShiftTy;
6941    switch(Inst.getOpcode()) {
6942    default: llvm_unreachable("unexpected opcode!");
6943    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6944    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6945    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6946    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6947    }
6948    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6949    MCInst TmpInst;
6950    TmpInst.setOpcode(ARM::MOVsr);
6951    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6952    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6953    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6954    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6955    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6956    TmpInst.addOperand(Inst.getOperand(4));
6957    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6958    Inst = TmpInst;
6959    return true;
6960  }
6961  case ARM::ASRi:
6962  case ARM::LSRi:
6963  case ARM::LSLi:
6964  case ARM::RORi: {
6965    ARM_AM::ShiftOpc ShiftTy;
6966    switch(Inst.getOpcode()) {
6967    default: llvm_unreachable("unexpected opcode!");
6968    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6969    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6970    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6971    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6972    }
6973    // A shift by zero is a plain MOVr, not a MOVsi.
6974    unsigned Amt = Inst.getOperand(2).getImm();
6975    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6976    // A shift by 32 should be encoded as 0 when permitted
6977    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6978      Amt = 0;
6979    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6980    MCInst TmpInst;
6981    TmpInst.setOpcode(Opc);
6982    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6983    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6984    if (Opc == ARM::MOVsi)
6985      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6986    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6987    TmpInst.addOperand(Inst.getOperand(4));
6988    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6989    Inst = TmpInst;
6990    return true;
6991  }
6992  case ARM::RRXi: {
6993    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6994    MCInst TmpInst;
6995    TmpInst.setOpcode(ARM::MOVsi);
6996    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6997    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6998    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6999    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7000    TmpInst.addOperand(Inst.getOperand(3));
7001    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7002    Inst = TmpInst;
7003    return true;
7004  }
7005  case ARM::t2LDMIA_UPD: {
7006    // If this is a load of a single register, then we should use
7007    // a post-indexed LDR instruction instead, per the ARM ARM.
7008    if (Inst.getNumOperands() != 5)
7009      return false;
7010    MCInst TmpInst;
7011    TmpInst.setOpcode(ARM::t2LDR_POST);
7012    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7013    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7014    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7015    TmpInst.addOperand(MCOperand::CreateImm(4));
7016    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7017    TmpInst.addOperand(Inst.getOperand(3));
7018    Inst = TmpInst;
7019    return true;
7020  }
7021  case ARM::t2STMDB_UPD: {
7022    // If this is a store of a single register, then we should use
7023    // a pre-indexed STR instruction instead, per the ARM ARM.
7024    if (Inst.getNumOperands() != 5)
7025      return false;
7026    MCInst TmpInst;
7027    TmpInst.setOpcode(ARM::t2STR_PRE);
7028    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7029    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7030    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7031    TmpInst.addOperand(MCOperand::CreateImm(-4));
7032    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7033    TmpInst.addOperand(Inst.getOperand(3));
7034    Inst = TmpInst;
7035    return true;
7036  }
7037  case ARM::LDMIA_UPD:
7038    // If this is a load of a single register via a 'pop', then we should use
7039    // a post-indexed LDR instruction instead, per the ARM ARM.
7040    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7041        Inst.getNumOperands() == 5) {
7042      MCInst TmpInst;
7043      TmpInst.setOpcode(ARM::LDR_POST_IMM);
7044      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7045      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7046      TmpInst.addOperand(Inst.getOperand(1)); // Rn
7047      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7048      TmpInst.addOperand(MCOperand::CreateImm(4));
7049      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7050      TmpInst.addOperand(Inst.getOperand(3));
7051      Inst = TmpInst;
7052      return true;
7053    }
7054    break;
7055  case ARM::STMDB_UPD:
7056    // If this is a store of a single register via a 'push', then we should use
7057    // a pre-indexed STR instruction instead, per the ARM ARM.
7058    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7059        Inst.getNumOperands() == 5) {
7060      MCInst TmpInst;
7061      TmpInst.setOpcode(ARM::STR_PRE_IMM);
7062      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7063      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7064      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7065      TmpInst.addOperand(MCOperand::CreateImm(-4));
7066      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7067      TmpInst.addOperand(Inst.getOperand(3));
7068      Inst = TmpInst;
7069    }
7070    break;
7071  case ARM::t2ADDri12:
7072    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7073    // mnemonic was used (not "addw"), encoding T3 is preferred.
7074    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7075        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7076      break;
7077    Inst.setOpcode(ARM::t2ADDri);
7078    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7079    break;
7080  case ARM::t2SUBri12:
7081    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7082    // mnemonic was used (not "subw"), encoding T3 is preferred.
7083    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7084        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7085      break;
7086    Inst.setOpcode(ARM::t2SUBri);
7087    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7088    break;
7089  case ARM::tADDi8:
7090    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7091    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7092    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7093    // to encoding T1 if <Rd> is omitted."
7094    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7095      Inst.setOpcode(ARM::tADDi3);
7096      return true;
7097    }
7098    break;
7099  case ARM::tSUBi8:
7100    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7101    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7102    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7103    // to encoding T1 if <Rd> is omitted."
7104    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7105      Inst.setOpcode(ARM::tSUBi3);
7106      return true;
7107    }
7108    break;
7109  case ARM::t2ADDri:
7110  case ARM::t2SUBri: {
7111    // If the destination and first source operand are the same, and
7112    // the flags are compatible with the current IT status, use encoding T2
7113    // instead of T3. For compatibility with the system 'as'. Make sure the
7114    // wide encoding wasn't explicit.
7115    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7116        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7117        (unsigned)Inst.getOperand(2).getImm() > 255 ||
7118        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7119        (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7120        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7121         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7122      break;
7123    MCInst TmpInst;
7124    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7125                      ARM::tADDi8 : ARM::tSUBi8);
7126    TmpInst.addOperand(Inst.getOperand(0));
7127    TmpInst.addOperand(Inst.getOperand(5));
7128    TmpInst.addOperand(Inst.getOperand(0));
7129    TmpInst.addOperand(Inst.getOperand(2));
7130    TmpInst.addOperand(Inst.getOperand(3));
7131    TmpInst.addOperand(Inst.getOperand(4));
7132    Inst = TmpInst;
7133    return true;
7134  }
7135  case ARM::t2ADDrr: {
7136    // If the destination and first source operand are the same, and
7137    // there's no setting of the flags, use encoding T2 instead of T3.
7138    // Note that this is only for ADD, not SUB. This mirrors the system
7139    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7140    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7141        Inst.getOperand(5).getReg() != 0 ||
7142        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7143         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7144      break;
7145    MCInst TmpInst;
7146    TmpInst.setOpcode(ARM::tADDhirr);
7147    TmpInst.addOperand(Inst.getOperand(0));
7148    TmpInst.addOperand(Inst.getOperand(0));
7149    TmpInst.addOperand(Inst.getOperand(2));
7150    TmpInst.addOperand(Inst.getOperand(3));
7151    TmpInst.addOperand(Inst.getOperand(4));
7152    Inst = TmpInst;
7153    return true;
7154  }
7155  case ARM::tADDrSP: {
7156    // If the non-SP source operand and the destination operand are not the
7157    // same, we need to use the 32-bit encoding if it's available.
7158    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7159      Inst.setOpcode(ARM::t2ADDrr);
7160      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7161      return true;
7162    }
7163    break;
7164  }
7165  case ARM::tB:
7166    // A Thumb conditional branch outside of an IT block is a tBcc.
7167    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7168      Inst.setOpcode(ARM::tBcc);
7169      return true;
7170    }
7171    break;
7172  case ARM::t2B:
7173    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7174    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7175      Inst.setOpcode(ARM::t2Bcc);
7176      return true;
7177    }
7178    break;
7179  case ARM::t2Bcc:
7180    // If the conditional is AL or we're in an IT block, we really want t2B.
7181    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7182      Inst.setOpcode(ARM::t2B);
7183      return true;
7184    }
7185    break;
7186  case ARM::tBcc:
7187    // If the conditional is AL, we really want tB.
7188    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7189      Inst.setOpcode(ARM::tB);
7190      return true;
7191    }
7192    break;
7193  case ARM::tLDMIA: {
7194    // If the register list contains any high registers, or if the writeback
7195    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7196    // instead if we're in Thumb2. Otherwise, this should have generated
7197    // an error in validateInstruction().
7198    unsigned Rn = Inst.getOperand(0).getReg();
7199    bool hasWritebackToken =
7200      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7201       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7202    bool listContainsBase;
7203    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7204        (!listContainsBase && !hasWritebackToken) ||
7205        (listContainsBase && hasWritebackToken)) {
7206      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7207      assert (isThumbTwo());
7208      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7209      // If we're switching to the updating version, we need to insert
7210      // the writeback tied operand.
7211      if (hasWritebackToken)
7212        Inst.insert(Inst.begin(),
7213                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7214      return true;
7215    }
7216    break;
7217  }
7218  case ARM::tSTMIA_UPD: {
7219    // If the register list contains any high registers, we need to use
7220    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7221    // should have generated an error in validateInstruction().
7222    unsigned Rn = Inst.getOperand(0).getReg();
7223    bool listContainsBase;
7224    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7225      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7226      assert (isThumbTwo());
7227      Inst.setOpcode(ARM::t2STMIA_UPD);
7228      return true;
7229    }
7230    break;
7231  }
7232  case ARM::tPOP: {
7233    bool listContainsBase;
7234    // If the register list contains any high registers, we need to use
7235    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7236    // should have generated an error in validateInstruction().
7237    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7238      return false;
7239    assert (isThumbTwo());
7240    Inst.setOpcode(ARM::t2LDMIA_UPD);
7241    // Add the base register and writeback operands.
7242    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7243    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7244    return true;
7245  }
7246  case ARM::tPUSH: {
7247    bool listContainsBase;
7248    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7249      return false;
7250    assert (isThumbTwo());
7251    Inst.setOpcode(ARM::t2STMDB_UPD);
7252    // Add the base register and writeback operands.
7253    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7254    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7255    return true;
7256  }
7257  case ARM::t2MOVi: {
7258    // If we can use the 16-bit encoding and the user didn't explicitly
7259    // request the 32-bit variant, transform it here.
7260    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7261        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7262        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7263         Inst.getOperand(4).getReg() == ARM::CPSR) ||
7264        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7265        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7266         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7267      // The operands aren't in the same order for tMOVi8...
7268      MCInst TmpInst;
7269      TmpInst.setOpcode(ARM::tMOVi8);
7270      TmpInst.addOperand(Inst.getOperand(0));
7271      TmpInst.addOperand(Inst.getOperand(4));
7272      TmpInst.addOperand(Inst.getOperand(1));
7273      TmpInst.addOperand(Inst.getOperand(2));
7274      TmpInst.addOperand(Inst.getOperand(3));
7275      Inst = TmpInst;
7276      return true;
7277    }
7278    break;
7279  }
7280  case ARM::t2MOVr: {
7281    // If we can use the 16-bit encoding and the user didn't explicitly
7282    // request the 32-bit variant, transform it here.
7283    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7284        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7285        Inst.getOperand(2).getImm() == ARMCC::AL &&
7286        Inst.getOperand(4).getReg() == ARM::CPSR &&
7287        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7288         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7289      // The operands aren't the same for tMOV[S]r... (no cc_out)
7290      MCInst TmpInst;
7291      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7292      TmpInst.addOperand(Inst.getOperand(0));
7293      TmpInst.addOperand(Inst.getOperand(1));
7294      TmpInst.addOperand(Inst.getOperand(2));
7295      TmpInst.addOperand(Inst.getOperand(3));
7296      Inst = TmpInst;
7297      return true;
7298    }
7299    break;
7300  }
7301  case ARM::t2SXTH:
7302  case ARM::t2SXTB:
7303  case ARM::t2UXTH:
7304  case ARM::t2UXTB: {
7305    // If we can use the 16-bit encoding and the user didn't explicitly
7306    // request the 32-bit variant, transform it here.
7307    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7308        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7309        Inst.getOperand(2).getImm() == 0 &&
7310        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7311         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7312      unsigned NewOpc;
7313      switch (Inst.getOpcode()) {
7314      default: llvm_unreachable("Illegal opcode!");
7315      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7316      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7317      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7318      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7319      }
7320      // The operands aren't the same for thumb1 (no rotate operand).
7321      MCInst TmpInst;
7322      TmpInst.setOpcode(NewOpc);
7323      TmpInst.addOperand(Inst.getOperand(0));
7324      TmpInst.addOperand(Inst.getOperand(1));
7325      TmpInst.addOperand(Inst.getOperand(3));
7326      TmpInst.addOperand(Inst.getOperand(4));
7327      Inst = TmpInst;
7328      return true;
7329    }
7330    break;
7331  }
7332  case ARM::MOVsi: {
7333    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7334    // rrx shifts and asr/lsr of #32 is encoded as 0
7335    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7336      return false;
7337    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7338      // Shifting by zero is accepted as a vanilla 'MOVr'
7339      MCInst TmpInst;
7340      TmpInst.setOpcode(ARM::MOVr);
7341      TmpInst.addOperand(Inst.getOperand(0));
7342      TmpInst.addOperand(Inst.getOperand(1));
7343      TmpInst.addOperand(Inst.getOperand(3));
7344      TmpInst.addOperand(Inst.getOperand(4));
7345      TmpInst.addOperand(Inst.getOperand(5));
7346      Inst = TmpInst;
7347      return true;
7348    }
7349    return false;
7350  }
7351  case ARM::ANDrsi:
7352  case ARM::ORRrsi:
7353  case ARM::EORrsi:
7354  case ARM::BICrsi:
7355  case ARM::SUBrsi:
7356  case ARM::ADDrsi: {
7357    unsigned newOpc;
7358    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7359    if (SOpc == ARM_AM::rrx) return false;
7360    switch (Inst.getOpcode()) {
7361    default: llvm_unreachable("unexpected opcode!");
7362    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7363    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7364    case ARM::EORrsi: newOpc = ARM::EORrr; break;
7365    case ARM::BICrsi: newOpc = ARM::BICrr; break;
7366    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7367    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7368    }
7369    // If the shift is by zero, use the non-shifted instruction definition.
7370    // The exception is for right shifts, where 0 == 32
7371    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7372        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7373      MCInst TmpInst;
7374      TmpInst.setOpcode(newOpc);
7375      TmpInst.addOperand(Inst.getOperand(0));
7376      TmpInst.addOperand(Inst.getOperand(1));
7377      TmpInst.addOperand(Inst.getOperand(2));
7378      TmpInst.addOperand(Inst.getOperand(4));
7379      TmpInst.addOperand(Inst.getOperand(5));
7380      TmpInst.addOperand(Inst.getOperand(6));
7381      Inst = TmpInst;
7382      return true;
7383    }
7384    return false;
7385  }
7386  case ARM::ITasm:
7387  case ARM::t2IT: {
7388    // The mask bits for all but the first condition are represented as
7389    // the low bit of the condition code value implies 't'. We currently
7390    // always have 1 implies 't', so XOR toggle the bits if the low bit
7391    // of the condition code is zero.
7392    MCOperand &MO = Inst.getOperand(1);
7393    unsigned Mask = MO.getImm();
7394    unsigned OrigMask = Mask;
7395    unsigned TZ = CountTrailingZeros_32(Mask);
7396    if ((Inst.getOperand(0).getImm() & 1) == 0) {
7397      assert(Mask && TZ <= 3 && "illegal IT mask value!");
7398      for (unsigned i = 3; i != TZ; --i)
7399        Mask ^= 1 << i;
7400    }
7401    MO.setImm(Mask);
7402
7403    // Set up the IT block state according to the IT instruction we just
7404    // matched.
7405    assert(!inITBlock() && "nested IT blocks?!");
7406    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7407    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7408    ITState.CurPosition = 0;
7409    ITState.FirstCond = true;
7410    break;
7411  }
7412  case ARM::t2LSLrr:
7413  case ARM::t2LSRrr:
7414  case ARM::t2ASRrr:
7415  case ARM::t2SBCrr:
7416  case ARM::t2RORrr:
7417  case ARM::t2BICrr:
7418  {
7419    // Assemblers should use the narrow encodings of these instructions when permissible.
7420    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7421         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7422        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7423        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7424         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7425        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7426         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7427      unsigned NewOpc;
7428      switch (Inst.getOpcode()) {
7429        default: llvm_unreachable("unexpected opcode");
7430        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7431        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7432        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7433        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7434        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7435        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7436      }
7437      MCInst TmpInst;
7438      TmpInst.setOpcode(NewOpc);
7439      TmpInst.addOperand(Inst.getOperand(0));
7440      TmpInst.addOperand(Inst.getOperand(5));
7441      TmpInst.addOperand(Inst.getOperand(1));
7442      TmpInst.addOperand(Inst.getOperand(2));
7443      TmpInst.addOperand(Inst.getOperand(3));
7444      TmpInst.addOperand(Inst.getOperand(4));
7445      Inst = TmpInst;
7446      return true;
7447    }
7448    return false;
7449  }
7450  case ARM::t2ANDrr:
7451  case ARM::t2EORrr:
7452  case ARM::t2ADCrr:
7453  case ARM::t2ORRrr:
7454  {
7455    // Assemblers should use the narrow encodings of these instructions when permissible.
7456    // These instructions are special in that they are commutable, so shorter encodings
7457    // are available more often.
7458    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7459         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7460        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7461         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7462        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7463         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7464        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7465         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7466      unsigned NewOpc;
7467      switch (Inst.getOpcode()) {
7468        default: llvm_unreachable("unexpected opcode");
7469        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7470        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7471        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7472        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7473      }
7474      MCInst TmpInst;
7475      TmpInst.setOpcode(NewOpc);
7476      TmpInst.addOperand(Inst.getOperand(0));
7477      TmpInst.addOperand(Inst.getOperand(5));
7478      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7479        TmpInst.addOperand(Inst.getOperand(1));
7480        TmpInst.addOperand(Inst.getOperand(2));
7481      } else {
7482        TmpInst.addOperand(Inst.getOperand(2));
7483        TmpInst.addOperand(Inst.getOperand(1));
7484      }
7485      TmpInst.addOperand(Inst.getOperand(3));
7486      TmpInst.addOperand(Inst.getOperand(4));
7487      Inst = TmpInst;
7488      return true;
7489    }
7490    return false;
7491  }
7492  }
7493  return false;
7494}
7495
7496unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7497  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7498  // suffix depending on whether they're in an IT block or not.
7499  unsigned Opc = Inst.getOpcode();
7500  const MCInstrDesc &MCID = getInstDesc(Opc);
7501  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7502    assert(MCID.hasOptionalDef() &&
7503           "optionally flag setting instruction missing optional def operand");
7504    assert(MCID.NumOperands == Inst.getNumOperands() &&
7505           "operand count mismatch!");
7506    // Find the optional-def operand (cc_out).
7507    unsigned OpNo;
7508    for (OpNo = 0;
7509         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7510         ++OpNo)
7511      ;
7512    // If we're parsing Thumb1, reject it completely.
7513    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7514      return Match_MnemonicFail;
7515    // If we're parsing Thumb2, which form is legal depends on whether we're
7516    // in an IT block.
7517    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7518        !inITBlock())
7519      return Match_RequiresITBlock;
7520    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7521        inITBlock())
7522      return Match_RequiresNotITBlock;
7523  }
7524  // Some high-register supporting Thumb1 encodings only allow both registers
7525  // to be from r0-r7 when in Thumb2.
7526  else if (Opc == ARM::tADDhirr && isThumbOne() &&
7527           isARMLowRegister(Inst.getOperand(1).getReg()) &&
7528           isARMLowRegister(Inst.getOperand(2).getReg()))
7529    return Match_RequiresThumb2;
7530  // Others only require ARMv6 or later.
7531  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7532           isARMLowRegister(Inst.getOperand(0).getReg()) &&
7533           isARMLowRegister(Inst.getOperand(1).getReg()))
7534    return Match_RequiresV6;
7535  return Match_Success;
7536}
7537
7538static const char *getSubtargetFeatureName(unsigned Val);
7539bool ARMAsmParser::
7540MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7541                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7542                        MCStreamer &Out, unsigned &ErrorInfo,
7543                        bool MatchingInlineAsm) {
7544  MCInst Inst;
7545  unsigned MatchResult;
7546
7547  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7548                                     MatchingInlineAsm);
7549  switch (MatchResult) {
7550  default: break;
7551  case Match_Success:
7552    // Context sensitive operand constraints aren't handled by the matcher,
7553    // so check them here.
7554    if (validateInstruction(Inst, Operands)) {
7555      // Still progress the IT block, otherwise one wrong condition causes
7556      // nasty cascading errors.
7557      forwardITPosition();
7558      return true;
7559    }
7560
7561    // Some instructions need post-processing to, for example, tweak which
7562    // encoding is selected. Loop on it while changes happen so the
7563    // individual transformations can chain off each other. E.g.,
7564    // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7565    while (processInstruction(Inst, Operands))
7566      ;
7567
7568    // Only move forward at the very end so that everything in validate
7569    // and process gets a consistent answer about whether we're in an IT
7570    // block.
7571    forwardITPosition();
7572
7573    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7574    // doesn't actually encode.
7575    if (Inst.getOpcode() == ARM::ITasm)
7576      return false;
7577
7578    Inst.setLoc(IDLoc);
7579    Out.EmitInstruction(Inst);
7580    return false;
7581  case Match_MissingFeature: {
7582    assert(ErrorInfo && "Unknown missing feature!");
7583    // Special case the error message for the very common case where only
7584    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7585    std::string Msg = "instruction requires:";
7586    unsigned Mask = 1;
7587    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7588      if (ErrorInfo & Mask) {
7589        Msg += " ";
7590        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7591      }
7592      Mask <<= 1;
7593    }
7594    return Error(IDLoc, Msg);
7595  }
7596  case Match_InvalidOperand: {
7597    SMLoc ErrorLoc = IDLoc;
7598    if (ErrorInfo != ~0U) {
7599      if (ErrorInfo >= Operands.size())
7600        return Error(IDLoc, "too few operands for instruction");
7601
7602      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7603      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7604    }
7605
7606    return Error(ErrorLoc, "invalid operand for instruction");
7607  }
7608  case Match_MnemonicFail:
7609    return Error(IDLoc, "invalid instruction",
7610                 ((ARMOperand*)Operands[0])->getLocRange());
7611  case Match_RequiresNotITBlock:
7612    return Error(IDLoc, "flag setting instruction only valid outside IT block");
7613  case Match_RequiresITBlock:
7614    return Error(IDLoc, "instruction only valid inside IT block");
7615  case Match_RequiresV6:
7616    return Error(IDLoc, "instruction variant requires ARMv6 or later");
7617  case Match_RequiresThumb2:
7618    return Error(IDLoc, "instruction variant requires Thumb2");
7619  case Match_ImmRange0_15: {
7620    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7621    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7622    return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7623  }
7624  }
7625
7626  llvm_unreachable("Implement any new match types added!");
7627}
7628
7629/// parseDirective parses the arm specific directives
7630bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7631  StringRef IDVal = DirectiveID.getIdentifier();
7632  if (IDVal == ".word")
7633    return parseDirectiveWord(4, DirectiveID.getLoc());
7634  else if (IDVal == ".thumb")
7635    return parseDirectiveThumb(DirectiveID.getLoc());
7636  else if (IDVal == ".arm")
7637    return parseDirectiveARM(DirectiveID.getLoc());
7638  else if (IDVal == ".thumb_func")
7639    return parseDirectiveThumbFunc(DirectiveID.getLoc());
7640  else if (IDVal == ".code")
7641    return parseDirectiveCode(DirectiveID.getLoc());
7642  else if (IDVal == ".syntax")
7643    return parseDirectiveSyntax(DirectiveID.getLoc());
7644  else if (IDVal == ".unreq")
7645    return parseDirectiveUnreq(DirectiveID.getLoc());
7646  else if (IDVal == ".arch")
7647    return parseDirectiveArch(DirectiveID.getLoc());
7648  else if (IDVal == ".eabi_attribute")
7649    return parseDirectiveEabiAttr(DirectiveID.getLoc());
7650  return true;
7651}
7652
7653/// parseDirectiveWord
7654///  ::= .word [ expression (, expression)* ]
7655bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7656  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7657    for (;;) {
7658      const MCExpr *Value;
7659      if (getParser().ParseExpression(Value))
7660        return true;
7661
7662      getParser().getStreamer().EmitValue(Value, Size);
7663
7664      if (getLexer().is(AsmToken::EndOfStatement))
7665        break;
7666
7667      // FIXME: Improve diagnostic.
7668      if (getLexer().isNot(AsmToken::Comma))
7669        return Error(L, "unexpected token in directive");
7670      Parser.Lex();
7671    }
7672  }
7673
7674  Parser.Lex();
7675  return false;
7676}
7677
7678/// parseDirectiveThumb
7679///  ::= .thumb
7680bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7681  if (getLexer().isNot(AsmToken::EndOfStatement))
7682    return Error(L, "unexpected token in directive");
7683  Parser.Lex();
7684
7685  if (!isThumb())
7686    SwitchMode();
7687  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7688  return false;
7689}
7690
7691/// parseDirectiveARM
7692///  ::= .arm
7693bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7694  if (getLexer().isNot(AsmToken::EndOfStatement))
7695    return Error(L, "unexpected token in directive");
7696  Parser.Lex();
7697
7698  if (isThumb())
7699    SwitchMode();
7700  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7701  return false;
7702}
7703
7704/// parseDirectiveThumbFunc
7705///  ::= .thumbfunc symbol_name
7706bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7707  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7708  bool isMachO = MAI.hasSubsectionsViaSymbols();
7709  StringRef Name;
7710  bool needFuncName = true;
7711
7712  // Darwin asm has (optionally) function name after .thumb_func direction
7713  // ELF doesn't
7714  if (isMachO) {
7715    const AsmToken &Tok = Parser.getTok();
7716    if (Tok.isNot(AsmToken::EndOfStatement)) {
7717      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7718        return Error(L, "unexpected token in .thumb_func directive");
7719      Name = Tok.getIdentifier();
7720      Parser.Lex(); // Consume the identifier token.
7721      needFuncName = false;
7722    }
7723  }
7724
7725  if (getLexer().isNot(AsmToken::EndOfStatement))
7726    return Error(L, "unexpected token in directive");
7727
7728  // Eat the end of statement and any blank lines that follow.
7729  while (getLexer().is(AsmToken::EndOfStatement))
7730    Parser.Lex();
7731
7732  // FIXME: assuming function name will be the line following .thumb_func
7733  // We really should be checking the next symbol definition even if there's
7734  // stuff in between.
7735  if (needFuncName) {
7736    Name = Parser.getTok().getIdentifier();
7737  }
7738
7739  // Mark symbol as a thumb symbol.
7740  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7741  getParser().getStreamer().EmitThumbFunc(Func);
7742  return false;
7743}
7744
7745/// parseDirectiveSyntax
7746///  ::= .syntax unified | divided
7747bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7748  const AsmToken &Tok = Parser.getTok();
7749  if (Tok.isNot(AsmToken::Identifier))
7750    return Error(L, "unexpected token in .syntax directive");
7751  StringRef Mode = Tok.getString();
7752  if (Mode == "unified" || Mode == "UNIFIED")
7753    Parser.Lex();
7754  else if (Mode == "divided" || Mode == "DIVIDED")
7755    return Error(L, "'.syntax divided' arm asssembly not supported");
7756  else
7757    return Error(L, "unrecognized syntax mode in .syntax directive");
7758
7759  if (getLexer().isNot(AsmToken::EndOfStatement))
7760    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7761  Parser.Lex();
7762
7763  // TODO tell the MC streamer the mode
7764  // getParser().getStreamer().Emit???();
7765  return false;
7766}
7767
7768/// parseDirectiveCode
7769///  ::= .code 16 | 32
7770bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7771  const AsmToken &Tok = Parser.getTok();
7772  if (Tok.isNot(AsmToken::Integer))
7773    return Error(L, "unexpected token in .code directive");
7774  int64_t Val = Parser.getTok().getIntVal();
7775  if (Val == 16)
7776    Parser.Lex();
7777  else if (Val == 32)
7778    Parser.Lex();
7779  else
7780    return Error(L, "invalid operand to .code directive");
7781
7782  if (getLexer().isNot(AsmToken::EndOfStatement))
7783    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7784  Parser.Lex();
7785
7786  if (Val == 16) {
7787    if (!isThumb())
7788      SwitchMode();
7789    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7790  } else {
7791    if (isThumb())
7792      SwitchMode();
7793    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7794  }
7795
7796  return false;
7797}
7798
7799/// parseDirectiveReq
7800///  ::= name .req registername
7801bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7802  Parser.Lex(); // Eat the '.req' token.
7803  unsigned Reg;
7804  SMLoc SRegLoc, ERegLoc;
7805  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7806    Parser.EatToEndOfStatement();
7807    return Error(SRegLoc, "register name expected");
7808  }
7809
7810  // Shouldn't be anything else.
7811  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7812    Parser.EatToEndOfStatement();
7813    return Error(Parser.getTok().getLoc(),
7814                 "unexpected input in .req directive.");
7815  }
7816
7817  Parser.Lex(); // Consume the EndOfStatement
7818
7819  if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7820    return Error(SRegLoc, "redefinition of '" + Name +
7821                          "' does not match original.");
7822
7823  return false;
7824}
7825
7826/// parseDirectiveUneq
7827///  ::= .unreq registername
7828bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7829  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7830    Parser.EatToEndOfStatement();
7831    return Error(L, "unexpected input in .unreq directive.");
7832  }
7833  RegisterReqs.erase(Parser.getTok().getIdentifier());
7834  Parser.Lex(); // Eat the identifier.
7835  return false;
7836}
7837
7838/// parseDirectiveArch
7839///  ::= .arch token
7840bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7841  return true;
7842}
7843
7844/// parseDirectiveEabiAttr
7845///  ::= .eabi_attribute int, int
7846bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7847  return true;
7848}
7849
7850/// Force static initialization.
7851extern "C" void LLVMInitializeARMAsmParser() {
7852  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7853  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7854}
7855
7856#define GET_REGISTER_MATCHER
7857#define GET_SUBTARGET_FEATURE_NAME
7858#define GET_MATCHER_IMPLEMENTATION
7859#include "ARMGenAsmMatcher.inc"
7860