ARMAsmParser.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "ARMFPUName.h" 11#include "ARMFeatures.h" 12#include "MCTargetDesc/ARMAddressingModes.h" 13#include "MCTargetDesc/ARMArchName.h" 14#include "MCTargetDesc/ARMBaseInfo.h" 15#include "MCTargetDesc/ARMMCExpr.h" 16#include "llvm/ADT/OwningPtr.h" 17#include "llvm/ADT/STLExtras.h" 18#include "llvm/ADT/SmallVector.h" 19#include "llvm/ADT/StringExtras.h" 20#include "llvm/ADT/StringSwitch.h" 21#include "llvm/ADT/Twine.h" 22#include "llvm/MC/MCAsmInfo.h" 23#include "llvm/MC/MCAssembler.h" 24#include "llvm/MC/MCContext.h" 25#include "llvm/MC/MCDisassembler.h" 26#include "llvm/MC/MCELF.h" 27#include "llvm/MC/MCELFStreamer.h" 28#include "llvm/MC/MCELFSymbolFlags.h" 29#include "llvm/MC/MCExpr.h" 30#include "llvm/MC/MCInst.h" 31#include "llvm/MC/MCInstrDesc.h" 32#include "llvm/MC/MCInstrInfo.h" 33#include "llvm/MC/MCObjectFileInfo.h" 34#include "llvm/MC/MCParser/MCAsmLexer.h" 35#include "llvm/MC/MCParser/MCAsmParser.h" 36#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 37#include "llvm/MC/MCRegisterInfo.h" 38#include "llvm/MC/MCSection.h" 39#include "llvm/MC/MCStreamer.h" 40#include "llvm/MC/MCSubtargetInfo.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/MC/MCTargetAsmParser.h" 43#include "llvm/Support/ARMBuildAttributes.h" 44#include "llvm/Support/ARMEHABI.h" 45#include "llvm/Support/COFF.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/ELF.h" 48#include "llvm/Support/MathExtras.h" 49#include "llvm/Support/SourceMgr.h" 50#include "llvm/Support/TargetRegistry.h" 51#include "llvm/Support/raw_ostream.h" 52 53using namespace llvm; 54 55namespace { 56 57class ARMOperand; 58 59enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 60 61class UnwindContext { 62 MCAsmParser &Parser; 63 64 typedef SmallVector<SMLoc, 4> Locs; 65 66 Locs FnStartLocs; 67 Locs CantUnwindLocs; 68 Locs PersonalityLocs; 69 Locs PersonalityIndexLocs; 70 Locs HandlerDataLocs; 71 int FPReg; 72 73public: 74 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} 75 76 bool hasFnStart() const { return !FnStartLocs.empty(); } 77 bool cantUnwind() const { return !CantUnwindLocs.empty(); } 78 bool hasHandlerData() const { return !HandlerDataLocs.empty(); } 79 bool hasPersonality() const { 80 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty()); 81 } 82 83 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); } 84 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); } 85 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); } 86 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); } 87 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); } 88 89 void saveFPReg(int Reg) { FPReg = Reg; } 90 int getFPReg() const { return FPReg; } 91 92 void emitFnStartLocNotes() const { 93 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end(); 94 FI != FE; ++FI) 95 Parser.Note(*FI, ".fnstart was specified here"); 96 } 97 void emitCantUnwindLocNotes() const { 98 for (Locs::const_iterator UI = CantUnwindLocs.begin(), 99 UE = CantUnwindLocs.end(); UI != UE; ++UI) 100 Parser.Note(*UI, ".cantunwind was specified here"); 101 } 102 void emitHandlerDataLocNotes() const { 103 for (Locs::const_iterator HI = HandlerDataLocs.begin(), 104 HE = HandlerDataLocs.end(); HI != HE; ++HI) 105 Parser.Note(*HI, ".handlerdata was specified here"); 106 } 107 void emitPersonalityLocNotes() const { 108 for (Locs::const_iterator PI = PersonalityLocs.begin(), 109 PE = PersonalityLocs.end(), 110 PII = PersonalityIndexLocs.begin(), 111 PIE = PersonalityIndexLocs.end(); 112 PI != PE || PII != PIE;) { 113 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) 114 Parser.Note(*PI++, ".personality was specified here"); 115 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer())) 116 Parser.Note(*PII++, ".personalityindex was specified here"); 117 else 118 llvm_unreachable(".personality and .personalityindex cannot be " 119 "at the same location"); 120 } 121 } 122 123 void reset() { 124 FnStartLocs = Locs(); 125 CantUnwindLocs = Locs(); 126 PersonalityLocs = Locs(); 127 HandlerDataLocs = Locs(); 128 PersonalityIndexLocs = Locs(); 129 FPReg = ARM::SP; 130 } 131}; 132 133class ARMAsmParser : public MCTargetAsmParser { 134 MCSubtargetInfo &STI; 135 MCAsmParser &Parser; 136 const MCInstrInfo &MII; 137 const MCRegisterInfo *MRI; 138 UnwindContext UC; 139 140 ARMTargetStreamer &getTargetStreamer() { 141 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); 142 return static_cast<ARMTargetStreamer &>(TS); 143 } 144 145 // Map of register aliases registers via the .req directive. 146 StringMap<unsigned> RegisterReqs; 147 148 bool NextSymbolIsThumb; 149 150 struct { 151 ARMCC::CondCodes Cond; // Condition for IT block. 152 unsigned Mask:4; // Condition mask for instructions. 153 // Starting at first 1 (from lsb). 154 // '1' condition as indicated in IT. 155 // '0' inverse of condition (else). 156 // Count of instructions in IT block is 157 // 4 - trailingzeroes(mask) 158 159 bool FirstCond; // Explicit flag for when we're parsing the 160 // First instruction in the IT block. It's 161 // implied in the mask, so needs special 162 // handling. 163 164 unsigned CurPosition; // Current position in parsing of IT 165 // block. In range [0,3]. Initialized 166 // according to count of instructions in block. 167 // ~0U if no active IT block. 168 } ITState; 169 bool inITBlock() { return ITState.CurPosition != ~0U;} 170 void forwardITPosition() { 171 if (!inITBlock()) return; 172 // Move to the next instruction in the IT block, if there is one. If not, 173 // mark the block as done. 174 unsigned TZ = countTrailingZeros(ITState.Mask); 175 if (++ITState.CurPosition == 5 - TZ) 176 ITState.CurPosition = ~0U; // Done with the IT block after this. 177 } 178 179 180 MCAsmParser &getParser() const { return Parser; } 181 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 182 183 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) { 184 return Parser.Note(L, Msg, Ranges); 185 } 186 bool Warning(SMLoc L, const Twine &Msg, 187 ArrayRef<SMRange> Ranges = None) { 188 return Parser.Warning(L, Msg, Ranges); 189 } 190 bool Error(SMLoc L, const Twine &Msg, 191 ArrayRef<SMRange> Ranges = None) { 192 return Parser.Error(L, Msg, Ranges); 193 } 194 195 int tryParseRegister(); 196 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 197 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 198 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 199 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 200 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 201 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 202 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 203 unsigned &ShiftAmount); 204 bool parseLiteralValues(unsigned Size, SMLoc L); 205 bool parseDirectiveThumb(SMLoc L); 206 bool parseDirectiveARM(SMLoc L); 207 bool parseDirectiveThumbFunc(SMLoc L); 208 bool parseDirectiveCode(SMLoc L); 209 bool parseDirectiveSyntax(SMLoc L); 210 bool parseDirectiveReq(StringRef Name, SMLoc L); 211 bool parseDirectiveUnreq(SMLoc L); 212 bool parseDirectiveArch(SMLoc L); 213 bool parseDirectiveEabiAttr(SMLoc L); 214 bool parseDirectiveCPU(SMLoc L); 215 bool parseDirectiveFPU(SMLoc L); 216 bool parseDirectiveFnStart(SMLoc L); 217 bool parseDirectiveFnEnd(SMLoc L); 218 bool parseDirectiveCantUnwind(SMLoc L); 219 bool parseDirectivePersonality(SMLoc L); 220 bool parseDirectiveHandlerData(SMLoc L); 221 bool parseDirectiveSetFP(SMLoc L); 222 bool parseDirectivePad(SMLoc L); 223 bool parseDirectiveRegSave(SMLoc L, bool IsVector); 224 bool parseDirectiveInst(SMLoc L, char Suffix = '\0'); 225 bool parseDirectiveLtorg(SMLoc L); 226 bool parseDirectiveEven(SMLoc L); 227 bool parseDirectivePersonalityIndex(SMLoc L); 228 bool parseDirectiveUnwindRaw(SMLoc L); 229 bool parseDirectiveTLSDescSeq(SMLoc L); 230 bool parseDirectiveMovSP(SMLoc L); 231 bool parseDirectiveObjectArch(SMLoc L); 232 bool parseDirectiveArchExtension(SMLoc L); 233 bool parseDirectiveAlign(SMLoc L); 234 bool parseDirectiveThumbSet(SMLoc L); 235 236 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 237 bool &CarrySetting, unsigned &ProcessorIMod, 238 StringRef &ITMask); 239 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 240 bool &CanAcceptCarrySet, 241 bool &CanAcceptPredicationCode); 242 243 bool isThumb() const { 244 // FIXME: Can tablegen auto-generate this? 245 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 246 } 247 bool isThumbOne() const { 248 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 249 } 250 bool isThumbTwo() const { 251 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 252 } 253 bool hasThumb() const { 254 return STI.getFeatureBits() & ARM::HasV4TOps; 255 } 256 bool hasV6Ops() const { 257 return STI.getFeatureBits() & ARM::HasV6Ops; 258 } 259 bool hasV6MOps() const { 260 return STI.getFeatureBits() & ARM::HasV6MOps; 261 } 262 bool hasV7Ops() const { 263 return STI.getFeatureBits() & ARM::HasV7Ops; 264 } 265 bool hasV8Ops() const { 266 return STI.getFeatureBits() & ARM::HasV8Ops; 267 } 268 bool hasARM() const { 269 return !(STI.getFeatureBits() & ARM::FeatureNoARM); 270 } 271 272 void SwitchMode() { 273 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 274 setAvailableFeatures(FB); 275 } 276 bool isMClass() const { 277 return STI.getFeatureBits() & ARM::FeatureMClass; 278 } 279 280 /// @name Auto-generated Match Functions 281 /// { 282 283#define GET_ASSEMBLER_HEADER 284#include "ARMGenAsmMatcher.inc" 285 286 /// } 287 288 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 289 OperandMatchResultTy parseCoprocNumOperand( 290 SmallVectorImpl<MCParsedAsmOperand*>&); 291 OperandMatchResultTy parseCoprocRegOperand( 292 SmallVectorImpl<MCParsedAsmOperand*>&); 293 OperandMatchResultTy parseCoprocOptionOperand( 294 SmallVectorImpl<MCParsedAsmOperand*>&); 295 OperandMatchResultTy parseMemBarrierOptOperand( 296 SmallVectorImpl<MCParsedAsmOperand*>&); 297 OperandMatchResultTy parseInstSyncBarrierOptOperand( 298 SmallVectorImpl<MCParsedAsmOperand*>&); 299 OperandMatchResultTy parseProcIFlagsOperand( 300 SmallVectorImpl<MCParsedAsmOperand*>&); 301 OperandMatchResultTy parseMSRMaskOperand( 302 SmallVectorImpl<MCParsedAsmOperand*>&); 303 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 304 StringRef Op, int Low, int High); 305 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 306 return parsePKHImm(O, "lsl", 0, 31); 307 } 308 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 309 return parsePKHImm(O, "asr", 1, 32); 310 } 311 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 312 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 313 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 314 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 315 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 316 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 317 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 318 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 319 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, 320 SMLoc &EndLoc); 321 322 // Asm Match Converter Methods 323 void cvtThumbMultiply(MCInst &Inst, 324 const SmallVectorImpl<MCParsedAsmOperand*> &); 325 void cvtThumbBranches(MCInst &Inst, 326 const SmallVectorImpl<MCParsedAsmOperand*> &); 327 328 bool validateInstruction(MCInst &Inst, 329 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 330 bool processInstruction(MCInst &Inst, 331 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 332 bool shouldOmitCCOutOperand(StringRef Mnemonic, 333 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 334 bool shouldOmitPredicateOperand(StringRef Mnemonic, 335 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 336public: 337 enum ARMMatchResultTy { 338 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 339 Match_RequiresNotITBlock, 340 Match_RequiresV6, 341 Match_RequiresThumb2, 342#define GET_OPERAND_DIAGNOSTIC_TYPES 343#include "ARMGenAsmMatcher.inc" 344 345 }; 346 347 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser, 348 const MCInstrInfo &MII) 349 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) { 350 MCAsmParserExtension::Initialize(_Parser); 351 352 // Cache the MCRegisterInfo. 353 MRI = getContext().getRegisterInfo(); 354 355 // Initialize the set of available features. 356 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 357 358 // Not in an ITBlock to start with. 359 ITState.CurPosition = ~0U; 360 361 NextSymbolIsThumb = false; 362 } 363 364 // Implementation of the MCTargetAsmParser interface: 365 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 366 bool 367 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 368 SMLoc NameLoc, 369 SmallVectorImpl<MCParsedAsmOperand*> &Operands) override; 370 bool ParseDirective(AsmToken DirectiveID) override; 371 372 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, 373 unsigned Kind) override; 374 unsigned checkTargetMatchPredicate(MCInst &Inst) override; 375 376 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 377 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 378 MCStreamer &Out, unsigned &ErrorInfo, 379 bool MatchingInlineAsm) override; 380 void onLabelParsed(MCSymbol *Symbol) override; 381}; 382} // end anonymous namespace 383 384namespace { 385 386/// ARMOperand - Instances of this class represent a parsed ARM machine 387/// operand. 388class ARMOperand : public MCParsedAsmOperand { 389 enum KindTy { 390 k_CondCode, 391 k_CCOut, 392 k_ITCondMask, 393 k_CoprocNum, 394 k_CoprocReg, 395 k_CoprocOption, 396 k_Immediate, 397 k_MemBarrierOpt, 398 k_InstSyncBarrierOpt, 399 k_Memory, 400 k_PostIndexRegister, 401 k_MSRMask, 402 k_ProcIFlags, 403 k_VectorIndex, 404 k_Register, 405 k_RegisterList, 406 k_DPRRegisterList, 407 k_SPRRegisterList, 408 k_VectorList, 409 k_VectorListAllLanes, 410 k_VectorListIndexed, 411 k_ShiftedRegister, 412 k_ShiftedImmediate, 413 k_ShifterImmediate, 414 k_RotateImmediate, 415 k_BitfieldDescriptor, 416 k_Token 417 } Kind; 418 419 SMLoc StartLoc, EndLoc; 420 SmallVector<unsigned, 8> Registers; 421 422 struct CCOp { 423 ARMCC::CondCodes Val; 424 }; 425 426 struct CopOp { 427 unsigned Val; 428 }; 429 430 struct CoprocOptionOp { 431 unsigned Val; 432 }; 433 434 struct ITMaskOp { 435 unsigned Mask:4; 436 }; 437 438 struct MBOptOp { 439 ARM_MB::MemBOpt Val; 440 }; 441 442 struct ISBOptOp { 443 ARM_ISB::InstSyncBOpt Val; 444 }; 445 446 struct IFlagsOp { 447 ARM_PROC::IFlags Val; 448 }; 449 450 struct MMaskOp { 451 unsigned Val; 452 }; 453 454 struct TokOp { 455 const char *Data; 456 unsigned Length; 457 }; 458 459 struct RegOp { 460 unsigned RegNum; 461 }; 462 463 // A vector register list is a sequential list of 1 to 4 registers. 464 struct VectorListOp { 465 unsigned RegNum; 466 unsigned Count; 467 unsigned LaneIndex; 468 bool isDoubleSpaced; 469 }; 470 471 struct VectorIndexOp { 472 unsigned Val; 473 }; 474 475 struct ImmOp { 476 const MCExpr *Val; 477 }; 478 479 /// Combined record for all forms of ARM address expressions. 480 struct MemoryOp { 481 unsigned BaseRegNum; 482 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 483 // was specified. 484 const MCConstantExpr *OffsetImm; // Offset immediate value 485 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 486 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 487 unsigned ShiftImm; // shift for OffsetReg. 488 unsigned Alignment; // 0 = no alignment specified 489 // n = alignment in bytes (2, 4, 8, 16, or 32) 490 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 491 }; 492 493 struct PostIdxRegOp { 494 unsigned RegNum; 495 bool isAdd; 496 ARM_AM::ShiftOpc ShiftTy; 497 unsigned ShiftImm; 498 }; 499 500 struct ShifterImmOp { 501 bool isASR; 502 unsigned Imm; 503 }; 504 505 struct RegShiftedRegOp { 506 ARM_AM::ShiftOpc ShiftTy; 507 unsigned SrcReg; 508 unsigned ShiftReg; 509 unsigned ShiftImm; 510 }; 511 512 struct RegShiftedImmOp { 513 ARM_AM::ShiftOpc ShiftTy; 514 unsigned SrcReg; 515 unsigned ShiftImm; 516 }; 517 518 struct RotImmOp { 519 unsigned Imm; 520 }; 521 522 struct BitfieldOp { 523 unsigned LSB; 524 unsigned Width; 525 }; 526 527 union { 528 struct CCOp CC; 529 struct CopOp Cop; 530 struct CoprocOptionOp CoprocOption; 531 struct MBOptOp MBOpt; 532 struct ISBOptOp ISBOpt; 533 struct ITMaskOp ITMask; 534 struct IFlagsOp IFlags; 535 struct MMaskOp MMask; 536 struct TokOp Tok; 537 struct RegOp Reg; 538 struct VectorListOp VectorList; 539 struct VectorIndexOp VectorIndex; 540 struct ImmOp Imm; 541 struct MemoryOp Memory; 542 struct PostIdxRegOp PostIdxReg; 543 struct ShifterImmOp ShifterImm; 544 struct RegShiftedRegOp RegShiftedReg; 545 struct RegShiftedImmOp RegShiftedImm; 546 struct RotImmOp RotImm; 547 struct BitfieldOp Bitfield; 548 }; 549 550 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 551public: 552 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 553 Kind = o.Kind; 554 StartLoc = o.StartLoc; 555 EndLoc = o.EndLoc; 556 switch (Kind) { 557 case k_CondCode: 558 CC = o.CC; 559 break; 560 case k_ITCondMask: 561 ITMask = o.ITMask; 562 break; 563 case k_Token: 564 Tok = o.Tok; 565 break; 566 case k_CCOut: 567 case k_Register: 568 Reg = o.Reg; 569 break; 570 case k_RegisterList: 571 case k_DPRRegisterList: 572 case k_SPRRegisterList: 573 Registers = o.Registers; 574 break; 575 case k_VectorList: 576 case k_VectorListAllLanes: 577 case k_VectorListIndexed: 578 VectorList = o.VectorList; 579 break; 580 case k_CoprocNum: 581 case k_CoprocReg: 582 Cop = o.Cop; 583 break; 584 case k_CoprocOption: 585 CoprocOption = o.CoprocOption; 586 break; 587 case k_Immediate: 588 Imm = o.Imm; 589 break; 590 case k_MemBarrierOpt: 591 MBOpt = o.MBOpt; 592 break; 593 case k_InstSyncBarrierOpt: 594 ISBOpt = o.ISBOpt; 595 case k_Memory: 596 Memory = o.Memory; 597 break; 598 case k_PostIndexRegister: 599 PostIdxReg = o.PostIdxReg; 600 break; 601 case k_MSRMask: 602 MMask = o.MMask; 603 break; 604 case k_ProcIFlags: 605 IFlags = o.IFlags; 606 break; 607 case k_ShifterImmediate: 608 ShifterImm = o.ShifterImm; 609 break; 610 case k_ShiftedRegister: 611 RegShiftedReg = o.RegShiftedReg; 612 break; 613 case k_ShiftedImmediate: 614 RegShiftedImm = o.RegShiftedImm; 615 break; 616 case k_RotateImmediate: 617 RotImm = o.RotImm; 618 break; 619 case k_BitfieldDescriptor: 620 Bitfield = o.Bitfield; 621 break; 622 case k_VectorIndex: 623 VectorIndex = o.VectorIndex; 624 break; 625 } 626 } 627 628 /// getStartLoc - Get the location of the first token of this operand. 629 SMLoc getStartLoc() const override { return StartLoc; } 630 /// getEndLoc - Get the location of the last token of this operand. 631 SMLoc getEndLoc() const override { return EndLoc; } 632 /// getLocRange - Get the range between the first and last token of this 633 /// operand. 634 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 635 636 ARMCC::CondCodes getCondCode() const { 637 assert(Kind == k_CondCode && "Invalid access!"); 638 return CC.Val; 639 } 640 641 unsigned getCoproc() const { 642 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 643 return Cop.Val; 644 } 645 646 StringRef getToken() const { 647 assert(Kind == k_Token && "Invalid access!"); 648 return StringRef(Tok.Data, Tok.Length); 649 } 650 651 unsigned getReg() const override { 652 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 653 return Reg.RegNum; 654 } 655 656 const SmallVectorImpl<unsigned> &getRegList() const { 657 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 658 Kind == k_SPRRegisterList) && "Invalid access!"); 659 return Registers; 660 } 661 662 const MCExpr *getImm() const { 663 assert(isImm() && "Invalid access!"); 664 return Imm.Val; 665 } 666 667 unsigned getVectorIndex() const { 668 assert(Kind == k_VectorIndex && "Invalid access!"); 669 return VectorIndex.Val; 670 } 671 672 ARM_MB::MemBOpt getMemBarrierOpt() const { 673 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 674 return MBOpt.Val; 675 } 676 677 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { 678 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); 679 return ISBOpt.Val; 680 } 681 682 ARM_PROC::IFlags getProcIFlags() const { 683 assert(Kind == k_ProcIFlags && "Invalid access!"); 684 return IFlags.Val; 685 } 686 687 unsigned getMSRMask() const { 688 assert(Kind == k_MSRMask && "Invalid access!"); 689 return MMask.Val; 690 } 691 692 bool isCoprocNum() const { return Kind == k_CoprocNum; } 693 bool isCoprocReg() const { return Kind == k_CoprocReg; } 694 bool isCoprocOption() const { return Kind == k_CoprocOption; } 695 bool isCondCode() const { return Kind == k_CondCode; } 696 bool isCCOut() const { return Kind == k_CCOut; } 697 bool isITMask() const { return Kind == k_ITCondMask; } 698 bool isITCondCode() const { return Kind == k_CondCode; } 699 bool isImm() const override { return Kind == k_Immediate; } 700 // checks whether this operand is an unsigned offset which fits is a field 701 // of specified width and scaled by a specific number of bits 702 template<unsigned width, unsigned scale> 703 bool isUnsignedOffset() const { 704 if (!isImm()) return false; 705 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 706 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 707 int64_t Val = CE->getValue(); 708 int64_t Align = 1LL << scale; 709 int64_t Max = Align * ((1LL << width) - 1); 710 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); 711 } 712 return false; 713 } 714 // checks whether this operand is an signed offset which fits is a field 715 // of specified width and scaled by a specific number of bits 716 template<unsigned width, unsigned scale> 717 bool isSignedOffset() const { 718 if (!isImm()) return false; 719 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 720 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 721 int64_t Val = CE->getValue(); 722 int64_t Align = 1LL << scale; 723 int64_t Max = Align * ((1LL << (width-1)) - 1); 724 int64_t Min = -Align * (1LL << (width-1)); 725 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); 726 } 727 return false; 728 } 729 730 // checks whether this operand is a memory operand computed as an offset 731 // applied to PC. the offset may have 8 bits of magnitude and is represented 732 // with two bits of shift. textually it may be either [pc, #imm], #imm or 733 // relocable expression... 734 bool isThumbMemPC() const { 735 int64_t Val = 0; 736 if (isImm()) { 737 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 738 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val); 739 if (!CE) return false; 740 Val = CE->getValue(); 741 } 742 else if (isMem()) { 743 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; 744 if(Memory.BaseRegNum != ARM::PC) return false; 745 Val = Memory.OffsetImm->getValue(); 746 } 747 else return false; 748 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); 749 } 750 bool isFPImm() const { 751 if (!isImm()) return false; 752 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 753 if (!CE) return false; 754 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 755 return Val != -1; 756 } 757 bool isFBits16() const { 758 if (!isImm()) return false; 759 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 760 if (!CE) return false; 761 int64_t Value = CE->getValue(); 762 return Value >= 0 && Value <= 16; 763 } 764 bool isFBits32() const { 765 if (!isImm()) return false; 766 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 767 if (!CE) return false; 768 int64_t Value = CE->getValue(); 769 return Value >= 1 && Value <= 32; 770 } 771 bool isImm8s4() const { 772 if (!isImm()) return false; 773 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 774 if (!CE) return false; 775 int64_t Value = CE->getValue(); 776 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 777 } 778 bool isImm0_1020s4() const { 779 if (!isImm()) return false; 780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 781 if (!CE) return false; 782 int64_t Value = CE->getValue(); 783 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 784 } 785 bool isImm0_508s4() const { 786 if (!isImm()) return false; 787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 788 if (!CE) return false; 789 int64_t Value = CE->getValue(); 790 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 791 } 792 bool isImm0_508s4Neg() const { 793 if (!isImm()) return false; 794 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 795 if (!CE) return false; 796 int64_t Value = -CE->getValue(); 797 // explicitly exclude zero. we want that to use the normal 0_508 version. 798 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 799 } 800 bool isImm0_239() const { 801 if (!isImm()) return false; 802 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 803 if (!CE) return false; 804 int64_t Value = CE->getValue(); 805 return Value >= 0 && Value < 240; 806 } 807 bool isImm0_255() const { 808 if (!isImm()) return false; 809 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 810 if (!CE) return false; 811 int64_t Value = CE->getValue(); 812 return Value >= 0 && Value < 256; 813 } 814 bool isImm0_4095() const { 815 if (!isImm()) return false; 816 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 817 if (!CE) return false; 818 int64_t Value = CE->getValue(); 819 return Value >= 0 && Value < 4096; 820 } 821 bool isImm0_4095Neg() const { 822 if (!isImm()) return false; 823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 824 if (!CE) return false; 825 int64_t Value = -CE->getValue(); 826 return Value > 0 && Value < 4096; 827 } 828 bool isImm0_1() const { 829 if (!isImm()) return false; 830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 831 if (!CE) return false; 832 int64_t Value = CE->getValue(); 833 return Value >= 0 && Value < 2; 834 } 835 bool isImm0_3() const { 836 if (!isImm()) return false; 837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 838 if (!CE) return false; 839 int64_t Value = CE->getValue(); 840 return Value >= 0 && Value < 4; 841 } 842 bool isImm0_7() const { 843 if (!isImm()) return false; 844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 845 if (!CE) return false; 846 int64_t Value = CE->getValue(); 847 return Value >= 0 && Value < 8; 848 } 849 bool isImm0_15() const { 850 if (!isImm()) return false; 851 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 852 if (!CE) return false; 853 int64_t Value = CE->getValue(); 854 return Value >= 0 && Value < 16; 855 } 856 bool isImm0_31() const { 857 if (!isImm()) return false; 858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 859 if (!CE) return false; 860 int64_t Value = CE->getValue(); 861 return Value >= 0 && Value < 32; 862 } 863 bool isImm0_63() const { 864 if (!isImm()) return false; 865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 866 if (!CE) return false; 867 int64_t Value = CE->getValue(); 868 return Value >= 0 && Value < 64; 869 } 870 bool isImm8() const { 871 if (!isImm()) return false; 872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 873 if (!CE) return false; 874 int64_t Value = CE->getValue(); 875 return Value == 8; 876 } 877 bool isImm16() const { 878 if (!isImm()) return false; 879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 880 if (!CE) return false; 881 int64_t Value = CE->getValue(); 882 return Value == 16; 883 } 884 bool isImm32() const { 885 if (!isImm()) return false; 886 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 887 if (!CE) return false; 888 int64_t Value = CE->getValue(); 889 return Value == 32; 890 } 891 bool isShrImm8() const { 892 if (!isImm()) return false; 893 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 894 if (!CE) return false; 895 int64_t Value = CE->getValue(); 896 return Value > 0 && Value <= 8; 897 } 898 bool isShrImm16() const { 899 if (!isImm()) return false; 900 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 901 if (!CE) return false; 902 int64_t Value = CE->getValue(); 903 return Value > 0 && Value <= 16; 904 } 905 bool isShrImm32() const { 906 if (!isImm()) return false; 907 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 908 if (!CE) return false; 909 int64_t Value = CE->getValue(); 910 return Value > 0 && Value <= 32; 911 } 912 bool isShrImm64() const { 913 if (!isImm()) return false; 914 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 915 if (!CE) return false; 916 int64_t Value = CE->getValue(); 917 return Value > 0 && Value <= 64; 918 } 919 bool isImm1_7() const { 920 if (!isImm()) return false; 921 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 922 if (!CE) return false; 923 int64_t Value = CE->getValue(); 924 return Value > 0 && Value < 8; 925 } 926 bool isImm1_15() const { 927 if (!isImm()) return false; 928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 929 if (!CE) return false; 930 int64_t Value = CE->getValue(); 931 return Value > 0 && Value < 16; 932 } 933 bool isImm1_31() const { 934 if (!isImm()) return false; 935 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 936 if (!CE) return false; 937 int64_t Value = CE->getValue(); 938 return Value > 0 && Value < 32; 939 } 940 bool isImm1_16() const { 941 if (!isImm()) return false; 942 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 943 if (!CE) return false; 944 int64_t Value = CE->getValue(); 945 return Value > 0 && Value < 17; 946 } 947 bool isImm1_32() const { 948 if (!isImm()) return false; 949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 950 if (!CE) return false; 951 int64_t Value = CE->getValue(); 952 return Value > 0 && Value < 33; 953 } 954 bool isImm0_32() const { 955 if (!isImm()) return false; 956 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 957 if (!CE) return false; 958 int64_t Value = CE->getValue(); 959 return Value >= 0 && Value < 33; 960 } 961 bool isImm0_65535() const { 962 if (!isImm()) return false; 963 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 964 if (!CE) return false; 965 int64_t Value = CE->getValue(); 966 return Value >= 0 && Value < 65536; 967 } 968 bool isImm256_65535Expr() const { 969 if (!isImm()) return false; 970 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 971 // If it's not a constant expression, it'll generate a fixup and be 972 // handled later. 973 if (!CE) return true; 974 int64_t Value = CE->getValue(); 975 return Value >= 256 && Value < 65536; 976 } 977 bool isImm0_65535Expr() const { 978 if (!isImm()) return false; 979 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 980 // If it's not a constant expression, it'll generate a fixup and be 981 // handled later. 982 if (!CE) return true; 983 int64_t Value = CE->getValue(); 984 return Value >= 0 && Value < 65536; 985 } 986 bool isImm24bit() const { 987 if (!isImm()) return false; 988 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 989 if (!CE) return false; 990 int64_t Value = CE->getValue(); 991 return Value >= 0 && Value <= 0xffffff; 992 } 993 bool isImmThumbSR() const { 994 if (!isImm()) return false; 995 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 996 if (!CE) return false; 997 int64_t Value = CE->getValue(); 998 return Value > 0 && Value < 33; 999 } 1000 bool isPKHLSLImm() const { 1001 if (!isImm()) return false; 1002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1003 if (!CE) return false; 1004 int64_t Value = CE->getValue(); 1005 return Value >= 0 && Value < 32; 1006 } 1007 bool isPKHASRImm() const { 1008 if (!isImm()) return false; 1009 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1010 if (!CE) return false; 1011 int64_t Value = CE->getValue(); 1012 return Value > 0 && Value <= 32; 1013 } 1014 bool isAdrLabel() const { 1015 // If we have an immediate that's not a constant, treat it as a label 1016 // reference needing a fixup. If it is a constant, but it can't fit 1017 // into shift immediate encoding, we reject it. 1018 if (isImm() && !isa<MCConstantExpr>(getImm())) return true; 1019 else return (isARMSOImm() || isARMSOImmNeg()); 1020 } 1021 bool isARMSOImm() const { 1022 if (!isImm()) return false; 1023 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1024 if (!CE) return false; 1025 int64_t Value = CE->getValue(); 1026 return ARM_AM::getSOImmVal(Value) != -1; 1027 } 1028 bool isARMSOImmNot() const { 1029 if (!isImm()) return false; 1030 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1031 if (!CE) return false; 1032 int64_t Value = CE->getValue(); 1033 return ARM_AM::getSOImmVal(~Value) != -1; 1034 } 1035 bool isARMSOImmNeg() const { 1036 if (!isImm()) return false; 1037 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1038 if (!CE) return false; 1039 int64_t Value = CE->getValue(); 1040 // Only use this when not representable as a plain so_imm. 1041 return ARM_AM::getSOImmVal(Value) == -1 && 1042 ARM_AM::getSOImmVal(-Value) != -1; 1043 } 1044 bool isT2SOImm() const { 1045 if (!isImm()) return false; 1046 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1047 if (!CE) return false; 1048 int64_t Value = CE->getValue(); 1049 return ARM_AM::getT2SOImmVal(Value) != -1; 1050 } 1051 bool isT2SOImmNot() const { 1052 if (!isImm()) return false; 1053 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1054 if (!CE) return false; 1055 int64_t Value = CE->getValue(); 1056 return ARM_AM::getT2SOImmVal(Value) == -1 && 1057 ARM_AM::getT2SOImmVal(~Value) != -1; 1058 } 1059 bool isT2SOImmNeg() const { 1060 if (!isImm()) return false; 1061 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1062 if (!CE) return false; 1063 int64_t Value = CE->getValue(); 1064 // Only use this when not representable as a plain so_imm. 1065 return ARM_AM::getT2SOImmVal(Value) == -1 && 1066 ARM_AM::getT2SOImmVal(-Value) != -1; 1067 } 1068 bool isSetEndImm() const { 1069 if (!isImm()) return false; 1070 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1071 if (!CE) return false; 1072 int64_t Value = CE->getValue(); 1073 return Value == 1 || Value == 0; 1074 } 1075 bool isReg() const override { return Kind == k_Register; } 1076 bool isRegList() const { return Kind == k_RegisterList; } 1077 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 1078 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 1079 bool isToken() const override { return Kind == k_Token; } 1080 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 1081 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } 1082 bool isMem() const override { return Kind == k_Memory; } 1083 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 1084 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 1085 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 1086 bool isRotImm() const { return Kind == k_RotateImmediate; } 1087 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 1088 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 1089 bool isPostIdxReg() const { 1090 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 1091 } 1092 bool isMemNoOffset(bool alignOK = false) const { 1093 if (!isMem()) 1094 return false; 1095 // No offset of any kind. 1096 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 1097 (alignOK || Memory.Alignment == 0); 1098 } 1099 bool isMemPCRelImm12() const { 1100 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1101 return false; 1102 // Base register must be PC. 1103 if (Memory.BaseRegNum != ARM::PC) 1104 return false; 1105 // Immediate offset in range [-4095, 4095]. 1106 if (!Memory.OffsetImm) return true; 1107 int64_t Val = Memory.OffsetImm->getValue(); 1108 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1109 } 1110 bool isAlignedMemory() const { 1111 return isMemNoOffset(true); 1112 } 1113 bool isAddrMode2() const { 1114 if (!isMem() || Memory.Alignment != 0) return false; 1115 // Check for register offset. 1116 if (Memory.OffsetRegNum) return true; 1117 // Immediate offset in range [-4095, 4095]. 1118 if (!Memory.OffsetImm) return true; 1119 int64_t Val = Memory.OffsetImm->getValue(); 1120 return Val > -4096 && Val < 4096; 1121 } 1122 bool isAM2OffsetImm() const { 1123 if (!isImm()) return false; 1124 // Immediate offset in range [-4095, 4095]. 1125 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1126 if (!CE) return false; 1127 int64_t Val = CE->getValue(); 1128 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096); 1129 } 1130 bool isAddrMode3() const { 1131 // If we have an immediate that's not a constant, treat it as a label 1132 // reference needing a fixup. If it is a constant, it's something else 1133 // and we reject it. 1134 if (isImm() && !isa<MCConstantExpr>(getImm())) 1135 return true; 1136 if (!isMem() || Memory.Alignment != 0) return false; 1137 // No shifts are legal for AM3. 1138 if (Memory.ShiftType != ARM_AM::no_shift) return false; 1139 // Check for register offset. 1140 if (Memory.OffsetRegNum) return true; 1141 // Immediate offset in range [-255, 255]. 1142 if (!Memory.OffsetImm) return true; 1143 int64_t Val = Memory.OffsetImm->getValue(); 1144 // The #-0 offset is encoded as INT32_MIN, and we have to check 1145 // for this too. 1146 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1147 } 1148 bool isAM3Offset() const { 1149 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 1150 return false; 1151 if (Kind == k_PostIndexRegister) 1152 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 1153 // Immediate offset in range [-255, 255]. 1154 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1155 if (!CE) return false; 1156 int64_t Val = CE->getValue(); 1157 // Special case, #-0 is INT32_MIN. 1158 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1159 } 1160 bool isAddrMode5() const { 1161 // If we have an immediate that's not a constant, treat it as a label 1162 // reference needing a fixup. If it is a constant, it's something else 1163 // and we reject it. 1164 if (isImm() && !isa<MCConstantExpr>(getImm())) 1165 return true; 1166 if (!isMem() || Memory.Alignment != 0) return false; 1167 // Check for register offset. 1168 if (Memory.OffsetRegNum) return false; 1169 // Immediate offset in range [-1020, 1020] and a multiple of 4. 1170 if (!Memory.OffsetImm) return true; 1171 int64_t Val = Memory.OffsetImm->getValue(); 1172 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 1173 Val == INT32_MIN; 1174 } 1175 bool isMemTBB() const { 1176 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1177 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1178 return false; 1179 return true; 1180 } 1181 bool isMemTBH() const { 1182 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1183 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 1184 Memory.Alignment != 0 ) 1185 return false; 1186 return true; 1187 } 1188 bool isMemRegOffset() const { 1189 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) 1190 return false; 1191 return true; 1192 } 1193 bool isT2MemRegOffset() const { 1194 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1195 Memory.Alignment != 0) 1196 return false; 1197 // Only lsl #{0, 1, 2, 3} allowed. 1198 if (Memory.ShiftType == ARM_AM::no_shift) 1199 return true; 1200 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 1201 return false; 1202 return true; 1203 } 1204 bool isMemThumbRR() const { 1205 // Thumb reg+reg addressing is simple. Just two registers, a base and 1206 // an offset. No shifts, negations or any other complicating factors. 1207 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1208 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1209 return false; 1210 return isARMLowRegister(Memory.BaseRegNum) && 1211 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1212 } 1213 bool isMemThumbRIs4() const { 1214 if (!isMem() || Memory.OffsetRegNum != 0 || 1215 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1216 return false; 1217 // Immediate offset, multiple of 4 in range [0, 124]. 1218 if (!Memory.OffsetImm) return true; 1219 int64_t Val = Memory.OffsetImm->getValue(); 1220 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1221 } 1222 bool isMemThumbRIs2() const { 1223 if (!isMem() || Memory.OffsetRegNum != 0 || 1224 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1225 return false; 1226 // Immediate offset, multiple of 4 in range [0, 62]. 1227 if (!Memory.OffsetImm) return true; 1228 int64_t Val = Memory.OffsetImm->getValue(); 1229 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1230 } 1231 bool isMemThumbRIs1() const { 1232 if (!isMem() || Memory.OffsetRegNum != 0 || 1233 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1234 return false; 1235 // Immediate offset in range [0, 31]. 1236 if (!Memory.OffsetImm) return true; 1237 int64_t Val = Memory.OffsetImm->getValue(); 1238 return Val >= 0 && Val <= 31; 1239 } 1240 bool isMemThumbSPI() const { 1241 if (!isMem() || Memory.OffsetRegNum != 0 || 1242 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1243 return false; 1244 // Immediate offset, multiple of 4 in range [0, 1020]. 1245 if (!Memory.OffsetImm) return true; 1246 int64_t Val = Memory.OffsetImm->getValue(); 1247 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1248 } 1249 bool isMemImm8s4Offset() const { 1250 // If we have an immediate that's not a constant, treat it as a label 1251 // reference needing a fixup. If it is a constant, it's something else 1252 // and we reject it. 1253 if (isImm() && !isa<MCConstantExpr>(getImm())) 1254 return true; 1255 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1256 return false; 1257 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1258 if (!Memory.OffsetImm) return true; 1259 int64_t Val = Memory.OffsetImm->getValue(); 1260 // Special case, #-0 is INT32_MIN. 1261 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1262 } 1263 bool isMemImm0_1020s4Offset() const { 1264 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1265 return false; 1266 // Immediate offset a multiple of 4 in range [0, 1020]. 1267 if (!Memory.OffsetImm) return true; 1268 int64_t Val = Memory.OffsetImm->getValue(); 1269 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1270 } 1271 bool isMemImm8Offset() const { 1272 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1273 return false; 1274 // Base reg of PC isn't allowed for these encodings. 1275 if (Memory.BaseRegNum == ARM::PC) return false; 1276 // Immediate offset in range [-255, 255]. 1277 if (!Memory.OffsetImm) return true; 1278 int64_t Val = Memory.OffsetImm->getValue(); 1279 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1280 } 1281 bool isMemPosImm8Offset() const { 1282 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1283 return false; 1284 // Immediate offset in range [0, 255]. 1285 if (!Memory.OffsetImm) return true; 1286 int64_t Val = Memory.OffsetImm->getValue(); 1287 return Val >= 0 && Val < 256; 1288 } 1289 bool isMemNegImm8Offset() const { 1290 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1291 return false; 1292 // Base reg of PC isn't allowed for these encodings. 1293 if (Memory.BaseRegNum == ARM::PC) return false; 1294 // Immediate offset in range [-255, -1]. 1295 if (!Memory.OffsetImm) return false; 1296 int64_t Val = Memory.OffsetImm->getValue(); 1297 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1298 } 1299 bool isMemUImm12Offset() const { 1300 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1301 return false; 1302 // Immediate offset in range [0, 4095]. 1303 if (!Memory.OffsetImm) return true; 1304 int64_t Val = Memory.OffsetImm->getValue(); 1305 return (Val >= 0 && Val < 4096); 1306 } 1307 bool isMemImm12Offset() const { 1308 // If we have an immediate that's not a constant, treat it as a label 1309 // reference needing a fixup. If it is a constant, it's something else 1310 // and we reject it. 1311 if (isImm() && !isa<MCConstantExpr>(getImm())) 1312 return true; 1313 1314 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1315 return false; 1316 // Immediate offset in range [-4095, 4095]. 1317 if (!Memory.OffsetImm) return true; 1318 int64_t Val = Memory.OffsetImm->getValue(); 1319 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1320 } 1321 bool isPostIdxImm8() const { 1322 if (!isImm()) return false; 1323 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1324 if (!CE) return false; 1325 int64_t Val = CE->getValue(); 1326 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1327 } 1328 bool isPostIdxImm8s4() const { 1329 if (!isImm()) return false; 1330 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1331 if (!CE) return false; 1332 int64_t Val = CE->getValue(); 1333 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1334 (Val == INT32_MIN); 1335 } 1336 1337 bool isMSRMask() const { return Kind == k_MSRMask; } 1338 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1339 1340 // NEON operands. 1341 bool isSingleSpacedVectorList() const { 1342 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1343 } 1344 bool isDoubleSpacedVectorList() const { 1345 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1346 } 1347 bool isVecListOneD() const { 1348 if (!isSingleSpacedVectorList()) return false; 1349 return VectorList.Count == 1; 1350 } 1351 1352 bool isVecListDPair() const { 1353 if (!isSingleSpacedVectorList()) return false; 1354 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1355 .contains(VectorList.RegNum)); 1356 } 1357 1358 bool isVecListThreeD() const { 1359 if (!isSingleSpacedVectorList()) return false; 1360 return VectorList.Count == 3; 1361 } 1362 1363 bool isVecListFourD() const { 1364 if (!isSingleSpacedVectorList()) return false; 1365 return VectorList.Count == 4; 1366 } 1367 1368 bool isVecListDPairSpaced() const { 1369 if (Kind != k_VectorList) return false; 1370 if (isSingleSpacedVectorList()) return false; 1371 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1372 .contains(VectorList.RegNum)); 1373 } 1374 1375 bool isVecListThreeQ() const { 1376 if (!isDoubleSpacedVectorList()) return false; 1377 return VectorList.Count == 3; 1378 } 1379 1380 bool isVecListFourQ() const { 1381 if (!isDoubleSpacedVectorList()) return false; 1382 return VectorList.Count == 4; 1383 } 1384 1385 bool isSingleSpacedVectorAllLanes() const { 1386 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1387 } 1388 bool isDoubleSpacedVectorAllLanes() const { 1389 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1390 } 1391 bool isVecListOneDAllLanes() const { 1392 if (!isSingleSpacedVectorAllLanes()) return false; 1393 return VectorList.Count == 1; 1394 } 1395 1396 bool isVecListDPairAllLanes() const { 1397 if (!isSingleSpacedVectorAllLanes()) return false; 1398 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1399 .contains(VectorList.RegNum)); 1400 } 1401 1402 bool isVecListDPairSpacedAllLanes() const { 1403 if (!isDoubleSpacedVectorAllLanes()) return false; 1404 return VectorList.Count == 2; 1405 } 1406 1407 bool isVecListThreeDAllLanes() const { 1408 if (!isSingleSpacedVectorAllLanes()) return false; 1409 return VectorList.Count == 3; 1410 } 1411 1412 bool isVecListThreeQAllLanes() const { 1413 if (!isDoubleSpacedVectorAllLanes()) return false; 1414 return VectorList.Count == 3; 1415 } 1416 1417 bool isVecListFourDAllLanes() const { 1418 if (!isSingleSpacedVectorAllLanes()) return false; 1419 return VectorList.Count == 4; 1420 } 1421 1422 bool isVecListFourQAllLanes() const { 1423 if (!isDoubleSpacedVectorAllLanes()) return false; 1424 return VectorList.Count == 4; 1425 } 1426 1427 bool isSingleSpacedVectorIndexed() const { 1428 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1429 } 1430 bool isDoubleSpacedVectorIndexed() const { 1431 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1432 } 1433 bool isVecListOneDByteIndexed() const { 1434 if (!isSingleSpacedVectorIndexed()) return false; 1435 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1436 } 1437 1438 bool isVecListOneDHWordIndexed() const { 1439 if (!isSingleSpacedVectorIndexed()) return false; 1440 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1441 } 1442 1443 bool isVecListOneDWordIndexed() const { 1444 if (!isSingleSpacedVectorIndexed()) return false; 1445 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1446 } 1447 1448 bool isVecListTwoDByteIndexed() const { 1449 if (!isSingleSpacedVectorIndexed()) return false; 1450 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1451 } 1452 1453 bool isVecListTwoDHWordIndexed() const { 1454 if (!isSingleSpacedVectorIndexed()) return false; 1455 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1456 } 1457 1458 bool isVecListTwoQWordIndexed() const { 1459 if (!isDoubleSpacedVectorIndexed()) return false; 1460 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1461 } 1462 1463 bool isVecListTwoQHWordIndexed() const { 1464 if (!isDoubleSpacedVectorIndexed()) return false; 1465 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1466 } 1467 1468 bool isVecListTwoDWordIndexed() const { 1469 if (!isSingleSpacedVectorIndexed()) return false; 1470 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1471 } 1472 1473 bool isVecListThreeDByteIndexed() const { 1474 if (!isSingleSpacedVectorIndexed()) return false; 1475 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1476 } 1477 1478 bool isVecListThreeDHWordIndexed() const { 1479 if (!isSingleSpacedVectorIndexed()) return false; 1480 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1481 } 1482 1483 bool isVecListThreeQWordIndexed() const { 1484 if (!isDoubleSpacedVectorIndexed()) return false; 1485 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1486 } 1487 1488 bool isVecListThreeQHWordIndexed() const { 1489 if (!isDoubleSpacedVectorIndexed()) return false; 1490 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1491 } 1492 1493 bool isVecListThreeDWordIndexed() const { 1494 if (!isSingleSpacedVectorIndexed()) return false; 1495 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1496 } 1497 1498 bool isVecListFourDByteIndexed() const { 1499 if (!isSingleSpacedVectorIndexed()) return false; 1500 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1501 } 1502 1503 bool isVecListFourDHWordIndexed() const { 1504 if (!isSingleSpacedVectorIndexed()) return false; 1505 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1506 } 1507 1508 bool isVecListFourQWordIndexed() const { 1509 if (!isDoubleSpacedVectorIndexed()) return false; 1510 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1511 } 1512 1513 bool isVecListFourQHWordIndexed() const { 1514 if (!isDoubleSpacedVectorIndexed()) return false; 1515 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1516 } 1517 1518 bool isVecListFourDWordIndexed() const { 1519 if (!isSingleSpacedVectorIndexed()) return false; 1520 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1521 } 1522 1523 bool isVectorIndex8() const { 1524 if (Kind != k_VectorIndex) return false; 1525 return VectorIndex.Val < 8; 1526 } 1527 bool isVectorIndex16() const { 1528 if (Kind != k_VectorIndex) return false; 1529 return VectorIndex.Val < 4; 1530 } 1531 bool isVectorIndex32() const { 1532 if (Kind != k_VectorIndex) return false; 1533 return VectorIndex.Val < 2; 1534 } 1535 1536 bool isNEONi8splat() const { 1537 if (!isImm()) return false; 1538 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1539 // Must be a constant. 1540 if (!CE) return false; 1541 int64_t Value = CE->getValue(); 1542 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1543 // value. 1544 return Value >= 0 && Value < 256; 1545 } 1546 1547 bool isNEONi16splat() const { 1548 if (!isImm()) return false; 1549 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1550 // Must be a constant. 1551 if (!CE) return false; 1552 int64_t Value = CE->getValue(); 1553 // i16 value in the range [0,255] or [0x0100, 0xff00] 1554 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1555 } 1556 1557 bool isNEONi32splat() const { 1558 if (!isImm()) return false; 1559 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1560 // Must be a constant. 1561 if (!CE) return false; 1562 int64_t Value = CE->getValue(); 1563 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1564 return (Value >= 0 && Value < 256) || 1565 (Value >= 0x0100 && Value <= 0xff00) || 1566 (Value >= 0x010000 && Value <= 0xff0000) || 1567 (Value >= 0x01000000 && Value <= 0xff000000); 1568 } 1569 1570 bool isNEONi32vmov() const { 1571 if (!isImm()) return false; 1572 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1573 // Must be a constant. 1574 if (!CE) return false; 1575 int64_t Value = CE->getValue(); 1576 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1577 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1578 return (Value >= 0 && Value < 256) || 1579 (Value >= 0x0100 && Value <= 0xff00) || 1580 (Value >= 0x010000 && Value <= 0xff0000) || 1581 (Value >= 0x01000000 && Value <= 0xff000000) || 1582 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1583 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1584 } 1585 bool isNEONi32vmovNeg() const { 1586 if (!isImm()) return false; 1587 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1588 // Must be a constant. 1589 if (!CE) return false; 1590 int64_t Value = ~CE->getValue(); 1591 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1592 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1593 return (Value >= 0 && Value < 256) || 1594 (Value >= 0x0100 && Value <= 0xff00) || 1595 (Value >= 0x010000 && Value <= 0xff0000) || 1596 (Value >= 0x01000000 && Value <= 0xff000000) || 1597 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1598 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1599 } 1600 1601 bool isNEONi64splat() const { 1602 if (!isImm()) return false; 1603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1604 // Must be a constant. 1605 if (!CE) return false; 1606 uint64_t Value = CE->getValue(); 1607 // i64 value with each byte being either 0 or 0xff. 1608 for (unsigned i = 0; i < 8; ++i) 1609 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1610 return true; 1611 } 1612 1613 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1614 // Add as immediates when possible. Null MCExpr = 0. 1615 if (Expr == 0) 1616 Inst.addOperand(MCOperand::CreateImm(0)); 1617 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1618 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1619 else 1620 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1621 } 1622 1623 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1624 assert(N == 2 && "Invalid number of operands!"); 1625 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1626 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1627 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1628 } 1629 1630 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1631 assert(N == 1 && "Invalid number of operands!"); 1632 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1633 } 1634 1635 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1636 assert(N == 1 && "Invalid number of operands!"); 1637 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1638 } 1639 1640 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1641 assert(N == 1 && "Invalid number of operands!"); 1642 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1643 } 1644 1645 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1646 assert(N == 1 && "Invalid number of operands!"); 1647 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1648 } 1649 1650 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1651 assert(N == 1 && "Invalid number of operands!"); 1652 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1653 } 1654 1655 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1656 assert(N == 1 && "Invalid number of operands!"); 1657 Inst.addOperand(MCOperand::CreateReg(getReg())); 1658 } 1659 1660 void addRegOperands(MCInst &Inst, unsigned N) const { 1661 assert(N == 1 && "Invalid number of operands!"); 1662 Inst.addOperand(MCOperand::CreateReg(getReg())); 1663 } 1664 1665 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1666 assert(N == 3 && "Invalid number of operands!"); 1667 assert(isRegShiftedReg() && 1668 "addRegShiftedRegOperands() on non-RegShiftedReg!"); 1669 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1670 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1671 Inst.addOperand(MCOperand::CreateImm( 1672 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1673 } 1674 1675 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1676 assert(N == 2 && "Invalid number of operands!"); 1677 assert(isRegShiftedImm() && 1678 "addRegShiftedImmOperands() on non-RegShiftedImm!"); 1679 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1680 // Shift of #32 is encoded as 0 where permitted 1681 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1682 Inst.addOperand(MCOperand::CreateImm( 1683 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1684 } 1685 1686 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1687 assert(N == 1 && "Invalid number of operands!"); 1688 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1689 ShifterImm.Imm)); 1690 } 1691 1692 void addRegListOperands(MCInst &Inst, unsigned N) const { 1693 assert(N == 1 && "Invalid number of operands!"); 1694 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1695 for (SmallVectorImpl<unsigned>::const_iterator 1696 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1697 Inst.addOperand(MCOperand::CreateReg(*I)); 1698 } 1699 1700 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1701 addRegListOperands(Inst, N); 1702 } 1703 1704 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1705 addRegListOperands(Inst, N); 1706 } 1707 1708 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1709 assert(N == 1 && "Invalid number of operands!"); 1710 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1711 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1712 } 1713 1714 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1715 assert(N == 1 && "Invalid number of operands!"); 1716 // Munge the lsb/width into a bitfield mask. 1717 unsigned lsb = Bitfield.LSB; 1718 unsigned width = Bitfield.Width; 1719 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1720 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1721 (32 - (lsb + width))); 1722 Inst.addOperand(MCOperand::CreateImm(Mask)); 1723 } 1724 1725 void addImmOperands(MCInst &Inst, unsigned N) const { 1726 assert(N == 1 && "Invalid number of operands!"); 1727 addExpr(Inst, getImm()); 1728 } 1729 1730 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1731 assert(N == 1 && "Invalid number of operands!"); 1732 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1733 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1734 } 1735 1736 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1737 assert(N == 1 && "Invalid number of operands!"); 1738 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1739 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1740 } 1741 1742 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1743 assert(N == 1 && "Invalid number of operands!"); 1744 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1745 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1746 Inst.addOperand(MCOperand::CreateImm(Val)); 1747 } 1748 1749 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1750 assert(N == 1 && "Invalid number of operands!"); 1751 // FIXME: We really want to scale the value here, but the LDRD/STRD 1752 // instruction don't encode operands that way yet. 1753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1754 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1755 } 1756 1757 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1758 assert(N == 1 && "Invalid number of operands!"); 1759 // The immediate is scaled by four in the encoding and is stored 1760 // in the MCInst as such. Lop off the low two bits here. 1761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1762 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1763 } 1764 1765 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1766 assert(N == 1 && "Invalid number of operands!"); 1767 // The immediate is scaled by four in the encoding and is stored 1768 // in the MCInst as such. Lop off the low two bits here. 1769 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1770 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1771 } 1772 1773 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1774 assert(N == 1 && "Invalid number of operands!"); 1775 // The immediate is scaled by four in the encoding and is stored 1776 // in the MCInst as such. Lop off the low two bits here. 1777 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1778 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1779 } 1780 1781 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1782 assert(N == 1 && "Invalid number of operands!"); 1783 // The constant encodes as the immediate-1, and we store in the instruction 1784 // the bits as encoded, so subtract off one here. 1785 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1786 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1787 } 1788 1789 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1790 assert(N == 1 && "Invalid number of operands!"); 1791 // The constant encodes as the immediate-1, and we store in the instruction 1792 // the bits as encoded, so subtract off one here. 1793 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1794 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1795 } 1796 1797 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1798 assert(N == 1 && "Invalid number of operands!"); 1799 // The constant encodes as the immediate, except for 32, which encodes as 1800 // zero. 1801 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1802 unsigned Imm = CE->getValue(); 1803 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1804 } 1805 1806 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1807 assert(N == 1 && "Invalid number of operands!"); 1808 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1809 // the instruction as well. 1810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1811 int Val = CE->getValue(); 1812 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1813 } 1814 1815 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1816 assert(N == 1 && "Invalid number of operands!"); 1817 // The operand is actually a t2_so_imm, but we have its bitwise 1818 // negation in the assembly source, so twiddle it here. 1819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1820 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1821 } 1822 1823 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1824 assert(N == 1 && "Invalid number of operands!"); 1825 // The operand is actually a t2_so_imm, but we have its 1826 // negation in the assembly source, so twiddle it here. 1827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1828 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1829 } 1830 1831 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1832 assert(N == 1 && "Invalid number of operands!"); 1833 // The operand is actually an imm0_4095, but we have its 1834 // negation in the assembly source, so twiddle it here. 1835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1836 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1837 } 1838 1839 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { 1840 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) { 1841 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2)); 1842 return; 1843 } 1844 1845 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1846 assert(SR && "Unknown value type!"); 1847 Inst.addOperand(MCOperand::CreateExpr(SR)); 1848 } 1849 1850 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { 1851 assert(N == 1 && "Invalid number of operands!"); 1852 if (isImm()) { 1853 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1854 if (CE) { 1855 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1856 return; 1857 } 1858 1859 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1860 assert(SR && "Unknown value type!"); 1861 Inst.addOperand(MCOperand::CreateExpr(SR)); 1862 return; 1863 } 1864 1865 assert(isMem() && "Unknown value type!"); 1866 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!"); 1867 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue())); 1868 } 1869 1870 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1871 assert(N == 1 && "Invalid number of operands!"); 1872 // The operand is actually a so_imm, but we have its bitwise 1873 // negation in the assembly source, so twiddle it here. 1874 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1875 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1876 } 1877 1878 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 1879 assert(N == 1 && "Invalid number of operands!"); 1880 // The operand is actually a so_imm, but we have its 1881 // negation in the assembly source, so twiddle it here. 1882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1883 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1884 } 1885 1886 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1887 assert(N == 1 && "Invalid number of operands!"); 1888 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1889 } 1890 1891 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 1892 assert(N == 1 && "Invalid number of operands!"); 1893 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt()))); 1894 } 1895 1896 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1897 assert(N == 1 && "Invalid number of operands!"); 1898 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1899 } 1900 1901 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1902 assert(N == 1 && "Invalid number of operands!"); 1903 int32_t Imm = Memory.OffsetImm->getValue(); 1904 Inst.addOperand(MCOperand::CreateImm(Imm)); 1905 } 1906 1907 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 1908 assert(N == 1 && "Invalid number of operands!"); 1909 assert(isImm() && "Not an immediate!"); 1910 1911 // If we have an immediate that's not a constant, treat it as a label 1912 // reference needing a fixup. 1913 if (!isa<MCConstantExpr>(getImm())) { 1914 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1915 return; 1916 } 1917 1918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1919 int Val = CE->getValue(); 1920 Inst.addOperand(MCOperand::CreateImm(Val)); 1921 } 1922 1923 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1924 assert(N == 2 && "Invalid number of operands!"); 1925 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1926 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1927 } 1928 1929 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1930 assert(N == 3 && "Invalid number of operands!"); 1931 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1932 if (!Memory.OffsetRegNum) { 1933 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1934 // Special case for #-0 1935 if (Val == INT32_MIN) Val = 0; 1936 if (Val < 0) Val = -Val; 1937 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1938 } else { 1939 // For register offset, we encode the shift type and negation flag 1940 // here. 1941 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1942 Memory.ShiftImm, Memory.ShiftType); 1943 } 1944 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1945 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1946 Inst.addOperand(MCOperand::CreateImm(Val)); 1947 } 1948 1949 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1950 assert(N == 2 && "Invalid number of operands!"); 1951 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1952 assert(CE && "non-constant AM2OffsetImm operand!"); 1953 int32_t Val = CE->getValue(); 1954 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1955 // Special case for #-0 1956 if (Val == INT32_MIN) Val = 0; 1957 if (Val < 0) Val = -Val; 1958 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1959 Inst.addOperand(MCOperand::CreateReg(0)); 1960 Inst.addOperand(MCOperand::CreateImm(Val)); 1961 } 1962 1963 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1964 assert(N == 3 && "Invalid number of operands!"); 1965 // If we have an immediate that's not a constant, treat it as a label 1966 // reference needing a fixup. If it is a constant, it's something else 1967 // and we reject it. 1968 if (isImm()) { 1969 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1970 Inst.addOperand(MCOperand::CreateReg(0)); 1971 Inst.addOperand(MCOperand::CreateImm(0)); 1972 return; 1973 } 1974 1975 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1976 if (!Memory.OffsetRegNum) { 1977 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1978 // Special case for #-0 1979 if (Val == INT32_MIN) Val = 0; 1980 if (Val < 0) Val = -Val; 1981 Val = ARM_AM::getAM3Opc(AddSub, Val); 1982 } else { 1983 // For register offset, we encode the shift type and negation flag 1984 // here. 1985 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1986 } 1987 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1988 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1989 Inst.addOperand(MCOperand::CreateImm(Val)); 1990 } 1991 1992 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1993 assert(N == 2 && "Invalid number of operands!"); 1994 if (Kind == k_PostIndexRegister) { 1995 int32_t Val = 1996 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1997 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1998 Inst.addOperand(MCOperand::CreateImm(Val)); 1999 return; 2000 } 2001 2002 // Constant offset. 2003 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 2004 int32_t Val = CE->getValue(); 2005 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2006 // Special case for #-0 2007 if (Val == INT32_MIN) Val = 0; 2008 if (Val < 0) Val = -Val; 2009 Val = ARM_AM::getAM3Opc(AddSub, Val); 2010 Inst.addOperand(MCOperand::CreateReg(0)); 2011 Inst.addOperand(MCOperand::CreateImm(Val)); 2012 } 2013 2014 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 2015 assert(N == 2 && "Invalid number of operands!"); 2016 // If we have an immediate that's not a constant, treat it as a label 2017 // reference needing a fixup. If it is a constant, it's something else 2018 // and we reject it. 2019 if (isImm()) { 2020 Inst.addOperand(MCOperand::CreateExpr(getImm())); 2021 Inst.addOperand(MCOperand::CreateImm(0)); 2022 return; 2023 } 2024 2025 // The lower two bits are always zero and as such are not encoded. 2026 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2027 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2028 // Special case for #-0 2029 if (Val == INT32_MIN) Val = 0; 2030 if (Val < 0) Val = -Val; 2031 Val = ARM_AM::getAM5Opc(AddSub, Val); 2032 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2033 Inst.addOperand(MCOperand::CreateImm(Val)); 2034 } 2035 2036 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 2037 assert(N == 2 && "Invalid number of operands!"); 2038 // If we have an immediate that's not a constant, treat it as a label 2039 // reference needing a fixup. If it is a constant, it's something else 2040 // and we reject it. 2041 if (isImm()) { 2042 Inst.addOperand(MCOperand::CreateExpr(getImm())); 2043 Inst.addOperand(MCOperand::CreateImm(0)); 2044 return; 2045 } 2046 2047 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2048 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2049 Inst.addOperand(MCOperand::CreateImm(Val)); 2050 } 2051 2052 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 2053 assert(N == 2 && "Invalid number of operands!"); 2054 // The lower two bits are always zero and as such are not encoded. 2055 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2056 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2057 Inst.addOperand(MCOperand::CreateImm(Val)); 2058 } 2059 2060 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2061 assert(N == 2 && "Invalid number of operands!"); 2062 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2063 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2064 Inst.addOperand(MCOperand::CreateImm(Val)); 2065 } 2066 2067 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2068 addMemImm8OffsetOperands(Inst, N); 2069 } 2070 2071 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2072 addMemImm8OffsetOperands(Inst, N); 2073 } 2074 2075 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2076 assert(N == 2 && "Invalid number of operands!"); 2077 // If this is an immediate, it's a label reference. 2078 if (isImm()) { 2079 addExpr(Inst, getImm()); 2080 Inst.addOperand(MCOperand::CreateImm(0)); 2081 return; 2082 } 2083 2084 // Otherwise, it's a normal memory reg+offset. 2085 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2086 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2087 Inst.addOperand(MCOperand::CreateImm(Val)); 2088 } 2089 2090 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2091 assert(N == 2 && "Invalid number of operands!"); 2092 // If this is an immediate, it's a label reference. 2093 if (isImm()) { 2094 addExpr(Inst, getImm()); 2095 Inst.addOperand(MCOperand::CreateImm(0)); 2096 return; 2097 } 2098 2099 // Otherwise, it's a normal memory reg+offset. 2100 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2101 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2102 Inst.addOperand(MCOperand::CreateImm(Val)); 2103 } 2104 2105 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 2106 assert(N == 2 && "Invalid number of operands!"); 2107 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2108 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2109 } 2110 2111 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 2112 assert(N == 2 && "Invalid number of operands!"); 2113 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2114 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2115 } 2116 2117 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2118 assert(N == 3 && "Invalid number of operands!"); 2119 unsigned Val = 2120 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2121 Memory.ShiftImm, Memory.ShiftType); 2122 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2123 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2124 Inst.addOperand(MCOperand::CreateImm(Val)); 2125 } 2126 2127 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2128 assert(N == 3 && "Invalid number of operands!"); 2129 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2130 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2131 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 2132 } 2133 2134 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 2135 assert(N == 2 && "Invalid number of operands!"); 2136 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2137 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2138 } 2139 2140 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 2141 assert(N == 2 && "Invalid number of operands!"); 2142 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2143 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2144 Inst.addOperand(MCOperand::CreateImm(Val)); 2145 } 2146 2147 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 2148 assert(N == 2 && "Invalid number of operands!"); 2149 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 2150 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2151 Inst.addOperand(MCOperand::CreateImm(Val)); 2152 } 2153 2154 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 2155 assert(N == 2 && "Invalid number of operands!"); 2156 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 2157 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2158 Inst.addOperand(MCOperand::CreateImm(Val)); 2159 } 2160 2161 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 2162 assert(N == 2 && "Invalid number of operands!"); 2163 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2164 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2165 Inst.addOperand(MCOperand::CreateImm(Val)); 2166 } 2167 2168 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 2169 assert(N == 1 && "Invalid number of operands!"); 2170 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2171 assert(CE && "non-constant post-idx-imm8 operand!"); 2172 int Imm = CE->getValue(); 2173 bool isAdd = Imm >= 0; 2174 if (Imm == INT32_MIN) Imm = 0; 2175 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 2176 Inst.addOperand(MCOperand::CreateImm(Imm)); 2177 } 2178 2179 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 2180 assert(N == 1 && "Invalid number of operands!"); 2181 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2182 assert(CE && "non-constant post-idx-imm8s4 operand!"); 2183 int Imm = CE->getValue(); 2184 bool isAdd = Imm >= 0; 2185 if (Imm == INT32_MIN) Imm = 0; 2186 // Immediate is scaled by 4. 2187 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 2188 Inst.addOperand(MCOperand::CreateImm(Imm)); 2189 } 2190 2191 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 2192 assert(N == 2 && "Invalid number of operands!"); 2193 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2194 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 2195 } 2196 2197 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 2198 assert(N == 2 && "Invalid number of operands!"); 2199 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2200 // The sign, shift type, and shift amount are encoded in a single operand 2201 // using the AM2 encoding helpers. 2202 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 2203 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 2204 PostIdxReg.ShiftTy); 2205 Inst.addOperand(MCOperand::CreateImm(Imm)); 2206 } 2207 2208 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 2209 assert(N == 1 && "Invalid number of operands!"); 2210 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 2211 } 2212 2213 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 2214 assert(N == 1 && "Invalid number of operands!"); 2215 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 2216 } 2217 2218 void addVecListOperands(MCInst &Inst, unsigned N) const { 2219 assert(N == 1 && "Invalid number of operands!"); 2220 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2221 } 2222 2223 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 2224 assert(N == 2 && "Invalid number of operands!"); 2225 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2226 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 2227 } 2228 2229 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 2230 assert(N == 1 && "Invalid number of operands!"); 2231 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2232 } 2233 2234 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 2235 assert(N == 1 && "Invalid number of operands!"); 2236 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2237 } 2238 2239 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 2240 assert(N == 1 && "Invalid number of operands!"); 2241 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2242 } 2243 2244 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 2245 assert(N == 1 && "Invalid number of operands!"); 2246 // The immediate encodes the type of constant as well as the value. 2247 // Mask in that this is an i8 splat. 2248 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2249 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 2250 } 2251 2252 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2253 assert(N == 1 && "Invalid number of operands!"); 2254 // The immediate encodes the type of constant as well as the value. 2255 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2256 unsigned Value = CE->getValue(); 2257 if (Value >= 256) 2258 Value = (Value >> 8) | 0xa00; 2259 else 2260 Value |= 0x800; 2261 Inst.addOperand(MCOperand::CreateImm(Value)); 2262 } 2263 2264 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2265 assert(N == 1 && "Invalid number of operands!"); 2266 // The immediate encodes the type of constant as well as the value. 2267 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2268 unsigned Value = CE->getValue(); 2269 if (Value >= 256 && Value <= 0xff00) 2270 Value = (Value >> 8) | 0x200; 2271 else if (Value > 0xffff && Value <= 0xff0000) 2272 Value = (Value >> 16) | 0x400; 2273 else if (Value > 0xffffff) 2274 Value = (Value >> 24) | 0x600; 2275 Inst.addOperand(MCOperand::CreateImm(Value)); 2276 } 2277 2278 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2279 assert(N == 1 && "Invalid number of operands!"); 2280 // The immediate encodes the type of constant as well as the value. 2281 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2282 unsigned Value = CE->getValue(); 2283 if (Value >= 256 && Value <= 0xffff) 2284 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2285 else if (Value > 0xffff && Value <= 0xffffff) 2286 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2287 else if (Value > 0xffffff) 2288 Value = (Value >> 24) | 0x600; 2289 Inst.addOperand(MCOperand::CreateImm(Value)); 2290 } 2291 2292 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2293 assert(N == 1 && "Invalid number of operands!"); 2294 // The immediate encodes the type of constant as well as the value. 2295 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2296 unsigned Value = ~CE->getValue(); 2297 if (Value >= 256 && Value <= 0xffff) 2298 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2299 else if (Value > 0xffff && Value <= 0xffffff) 2300 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2301 else if (Value > 0xffffff) 2302 Value = (Value >> 24) | 0x600; 2303 Inst.addOperand(MCOperand::CreateImm(Value)); 2304 } 2305 2306 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2307 assert(N == 1 && "Invalid number of operands!"); 2308 // The immediate encodes the type of constant as well as the value. 2309 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2310 uint64_t Value = CE->getValue(); 2311 unsigned Imm = 0; 2312 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2313 Imm |= (Value & 1) << i; 2314 } 2315 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2316 } 2317 2318 void print(raw_ostream &OS) const override; 2319 2320 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 2321 ARMOperand *Op = new ARMOperand(k_ITCondMask); 2322 Op->ITMask.Mask = Mask; 2323 Op->StartLoc = S; 2324 Op->EndLoc = S; 2325 return Op; 2326 } 2327 2328 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 2329 ARMOperand *Op = new ARMOperand(k_CondCode); 2330 Op->CC.Val = CC; 2331 Op->StartLoc = S; 2332 Op->EndLoc = S; 2333 return Op; 2334 } 2335 2336 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 2337 ARMOperand *Op = new ARMOperand(k_CoprocNum); 2338 Op->Cop.Val = CopVal; 2339 Op->StartLoc = S; 2340 Op->EndLoc = S; 2341 return Op; 2342 } 2343 2344 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 2345 ARMOperand *Op = new ARMOperand(k_CoprocReg); 2346 Op->Cop.Val = CopVal; 2347 Op->StartLoc = S; 2348 Op->EndLoc = S; 2349 return Op; 2350 } 2351 2352 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 2353 ARMOperand *Op = new ARMOperand(k_CoprocOption); 2354 Op->Cop.Val = Val; 2355 Op->StartLoc = S; 2356 Op->EndLoc = E; 2357 return Op; 2358 } 2359 2360 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 2361 ARMOperand *Op = new ARMOperand(k_CCOut); 2362 Op->Reg.RegNum = RegNum; 2363 Op->StartLoc = S; 2364 Op->EndLoc = S; 2365 return Op; 2366 } 2367 2368 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 2369 ARMOperand *Op = new ARMOperand(k_Token); 2370 Op->Tok.Data = Str.data(); 2371 Op->Tok.Length = Str.size(); 2372 Op->StartLoc = S; 2373 Op->EndLoc = S; 2374 return Op; 2375 } 2376 2377 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 2378 ARMOperand *Op = new ARMOperand(k_Register); 2379 Op->Reg.RegNum = RegNum; 2380 Op->StartLoc = S; 2381 Op->EndLoc = E; 2382 return Op; 2383 } 2384 2385 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 2386 unsigned SrcReg, 2387 unsigned ShiftReg, 2388 unsigned ShiftImm, 2389 SMLoc S, SMLoc E) { 2390 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2391 Op->RegShiftedReg.ShiftTy = ShTy; 2392 Op->RegShiftedReg.SrcReg = SrcReg; 2393 Op->RegShiftedReg.ShiftReg = ShiftReg; 2394 Op->RegShiftedReg.ShiftImm = ShiftImm; 2395 Op->StartLoc = S; 2396 Op->EndLoc = E; 2397 return Op; 2398 } 2399 2400 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 2401 unsigned SrcReg, 2402 unsigned ShiftImm, 2403 SMLoc S, SMLoc E) { 2404 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2405 Op->RegShiftedImm.ShiftTy = ShTy; 2406 Op->RegShiftedImm.SrcReg = SrcReg; 2407 Op->RegShiftedImm.ShiftImm = ShiftImm; 2408 Op->StartLoc = S; 2409 Op->EndLoc = E; 2410 return Op; 2411 } 2412 2413 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 2414 SMLoc S, SMLoc E) { 2415 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2416 Op->ShifterImm.isASR = isASR; 2417 Op->ShifterImm.Imm = Imm; 2418 Op->StartLoc = S; 2419 Op->EndLoc = E; 2420 return Op; 2421 } 2422 2423 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 2424 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 2425 Op->RotImm.Imm = Imm; 2426 Op->StartLoc = S; 2427 Op->EndLoc = E; 2428 return Op; 2429 } 2430 2431 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2432 SMLoc S, SMLoc E) { 2433 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2434 Op->Bitfield.LSB = LSB; 2435 Op->Bitfield.Width = Width; 2436 Op->StartLoc = S; 2437 Op->EndLoc = E; 2438 return Op; 2439 } 2440 2441 static ARMOperand * 2442 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs, 2443 SMLoc StartLoc, SMLoc EndLoc) { 2444 assert (Regs.size() > 0 && "RegList contains no registers?"); 2445 KindTy Kind = k_RegisterList; 2446 2447 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) 2448 Kind = k_DPRRegisterList; 2449 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2450 contains(Regs.front().second)) 2451 Kind = k_SPRRegisterList; 2452 2453 // Sort based on the register encoding values. 2454 array_pod_sort(Regs.begin(), Regs.end()); 2455 2456 ARMOperand *Op = new ARMOperand(Kind); 2457 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator 2458 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2459 Op->Registers.push_back(I->second); 2460 Op->StartLoc = StartLoc; 2461 Op->EndLoc = EndLoc; 2462 return Op; 2463 } 2464 2465 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 2466 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2467 ARMOperand *Op = new ARMOperand(k_VectorList); 2468 Op->VectorList.RegNum = RegNum; 2469 Op->VectorList.Count = Count; 2470 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2471 Op->StartLoc = S; 2472 Op->EndLoc = E; 2473 return Op; 2474 } 2475 2476 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 2477 bool isDoubleSpaced, 2478 SMLoc S, SMLoc E) { 2479 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 2480 Op->VectorList.RegNum = RegNum; 2481 Op->VectorList.Count = Count; 2482 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2483 Op->StartLoc = S; 2484 Op->EndLoc = E; 2485 return Op; 2486 } 2487 2488 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 2489 unsigned Index, 2490 bool isDoubleSpaced, 2491 SMLoc S, SMLoc E) { 2492 ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 2493 Op->VectorList.RegNum = RegNum; 2494 Op->VectorList.Count = Count; 2495 Op->VectorList.LaneIndex = Index; 2496 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2497 Op->StartLoc = S; 2498 Op->EndLoc = E; 2499 return Op; 2500 } 2501 2502 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2503 MCContext &Ctx) { 2504 ARMOperand *Op = new ARMOperand(k_VectorIndex); 2505 Op->VectorIndex.Val = Idx; 2506 Op->StartLoc = S; 2507 Op->EndLoc = E; 2508 return Op; 2509 } 2510 2511 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 2512 ARMOperand *Op = new ARMOperand(k_Immediate); 2513 Op->Imm.Val = Val; 2514 Op->StartLoc = S; 2515 Op->EndLoc = E; 2516 return Op; 2517 } 2518 2519 static ARMOperand *CreateMem(unsigned BaseRegNum, 2520 const MCConstantExpr *OffsetImm, 2521 unsigned OffsetRegNum, 2522 ARM_AM::ShiftOpc ShiftType, 2523 unsigned ShiftImm, 2524 unsigned Alignment, 2525 bool isNegative, 2526 SMLoc S, SMLoc E) { 2527 ARMOperand *Op = new ARMOperand(k_Memory); 2528 Op->Memory.BaseRegNum = BaseRegNum; 2529 Op->Memory.OffsetImm = OffsetImm; 2530 Op->Memory.OffsetRegNum = OffsetRegNum; 2531 Op->Memory.ShiftType = ShiftType; 2532 Op->Memory.ShiftImm = ShiftImm; 2533 Op->Memory.Alignment = Alignment; 2534 Op->Memory.isNegative = isNegative; 2535 Op->StartLoc = S; 2536 Op->EndLoc = E; 2537 return Op; 2538 } 2539 2540 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2541 ARM_AM::ShiftOpc ShiftTy, 2542 unsigned ShiftImm, 2543 SMLoc S, SMLoc E) { 2544 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 2545 Op->PostIdxReg.RegNum = RegNum; 2546 Op->PostIdxReg.isAdd = isAdd; 2547 Op->PostIdxReg.ShiftTy = ShiftTy; 2548 Op->PostIdxReg.ShiftImm = ShiftImm; 2549 Op->StartLoc = S; 2550 Op->EndLoc = E; 2551 return Op; 2552 } 2553 2554 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 2555 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2556 Op->MBOpt.Val = Opt; 2557 Op->StartLoc = S; 2558 Op->EndLoc = S; 2559 return Op; 2560 } 2561 2562 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, 2563 SMLoc S) { 2564 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt); 2565 Op->ISBOpt.Val = Opt; 2566 Op->StartLoc = S; 2567 Op->EndLoc = S; 2568 return Op; 2569 } 2570 2571 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 2572 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2573 Op->IFlags.Val = IFlags; 2574 Op->StartLoc = S; 2575 Op->EndLoc = S; 2576 return Op; 2577 } 2578 2579 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 2580 ARMOperand *Op = new ARMOperand(k_MSRMask); 2581 Op->MMask.Val = MMask; 2582 Op->StartLoc = S; 2583 Op->EndLoc = S; 2584 return Op; 2585 } 2586}; 2587 2588} // end anonymous namespace. 2589 2590void ARMOperand::print(raw_ostream &OS) const { 2591 switch (Kind) { 2592 case k_CondCode: 2593 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2594 break; 2595 case k_CCOut: 2596 OS << "<ccout " << getReg() << ">"; 2597 break; 2598 case k_ITCondMask: { 2599 static const char *const MaskStr[] = { 2600 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2601 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2602 }; 2603 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2604 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2605 break; 2606 } 2607 case k_CoprocNum: 2608 OS << "<coprocessor number: " << getCoproc() << ">"; 2609 break; 2610 case k_CoprocReg: 2611 OS << "<coprocessor register: " << getCoproc() << ">"; 2612 break; 2613 case k_CoprocOption: 2614 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2615 break; 2616 case k_MSRMask: 2617 OS << "<mask: " << getMSRMask() << ">"; 2618 break; 2619 case k_Immediate: 2620 getImm()->print(OS); 2621 break; 2622 case k_MemBarrierOpt: 2623 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">"; 2624 break; 2625 case k_InstSyncBarrierOpt: 2626 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; 2627 break; 2628 case k_Memory: 2629 OS << "<memory " 2630 << " base:" << Memory.BaseRegNum; 2631 OS << ">"; 2632 break; 2633 case k_PostIndexRegister: 2634 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2635 << PostIdxReg.RegNum; 2636 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2637 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2638 << PostIdxReg.ShiftImm; 2639 OS << ">"; 2640 break; 2641 case k_ProcIFlags: { 2642 OS << "<ARM_PROC::"; 2643 unsigned IFlags = getProcIFlags(); 2644 for (int i=2; i >= 0; --i) 2645 if (IFlags & (1 << i)) 2646 OS << ARM_PROC::IFlagsToString(1 << i); 2647 OS << ">"; 2648 break; 2649 } 2650 case k_Register: 2651 OS << "<register " << getReg() << ">"; 2652 break; 2653 case k_ShifterImmediate: 2654 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2655 << " #" << ShifterImm.Imm << ">"; 2656 break; 2657 case k_ShiftedRegister: 2658 OS << "<so_reg_reg " 2659 << RegShiftedReg.SrcReg << " " 2660 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2661 << " " << RegShiftedReg.ShiftReg << ">"; 2662 break; 2663 case k_ShiftedImmediate: 2664 OS << "<so_reg_imm " 2665 << RegShiftedImm.SrcReg << " " 2666 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2667 << " #" << RegShiftedImm.ShiftImm << ">"; 2668 break; 2669 case k_RotateImmediate: 2670 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2671 break; 2672 case k_BitfieldDescriptor: 2673 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2674 << ", width: " << Bitfield.Width << ">"; 2675 break; 2676 case k_RegisterList: 2677 case k_DPRRegisterList: 2678 case k_SPRRegisterList: { 2679 OS << "<register_list "; 2680 2681 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2682 for (SmallVectorImpl<unsigned>::const_iterator 2683 I = RegList.begin(), E = RegList.end(); I != E; ) { 2684 OS << *I; 2685 if (++I < E) OS << ", "; 2686 } 2687 2688 OS << ">"; 2689 break; 2690 } 2691 case k_VectorList: 2692 OS << "<vector_list " << VectorList.Count << " * " 2693 << VectorList.RegNum << ">"; 2694 break; 2695 case k_VectorListAllLanes: 2696 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2697 << VectorList.RegNum << ">"; 2698 break; 2699 case k_VectorListIndexed: 2700 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2701 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2702 break; 2703 case k_Token: 2704 OS << "'" << getToken() << "'"; 2705 break; 2706 case k_VectorIndex: 2707 OS << "<vectorindex " << getVectorIndex() << ">"; 2708 break; 2709 } 2710} 2711 2712/// @name Auto-generated Match Functions 2713/// { 2714 2715static unsigned MatchRegisterName(StringRef Name); 2716 2717/// } 2718 2719bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2720 SMLoc &StartLoc, SMLoc &EndLoc) { 2721 StartLoc = Parser.getTok().getLoc(); 2722 EndLoc = Parser.getTok().getEndLoc(); 2723 RegNo = tryParseRegister(); 2724 2725 return (RegNo == (unsigned)-1); 2726} 2727 2728/// Try to parse a register name. The token must be an Identifier when called, 2729/// and if it is a register name the token is eaten and the register number is 2730/// returned. Otherwise return -1. 2731/// 2732int ARMAsmParser::tryParseRegister() { 2733 const AsmToken &Tok = Parser.getTok(); 2734 if (Tok.isNot(AsmToken::Identifier)) return -1; 2735 2736 std::string lowerCase = Tok.getString().lower(); 2737 unsigned RegNum = MatchRegisterName(lowerCase); 2738 if (!RegNum) { 2739 RegNum = StringSwitch<unsigned>(lowerCase) 2740 .Case("r13", ARM::SP) 2741 .Case("r14", ARM::LR) 2742 .Case("r15", ARM::PC) 2743 .Case("ip", ARM::R12) 2744 // Additional register name aliases for 'gas' compatibility. 2745 .Case("a1", ARM::R0) 2746 .Case("a2", ARM::R1) 2747 .Case("a3", ARM::R2) 2748 .Case("a4", ARM::R3) 2749 .Case("v1", ARM::R4) 2750 .Case("v2", ARM::R5) 2751 .Case("v3", ARM::R6) 2752 .Case("v4", ARM::R7) 2753 .Case("v5", ARM::R8) 2754 .Case("v6", ARM::R9) 2755 .Case("v7", ARM::R10) 2756 .Case("v8", ARM::R11) 2757 .Case("sb", ARM::R9) 2758 .Case("sl", ARM::R10) 2759 .Case("fp", ARM::R11) 2760 .Default(0); 2761 } 2762 if (!RegNum) { 2763 // Check for aliases registered via .req. Canonicalize to lower case. 2764 // That's more consistent since register names are case insensitive, and 2765 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2766 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2767 // If no match, return failure. 2768 if (Entry == RegisterReqs.end()) 2769 return -1; 2770 Parser.Lex(); // Eat identifier token. 2771 return Entry->getValue(); 2772 } 2773 2774 Parser.Lex(); // Eat identifier token. 2775 2776 return RegNum; 2777} 2778 2779// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2780// If a recoverable error occurs, return 1. If an irrecoverable error 2781// occurs, return -1. An irrecoverable error is one where tokens have been 2782// consumed in the process of trying to parse the shifter (i.e., when it is 2783// indeed a shifter operand, but malformed). 2784int ARMAsmParser::tryParseShiftRegister( 2785 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2786 SMLoc S = Parser.getTok().getLoc(); 2787 const AsmToken &Tok = Parser.getTok(); 2788 if (Tok.isNot(AsmToken::Identifier)) 2789 return -1; 2790 2791 std::string lowerCase = Tok.getString().lower(); 2792 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2793 .Case("asl", ARM_AM::lsl) 2794 .Case("lsl", ARM_AM::lsl) 2795 .Case("lsr", ARM_AM::lsr) 2796 .Case("asr", ARM_AM::asr) 2797 .Case("ror", ARM_AM::ror) 2798 .Case("rrx", ARM_AM::rrx) 2799 .Default(ARM_AM::no_shift); 2800 2801 if (ShiftTy == ARM_AM::no_shift) 2802 return 1; 2803 2804 Parser.Lex(); // Eat the operator. 2805 2806 // The source register for the shift has already been added to the 2807 // operand list, so we need to pop it off and combine it into the shifted 2808 // register operand instead. 2809 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2810 if (!PrevOp->isReg()) 2811 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2812 int SrcReg = PrevOp->getReg(); 2813 2814 SMLoc EndLoc; 2815 int64_t Imm = 0; 2816 int ShiftReg = 0; 2817 if (ShiftTy == ARM_AM::rrx) { 2818 // RRX Doesn't have an explicit shift amount. The encoder expects 2819 // the shift register to be the same as the source register. Seems odd, 2820 // but OK. 2821 ShiftReg = SrcReg; 2822 } else { 2823 // Figure out if this is shifted by a constant or a register (for non-RRX). 2824 if (Parser.getTok().is(AsmToken::Hash) || 2825 Parser.getTok().is(AsmToken::Dollar)) { 2826 Parser.Lex(); // Eat hash. 2827 SMLoc ImmLoc = Parser.getTok().getLoc(); 2828 const MCExpr *ShiftExpr = 0; 2829 if (getParser().parseExpression(ShiftExpr, EndLoc)) { 2830 Error(ImmLoc, "invalid immediate shift value"); 2831 return -1; 2832 } 2833 // The expression must be evaluatable as an immediate. 2834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2835 if (!CE) { 2836 Error(ImmLoc, "invalid immediate shift value"); 2837 return -1; 2838 } 2839 // Range check the immediate. 2840 // lsl, ror: 0 <= imm <= 31 2841 // lsr, asr: 0 <= imm <= 32 2842 Imm = CE->getValue(); 2843 if (Imm < 0 || 2844 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2845 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2846 Error(ImmLoc, "immediate shift value out of range"); 2847 return -1; 2848 } 2849 // shift by zero is a nop. Always send it through as lsl. 2850 // ('as' compatibility) 2851 if (Imm == 0) 2852 ShiftTy = ARM_AM::lsl; 2853 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2854 SMLoc L = Parser.getTok().getLoc(); 2855 EndLoc = Parser.getTok().getEndLoc(); 2856 ShiftReg = tryParseRegister(); 2857 if (ShiftReg == -1) { 2858 Error (L, "expected immediate or register in shift operand"); 2859 return -1; 2860 } 2861 } else { 2862 Error (Parser.getTok().getLoc(), 2863 "expected immediate or register in shift operand"); 2864 return -1; 2865 } 2866 } 2867 2868 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2869 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2870 ShiftReg, Imm, 2871 S, EndLoc)); 2872 else 2873 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2874 S, EndLoc)); 2875 2876 return 0; 2877} 2878 2879 2880/// Try to parse a register name. The token must be an Identifier when called. 2881/// If it's a register, an AsmOperand is created. Another AsmOperand is created 2882/// if there is a "writeback". 'true' if it's not a register. 2883/// 2884/// TODO this is likely to change to allow different register types and or to 2885/// parse for a specific register type. 2886bool ARMAsmParser:: 2887tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2888 const AsmToken &RegTok = Parser.getTok(); 2889 int RegNo = tryParseRegister(); 2890 if (RegNo == -1) 2891 return true; 2892 2893 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 2894 RegTok.getEndLoc())); 2895 2896 const AsmToken &ExclaimTok = Parser.getTok(); 2897 if (ExclaimTok.is(AsmToken::Exclaim)) { 2898 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2899 ExclaimTok.getLoc())); 2900 Parser.Lex(); // Eat exclaim token 2901 return false; 2902 } 2903 2904 // Also check for an index operand. This is only legal for vector registers, 2905 // but that'll get caught OK in operand matching, so we don't need to 2906 // explicitly filter everything else out here. 2907 if (Parser.getTok().is(AsmToken::LBrac)) { 2908 SMLoc SIdx = Parser.getTok().getLoc(); 2909 Parser.Lex(); // Eat left bracket token. 2910 2911 const MCExpr *ImmVal; 2912 if (getParser().parseExpression(ImmVal)) 2913 return true; 2914 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2915 if (!MCE) 2916 return TokError("immediate value expected for vector index"); 2917 2918 if (Parser.getTok().isNot(AsmToken::RBrac)) 2919 return Error(Parser.getTok().getLoc(), "']' expected"); 2920 2921 SMLoc E = Parser.getTok().getEndLoc(); 2922 Parser.Lex(); // Eat right bracket token. 2923 2924 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2925 SIdx, E, 2926 getContext())); 2927 } 2928 2929 return false; 2930} 2931 2932/// MatchCoprocessorOperandName - Try to parse an coprocessor related 2933/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2934/// "c5", ... 2935static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2936 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2937 // but efficient. 2938 switch (Name.size()) { 2939 default: return -1; 2940 case 2: 2941 if (Name[0] != CoprocOp) 2942 return -1; 2943 switch (Name[1]) { 2944 default: return -1; 2945 case '0': return 0; 2946 case '1': return 1; 2947 case '2': return 2; 2948 case '3': return 3; 2949 case '4': return 4; 2950 case '5': return 5; 2951 case '6': return 6; 2952 case '7': return 7; 2953 case '8': return 8; 2954 case '9': return 9; 2955 } 2956 case 3: 2957 if (Name[0] != CoprocOp || Name[1] != '1') 2958 return -1; 2959 switch (Name[2]) { 2960 default: return -1; 2961 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON) 2962 case '0': return CoprocOp == 'p'? -1: 10; 2963 case '1': return CoprocOp == 'p'? -1: 11; 2964 case '2': return 12; 2965 case '3': return 13; 2966 case '4': return 14; 2967 case '5': return 15; 2968 } 2969 } 2970} 2971 2972/// parseITCondCode - Try to parse a condition code for an IT instruction. 2973ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2974parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2975 SMLoc S = Parser.getTok().getLoc(); 2976 const AsmToken &Tok = Parser.getTok(); 2977 if (!Tok.is(AsmToken::Identifier)) 2978 return MatchOperand_NoMatch; 2979 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 2980 .Case("eq", ARMCC::EQ) 2981 .Case("ne", ARMCC::NE) 2982 .Case("hs", ARMCC::HS) 2983 .Case("cs", ARMCC::HS) 2984 .Case("lo", ARMCC::LO) 2985 .Case("cc", ARMCC::LO) 2986 .Case("mi", ARMCC::MI) 2987 .Case("pl", ARMCC::PL) 2988 .Case("vs", ARMCC::VS) 2989 .Case("vc", ARMCC::VC) 2990 .Case("hi", ARMCC::HI) 2991 .Case("ls", ARMCC::LS) 2992 .Case("ge", ARMCC::GE) 2993 .Case("lt", ARMCC::LT) 2994 .Case("gt", ARMCC::GT) 2995 .Case("le", ARMCC::LE) 2996 .Case("al", ARMCC::AL) 2997 .Default(~0U); 2998 if (CC == ~0U) 2999 return MatchOperand_NoMatch; 3000 Parser.Lex(); // Eat the token. 3001 3002 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 3003 3004 return MatchOperand_Success; 3005} 3006 3007/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 3008/// token must be an Identifier when called, and if it is a coprocessor 3009/// number, the token is eaten and the operand is added to the operand list. 3010ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3011parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3012 SMLoc S = Parser.getTok().getLoc(); 3013 const AsmToken &Tok = Parser.getTok(); 3014 if (Tok.isNot(AsmToken::Identifier)) 3015 return MatchOperand_NoMatch; 3016 3017 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 3018 if (Num == -1) 3019 return MatchOperand_NoMatch; 3020 3021 Parser.Lex(); // Eat identifier token. 3022 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 3023 return MatchOperand_Success; 3024} 3025 3026/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 3027/// token must be an Identifier when called, and if it is a coprocessor 3028/// number, the token is eaten and the operand is added to the operand list. 3029ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3030parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3031 SMLoc S = Parser.getTok().getLoc(); 3032 const AsmToken &Tok = Parser.getTok(); 3033 if (Tok.isNot(AsmToken::Identifier)) 3034 return MatchOperand_NoMatch; 3035 3036 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 3037 if (Reg == -1) 3038 return MatchOperand_NoMatch; 3039 3040 Parser.Lex(); // Eat identifier token. 3041 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 3042 return MatchOperand_Success; 3043} 3044 3045/// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 3046/// coproc_option : '{' imm0_255 '}' 3047ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3048parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3049 SMLoc S = Parser.getTok().getLoc(); 3050 3051 // If this isn't a '{', this isn't a coprocessor immediate operand. 3052 if (Parser.getTok().isNot(AsmToken::LCurly)) 3053 return MatchOperand_NoMatch; 3054 Parser.Lex(); // Eat the '{' 3055 3056 const MCExpr *Expr; 3057 SMLoc Loc = Parser.getTok().getLoc(); 3058 if (getParser().parseExpression(Expr)) { 3059 Error(Loc, "illegal expression"); 3060 return MatchOperand_ParseFail; 3061 } 3062 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 3063 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 3064 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 3065 return MatchOperand_ParseFail; 3066 } 3067 int Val = CE->getValue(); 3068 3069 // Check for and consume the closing '}' 3070 if (Parser.getTok().isNot(AsmToken::RCurly)) 3071 return MatchOperand_ParseFail; 3072 SMLoc E = Parser.getTok().getEndLoc(); 3073 Parser.Lex(); // Eat the '}' 3074 3075 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 3076 return MatchOperand_Success; 3077} 3078 3079// For register list parsing, we need to map from raw GPR register numbering 3080// to the enumeration values. The enumeration values aren't sorted by 3081// register number due to our using "sp", "lr" and "pc" as canonical names. 3082static unsigned getNextRegister(unsigned Reg) { 3083 // If this is a GPR, we need to do it manually, otherwise we can rely 3084 // on the sort ordering of the enumeration since the other reg-classes 3085 // are sane. 3086 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3087 return Reg + 1; 3088 switch(Reg) { 3089 default: llvm_unreachable("Invalid GPR number!"); 3090 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 3091 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 3092 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 3093 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 3094 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 3095 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 3096 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 3097 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 3098 } 3099} 3100 3101// Return the low-subreg of a given Q register. 3102static unsigned getDRegFromQReg(unsigned QReg) { 3103 switch (QReg) { 3104 default: llvm_unreachable("expected a Q register!"); 3105 case ARM::Q0: return ARM::D0; 3106 case ARM::Q1: return ARM::D2; 3107 case ARM::Q2: return ARM::D4; 3108 case ARM::Q3: return ARM::D6; 3109 case ARM::Q4: return ARM::D8; 3110 case ARM::Q5: return ARM::D10; 3111 case ARM::Q6: return ARM::D12; 3112 case ARM::Q7: return ARM::D14; 3113 case ARM::Q8: return ARM::D16; 3114 case ARM::Q9: return ARM::D18; 3115 case ARM::Q10: return ARM::D20; 3116 case ARM::Q11: return ARM::D22; 3117 case ARM::Q12: return ARM::D24; 3118 case ARM::Q13: return ARM::D26; 3119 case ARM::Q14: return ARM::D28; 3120 case ARM::Q15: return ARM::D30; 3121 } 3122} 3123 3124/// Parse a register list. 3125bool ARMAsmParser:: 3126parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3127 assert(Parser.getTok().is(AsmToken::LCurly) && 3128 "Token is not a Left Curly Brace"); 3129 SMLoc S = Parser.getTok().getLoc(); 3130 Parser.Lex(); // Eat '{' token. 3131 SMLoc RegLoc = Parser.getTok().getLoc(); 3132 3133 // Check the first register in the list to see what register class 3134 // this is a list of. 3135 int Reg = tryParseRegister(); 3136 if (Reg == -1) 3137 return Error(RegLoc, "register expected"); 3138 3139 // The reglist instructions have at most 16 registers, so reserve 3140 // space for that many. 3141 int EReg = 0; 3142 SmallVector<std::pair<unsigned, unsigned>, 16> Registers; 3143 3144 // Allow Q regs and just interpret them as the two D sub-registers. 3145 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3146 Reg = getDRegFromQReg(Reg); 3147 EReg = MRI->getEncodingValue(Reg); 3148 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3149 ++Reg; 3150 } 3151 const MCRegisterClass *RC; 3152 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3153 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 3154 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 3155 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 3156 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 3157 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 3158 else 3159 return Error(RegLoc, "invalid register in register list"); 3160 3161 // Store the register. 3162 EReg = MRI->getEncodingValue(Reg); 3163 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3164 3165 // This starts immediately after the first register token in the list, 3166 // so we can see either a comma or a minus (range separator) as a legal 3167 // next token. 3168 while (Parser.getTok().is(AsmToken::Comma) || 3169 Parser.getTok().is(AsmToken::Minus)) { 3170 if (Parser.getTok().is(AsmToken::Minus)) { 3171 Parser.Lex(); // Eat the minus. 3172 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3173 int EndReg = tryParseRegister(); 3174 if (EndReg == -1) 3175 return Error(AfterMinusLoc, "register expected"); 3176 // Allow Q regs and just interpret them as the two D sub-registers. 3177 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3178 EndReg = getDRegFromQReg(EndReg) + 1; 3179 // If the register is the same as the start reg, there's nothing 3180 // more to do. 3181 if (Reg == EndReg) 3182 continue; 3183 // The register must be in the same register class as the first. 3184 if (!RC->contains(EndReg)) 3185 return Error(AfterMinusLoc, "invalid register in register list"); 3186 // Ranges must go from low to high. 3187 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 3188 return Error(AfterMinusLoc, "bad range in register list"); 3189 3190 // Add all the registers in the range to the register list. 3191 while (Reg != EndReg) { 3192 Reg = getNextRegister(Reg); 3193 EReg = MRI->getEncodingValue(Reg); 3194 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3195 } 3196 continue; 3197 } 3198 Parser.Lex(); // Eat the comma. 3199 RegLoc = Parser.getTok().getLoc(); 3200 int OldReg = Reg; 3201 const AsmToken RegTok = Parser.getTok(); 3202 Reg = tryParseRegister(); 3203 if (Reg == -1) 3204 return Error(RegLoc, "register expected"); 3205 // Allow Q regs and just interpret them as the two D sub-registers. 3206 bool isQReg = false; 3207 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3208 Reg = getDRegFromQReg(Reg); 3209 isQReg = true; 3210 } 3211 // The register must be in the same register class as the first. 3212 if (!RC->contains(Reg)) 3213 return Error(RegLoc, "invalid register in register list"); 3214 // List must be monotonically increasing. 3215 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 3216 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3217 Warning(RegLoc, "register list not in ascending order"); 3218 else 3219 return Error(RegLoc, "register list not in ascending order"); 3220 } 3221 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 3222 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 3223 ") in register list"); 3224 continue; 3225 } 3226 // VFP register lists must also be contiguous. 3227 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 3228 Reg != OldReg + 1) 3229 return Error(RegLoc, "non-contiguous register range"); 3230 EReg = MRI->getEncodingValue(Reg); 3231 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3232 if (isQReg) { 3233 EReg = MRI->getEncodingValue(++Reg); 3234 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3235 } 3236 } 3237 3238 if (Parser.getTok().isNot(AsmToken::RCurly)) 3239 return Error(Parser.getTok().getLoc(), "'}' expected"); 3240 SMLoc E = Parser.getTok().getEndLoc(); 3241 Parser.Lex(); // Eat '}' token. 3242 3243 // Push the register list operand. 3244 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 3245 3246 // The ARM system instruction variants for LDM/STM have a '^' token here. 3247 if (Parser.getTok().is(AsmToken::Caret)) { 3248 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 3249 Parser.Lex(); // Eat '^' token. 3250 } 3251 3252 return false; 3253} 3254 3255// Helper function to parse the lane index for vector lists. 3256ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3257parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { 3258 Index = 0; // Always return a defined index value. 3259 if (Parser.getTok().is(AsmToken::LBrac)) { 3260 Parser.Lex(); // Eat the '['. 3261 if (Parser.getTok().is(AsmToken::RBrac)) { 3262 // "Dn[]" is the 'all lanes' syntax. 3263 LaneKind = AllLanes; 3264 EndLoc = Parser.getTok().getEndLoc(); 3265 Parser.Lex(); // Eat the ']'. 3266 return MatchOperand_Success; 3267 } 3268 3269 // There's an optional '#' token here. Normally there wouldn't be, but 3270 // inline assemble puts one in, and it's friendly to accept that. 3271 if (Parser.getTok().is(AsmToken::Hash)) 3272 Parser.Lex(); // Eat '#' or '$'. 3273 3274 const MCExpr *LaneIndex; 3275 SMLoc Loc = Parser.getTok().getLoc(); 3276 if (getParser().parseExpression(LaneIndex)) { 3277 Error(Loc, "illegal expression"); 3278 return MatchOperand_ParseFail; 3279 } 3280 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3281 if (!CE) { 3282 Error(Loc, "lane index must be empty or an integer"); 3283 return MatchOperand_ParseFail; 3284 } 3285 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3286 Error(Parser.getTok().getLoc(), "']' expected"); 3287 return MatchOperand_ParseFail; 3288 } 3289 EndLoc = Parser.getTok().getEndLoc(); 3290 Parser.Lex(); // Eat the ']'. 3291 int64_t Val = CE->getValue(); 3292 3293 // FIXME: Make this range check context sensitive for .8, .16, .32. 3294 if (Val < 0 || Val > 7) { 3295 Error(Parser.getTok().getLoc(), "lane index out of range"); 3296 return MatchOperand_ParseFail; 3297 } 3298 Index = Val; 3299 LaneKind = IndexedLane; 3300 return MatchOperand_Success; 3301 } 3302 LaneKind = NoLanes; 3303 return MatchOperand_Success; 3304} 3305 3306// parse a vector register list 3307ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3308parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3309 VectorLaneTy LaneKind; 3310 unsigned LaneIndex; 3311 SMLoc S = Parser.getTok().getLoc(); 3312 // As an extension (to match gas), support a plain D register or Q register 3313 // (without encosing curly braces) as a single or double entry list, 3314 // respectively. 3315 if (Parser.getTok().is(AsmToken::Identifier)) { 3316 SMLoc E = Parser.getTok().getEndLoc(); 3317 int Reg = tryParseRegister(); 3318 if (Reg == -1) 3319 return MatchOperand_NoMatch; 3320 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3321 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3322 if (Res != MatchOperand_Success) 3323 return Res; 3324 switch (LaneKind) { 3325 case NoLanes: 3326 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3327 break; 3328 case AllLanes: 3329 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3330 S, E)); 3331 break; 3332 case IndexedLane: 3333 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3334 LaneIndex, 3335 false, S, E)); 3336 break; 3337 } 3338 return MatchOperand_Success; 3339 } 3340 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3341 Reg = getDRegFromQReg(Reg); 3342 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3343 if (Res != MatchOperand_Success) 3344 return Res; 3345 switch (LaneKind) { 3346 case NoLanes: 3347 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3348 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3349 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3350 break; 3351 case AllLanes: 3352 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3353 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3354 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3355 S, E)); 3356 break; 3357 case IndexedLane: 3358 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3359 LaneIndex, 3360 false, S, E)); 3361 break; 3362 } 3363 return MatchOperand_Success; 3364 } 3365 Error(S, "vector register expected"); 3366 return MatchOperand_ParseFail; 3367 } 3368 3369 if (Parser.getTok().isNot(AsmToken::LCurly)) 3370 return MatchOperand_NoMatch; 3371 3372 Parser.Lex(); // Eat '{' token. 3373 SMLoc RegLoc = Parser.getTok().getLoc(); 3374 3375 int Reg = tryParseRegister(); 3376 if (Reg == -1) { 3377 Error(RegLoc, "register expected"); 3378 return MatchOperand_ParseFail; 3379 } 3380 unsigned Count = 1; 3381 int Spacing = 0; 3382 unsigned FirstReg = Reg; 3383 // The list is of D registers, but we also allow Q regs and just interpret 3384 // them as the two D sub-registers. 3385 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3386 FirstReg = Reg = getDRegFromQReg(Reg); 3387 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3388 // it's ambiguous with four-register single spaced. 3389 ++Reg; 3390 ++Count; 3391 } 3392 3393 SMLoc E; 3394 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) 3395 return MatchOperand_ParseFail; 3396 3397 while (Parser.getTok().is(AsmToken::Comma) || 3398 Parser.getTok().is(AsmToken::Minus)) { 3399 if (Parser.getTok().is(AsmToken::Minus)) { 3400 if (!Spacing) 3401 Spacing = 1; // Register range implies a single spaced list. 3402 else if (Spacing == 2) { 3403 Error(Parser.getTok().getLoc(), 3404 "sequential registers in double spaced list"); 3405 return MatchOperand_ParseFail; 3406 } 3407 Parser.Lex(); // Eat the minus. 3408 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3409 int EndReg = tryParseRegister(); 3410 if (EndReg == -1) { 3411 Error(AfterMinusLoc, "register expected"); 3412 return MatchOperand_ParseFail; 3413 } 3414 // Allow Q regs and just interpret them as the two D sub-registers. 3415 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3416 EndReg = getDRegFromQReg(EndReg) + 1; 3417 // If the register is the same as the start reg, there's nothing 3418 // more to do. 3419 if (Reg == EndReg) 3420 continue; 3421 // The register must be in the same register class as the first. 3422 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3423 Error(AfterMinusLoc, "invalid register in register list"); 3424 return MatchOperand_ParseFail; 3425 } 3426 // Ranges must go from low to high. 3427 if (Reg > EndReg) { 3428 Error(AfterMinusLoc, "bad range in register list"); 3429 return MatchOperand_ParseFail; 3430 } 3431 // Parse the lane specifier if present. 3432 VectorLaneTy NextLaneKind; 3433 unsigned NextLaneIndex; 3434 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3435 MatchOperand_Success) 3436 return MatchOperand_ParseFail; 3437 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3438 Error(AfterMinusLoc, "mismatched lane index in register list"); 3439 return MatchOperand_ParseFail; 3440 } 3441 3442 // Add all the registers in the range to the register list. 3443 Count += EndReg - Reg; 3444 Reg = EndReg; 3445 continue; 3446 } 3447 Parser.Lex(); // Eat the comma. 3448 RegLoc = Parser.getTok().getLoc(); 3449 int OldReg = Reg; 3450 Reg = tryParseRegister(); 3451 if (Reg == -1) { 3452 Error(RegLoc, "register expected"); 3453 return MatchOperand_ParseFail; 3454 } 3455 // vector register lists must be contiguous. 3456 // It's OK to use the enumeration values directly here rather, as the 3457 // VFP register classes have the enum sorted properly. 3458 // 3459 // The list is of D registers, but we also allow Q regs and just interpret 3460 // them as the two D sub-registers. 3461 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3462 if (!Spacing) 3463 Spacing = 1; // Register range implies a single spaced list. 3464 else if (Spacing == 2) { 3465 Error(RegLoc, 3466 "invalid register in double-spaced list (must be 'D' register')"); 3467 return MatchOperand_ParseFail; 3468 } 3469 Reg = getDRegFromQReg(Reg); 3470 if (Reg != OldReg + 1) { 3471 Error(RegLoc, "non-contiguous register range"); 3472 return MatchOperand_ParseFail; 3473 } 3474 ++Reg; 3475 Count += 2; 3476 // Parse the lane specifier if present. 3477 VectorLaneTy NextLaneKind; 3478 unsigned NextLaneIndex; 3479 SMLoc LaneLoc = Parser.getTok().getLoc(); 3480 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3481 MatchOperand_Success) 3482 return MatchOperand_ParseFail; 3483 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3484 Error(LaneLoc, "mismatched lane index in register list"); 3485 return MatchOperand_ParseFail; 3486 } 3487 continue; 3488 } 3489 // Normal D register. 3490 // Figure out the register spacing (single or double) of the list if 3491 // we don't know it already. 3492 if (!Spacing) 3493 Spacing = 1 + (Reg == OldReg + 2); 3494 3495 // Just check that it's contiguous and keep going. 3496 if (Reg != OldReg + Spacing) { 3497 Error(RegLoc, "non-contiguous register range"); 3498 return MatchOperand_ParseFail; 3499 } 3500 ++Count; 3501 // Parse the lane specifier if present. 3502 VectorLaneTy NextLaneKind; 3503 unsigned NextLaneIndex; 3504 SMLoc EndLoc = Parser.getTok().getLoc(); 3505 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) 3506 return MatchOperand_ParseFail; 3507 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3508 Error(EndLoc, "mismatched lane index in register list"); 3509 return MatchOperand_ParseFail; 3510 } 3511 } 3512 3513 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3514 Error(Parser.getTok().getLoc(), "'}' expected"); 3515 return MatchOperand_ParseFail; 3516 } 3517 E = Parser.getTok().getEndLoc(); 3518 Parser.Lex(); // Eat '}' token. 3519 3520 switch (LaneKind) { 3521 case NoLanes: 3522 // Two-register operands have been converted to the 3523 // composite register classes. 3524 if (Count == 2) { 3525 const MCRegisterClass *RC = (Spacing == 1) ? 3526 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3527 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3528 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3529 } 3530 3531 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3532 (Spacing == 2), S, E)); 3533 break; 3534 case AllLanes: 3535 // Two-register operands have been converted to the 3536 // composite register classes. 3537 if (Count == 2) { 3538 const MCRegisterClass *RC = (Spacing == 1) ? 3539 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3540 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3541 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3542 } 3543 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3544 (Spacing == 2), 3545 S, E)); 3546 break; 3547 case IndexedLane: 3548 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3549 LaneIndex, 3550 (Spacing == 2), 3551 S, E)); 3552 break; 3553 } 3554 return MatchOperand_Success; 3555} 3556 3557/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3558ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3559parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3560 SMLoc S = Parser.getTok().getLoc(); 3561 const AsmToken &Tok = Parser.getTok(); 3562 unsigned Opt; 3563 3564 if (Tok.is(AsmToken::Identifier)) { 3565 StringRef OptStr = Tok.getString(); 3566 3567 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3568 .Case("sy", ARM_MB::SY) 3569 .Case("st", ARM_MB::ST) 3570 .Case("ld", ARM_MB::LD) 3571 .Case("sh", ARM_MB::ISH) 3572 .Case("ish", ARM_MB::ISH) 3573 .Case("shst", ARM_MB::ISHST) 3574 .Case("ishst", ARM_MB::ISHST) 3575 .Case("ishld", ARM_MB::ISHLD) 3576 .Case("nsh", ARM_MB::NSH) 3577 .Case("un", ARM_MB::NSH) 3578 .Case("nshst", ARM_MB::NSHST) 3579 .Case("nshld", ARM_MB::NSHLD) 3580 .Case("unst", ARM_MB::NSHST) 3581 .Case("osh", ARM_MB::OSH) 3582 .Case("oshst", ARM_MB::OSHST) 3583 .Case("oshld", ARM_MB::OSHLD) 3584 .Default(~0U); 3585 3586 // ishld, oshld, nshld and ld are only available from ARMv8. 3587 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || 3588 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) 3589 Opt = ~0U; 3590 3591 if (Opt == ~0U) 3592 return MatchOperand_NoMatch; 3593 3594 Parser.Lex(); // Eat identifier token. 3595 } else if (Tok.is(AsmToken::Hash) || 3596 Tok.is(AsmToken::Dollar) || 3597 Tok.is(AsmToken::Integer)) { 3598 if (Parser.getTok().isNot(AsmToken::Integer)) 3599 Parser.Lex(); // Eat '#' or '$'. 3600 SMLoc Loc = Parser.getTok().getLoc(); 3601 3602 const MCExpr *MemBarrierID; 3603 if (getParser().parseExpression(MemBarrierID)) { 3604 Error(Loc, "illegal expression"); 3605 return MatchOperand_ParseFail; 3606 } 3607 3608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3609 if (!CE) { 3610 Error(Loc, "constant expression expected"); 3611 return MatchOperand_ParseFail; 3612 } 3613 3614 int Val = CE->getValue(); 3615 if (Val & ~0xf) { 3616 Error(Loc, "immediate value out of range"); 3617 return MatchOperand_ParseFail; 3618 } 3619 3620 Opt = ARM_MB::RESERVED_0 + Val; 3621 } else 3622 return MatchOperand_ParseFail; 3623 3624 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3625 return MatchOperand_Success; 3626} 3627 3628/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. 3629ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3630parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3631 SMLoc S = Parser.getTok().getLoc(); 3632 const AsmToken &Tok = Parser.getTok(); 3633 unsigned Opt; 3634 3635 if (Tok.is(AsmToken::Identifier)) { 3636 StringRef OptStr = Tok.getString(); 3637 3638 if (OptStr.equals_lower("sy")) 3639 Opt = ARM_ISB::SY; 3640 else 3641 return MatchOperand_NoMatch; 3642 3643 Parser.Lex(); // Eat identifier token. 3644 } else if (Tok.is(AsmToken::Hash) || 3645 Tok.is(AsmToken::Dollar) || 3646 Tok.is(AsmToken::Integer)) { 3647 if (Parser.getTok().isNot(AsmToken::Integer)) 3648 Parser.Lex(); // Eat '#' or '$'. 3649 SMLoc Loc = Parser.getTok().getLoc(); 3650 3651 const MCExpr *ISBarrierID; 3652 if (getParser().parseExpression(ISBarrierID)) { 3653 Error(Loc, "illegal expression"); 3654 return MatchOperand_ParseFail; 3655 } 3656 3657 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); 3658 if (!CE) { 3659 Error(Loc, "constant expression expected"); 3660 return MatchOperand_ParseFail; 3661 } 3662 3663 int Val = CE->getValue(); 3664 if (Val & ~0xf) { 3665 Error(Loc, "immediate value out of range"); 3666 return MatchOperand_ParseFail; 3667 } 3668 3669 Opt = ARM_ISB::RESERVED_0 + Val; 3670 } else 3671 return MatchOperand_ParseFail; 3672 3673 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( 3674 (ARM_ISB::InstSyncBOpt)Opt, S)); 3675 return MatchOperand_Success; 3676} 3677 3678 3679/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3680ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3681parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3682 SMLoc S = Parser.getTok().getLoc(); 3683 const AsmToken &Tok = Parser.getTok(); 3684 if (!Tok.is(AsmToken::Identifier)) 3685 return MatchOperand_NoMatch; 3686 StringRef IFlagsStr = Tok.getString(); 3687 3688 // An iflags string of "none" is interpreted to mean that none of the AIF 3689 // bits are set. Not a terribly useful instruction, but a valid encoding. 3690 unsigned IFlags = 0; 3691 if (IFlagsStr != "none") { 3692 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3693 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3694 .Case("a", ARM_PROC::A) 3695 .Case("i", ARM_PROC::I) 3696 .Case("f", ARM_PROC::F) 3697 .Default(~0U); 3698 3699 // If some specific iflag is already set, it means that some letter is 3700 // present more than once, this is not acceptable. 3701 if (Flag == ~0U || (IFlags & Flag)) 3702 return MatchOperand_NoMatch; 3703 3704 IFlags |= Flag; 3705 } 3706 } 3707 3708 Parser.Lex(); // Eat identifier token. 3709 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3710 return MatchOperand_Success; 3711} 3712 3713/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3714ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3715parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3716 SMLoc S = Parser.getTok().getLoc(); 3717 const AsmToken &Tok = Parser.getTok(); 3718 if (!Tok.is(AsmToken::Identifier)) 3719 return MatchOperand_NoMatch; 3720 StringRef Mask = Tok.getString(); 3721 3722 if (isMClass()) { 3723 // See ARMv6-M 10.1.1 3724 std::string Name = Mask.lower(); 3725 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3726 // Note: in the documentation: 3727 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3728 // for MSR APSR_nzcvq. 3729 // but we do make it an alias here. This is so to get the "mask encoding" 3730 // bits correct on MSR APSR writes. 3731 // 3732 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3733 // should really only be allowed when writing a special register. Note 3734 // they get dropped in the MRS instruction reading a special register as 3735 // the SYSm field is only 8 bits. 3736 // 3737 // FIXME: the _g and _nzcvqg versions are only allowed if the processor 3738 // includes the DSP extension but that is not checked. 3739 .Case("apsr", 0x800) 3740 .Case("apsr_nzcvq", 0x800) 3741 .Case("apsr_g", 0x400) 3742 .Case("apsr_nzcvqg", 0xc00) 3743 .Case("iapsr", 0x801) 3744 .Case("iapsr_nzcvq", 0x801) 3745 .Case("iapsr_g", 0x401) 3746 .Case("iapsr_nzcvqg", 0xc01) 3747 .Case("eapsr", 0x802) 3748 .Case("eapsr_nzcvq", 0x802) 3749 .Case("eapsr_g", 0x402) 3750 .Case("eapsr_nzcvqg", 0xc02) 3751 .Case("xpsr", 0x803) 3752 .Case("xpsr_nzcvq", 0x803) 3753 .Case("xpsr_g", 0x403) 3754 .Case("xpsr_nzcvqg", 0xc03) 3755 .Case("ipsr", 0x805) 3756 .Case("epsr", 0x806) 3757 .Case("iepsr", 0x807) 3758 .Case("msp", 0x808) 3759 .Case("psp", 0x809) 3760 .Case("primask", 0x810) 3761 .Case("basepri", 0x811) 3762 .Case("basepri_max", 0x812) 3763 .Case("faultmask", 0x813) 3764 .Case("control", 0x814) 3765 .Default(~0U); 3766 3767 if (FlagsVal == ~0U) 3768 return MatchOperand_NoMatch; 3769 3770 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3771 // basepri, basepri_max and faultmask only valid for V7m. 3772 return MatchOperand_NoMatch; 3773 3774 Parser.Lex(); // Eat identifier token. 3775 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3776 return MatchOperand_Success; 3777 } 3778 3779 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3780 size_t Start = 0, Next = Mask.find('_'); 3781 StringRef Flags = ""; 3782 std::string SpecReg = Mask.slice(Start, Next).lower(); 3783 if (Next != StringRef::npos) 3784 Flags = Mask.slice(Next+1, Mask.size()); 3785 3786 // FlagsVal contains the complete mask: 3787 // 3-0: Mask 3788 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3789 unsigned FlagsVal = 0; 3790 3791 if (SpecReg == "apsr") { 3792 FlagsVal = StringSwitch<unsigned>(Flags) 3793 .Case("nzcvq", 0x8) // same as CPSR_f 3794 .Case("g", 0x4) // same as CPSR_s 3795 .Case("nzcvqg", 0xc) // same as CPSR_fs 3796 .Default(~0U); 3797 3798 if (FlagsVal == ~0U) { 3799 if (!Flags.empty()) 3800 return MatchOperand_NoMatch; 3801 else 3802 FlagsVal = 8; // No flag 3803 } 3804 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3805 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3806 if (Flags == "all" || Flags == "") 3807 Flags = "fc"; 3808 for (int i = 0, e = Flags.size(); i != e; ++i) { 3809 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3810 .Case("c", 1) 3811 .Case("x", 2) 3812 .Case("s", 4) 3813 .Case("f", 8) 3814 .Default(~0U); 3815 3816 // If some specific flag is already set, it means that some letter is 3817 // present more than once, this is not acceptable. 3818 if (FlagsVal == ~0U || (FlagsVal & Flag)) 3819 return MatchOperand_NoMatch; 3820 FlagsVal |= Flag; 3821 } 3822 } else // No match for special register. 3823 return MatchOperand_NoMatch; 3824 3825 // Special register without flags is NOT equivalent to "fc" flags. 3826 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 3827 // two lines would enable gas compatibility at the expense of breaking 3828 // round-tripping. 3829 // 3830 // if (!FlagsVal) 3831 // FlagsVal = 0x9; 3832 3833 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3834 if (SpecReg == "spsr") 3835 FlagsVal |= 16; 3836 3837 Parser.Lex(); // Eat identifier token. 3838 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3839 return MatchOperand_Success; 3840} 3841 3842ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3843parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3844 int Low, int High) { 3845 const AsmToken &Tok = Parser.getTok(); 3846 if (Tok.isNot(AsmToken::Identifier)) { 3847 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3848 return MatchOperand_ParseFail; 3849 } 3850 StringRef ShiftName = Tok.getString(); 3851 std::string LowerOp = Op.lower(); 3852 std::string UpperOp = Op.upper(); 3853 if (ShiftName != LowerOp && ShiftName != UpperOp) { 3854 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3855 return MatchOperand_ParseFail; 3856 } 3857 Parser.Lex(); // Eat shift type token. 3858 3859 // There must be a '#' and a shift amount. 3860 if (Parser.getTok().isNot(AsmToken::Hash) && 3861 Parser.getTok().isNot(AsmToken::Dollar)) { 3862 Error(Parser.getTok().getLoc(), "'#' expected"); 3863 return MatchOperand_ParseFail; 3864 } 3865 Parser.Lex(); // Eat hash token. 3866 3867 const MCExpr *ShiftAmount; 3868 SMLoc Loc = Parser.getTok().getLoc(); 3869 SMLoc EndLoc; 3870 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3871 Error(Loc, "illegal expression"); 3872 return MatchOperand_ParseFail; 3873 } 3874 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3875 if (!CE) { 3876 Error(Loc, "constant expression expected"); 3877 return MatchOperand_ParseFail; 3878 } 3879 int Val = CE->getValue(); 3880 if (Val < Low || Val > High) { 3881 Error(Loc, "immediate value out of range"); 3882 return MatchOperand_ParseFail; 3883 } 3884 3885 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); 3886 3887 return MatchOperand_Success; 3888} 3889 3890ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3891parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3892 const AsmToken &Tok = Parser.getTok(); 3893 SMLoc S = Tok.getLoc(); 3894 if (Tok.isNot(AsmToken::Identifier)) { 3895 Error(S, "'be' or 'le' operand expected"); 3896 return MatchOperand_ParseFail; 3897 } 3898 int Val = StringSwitch<int>(Tok.getString().lower()) 3899 .Case("be", 1) 3900 .Case("le", 0) 3901 .Default(-1); 3902 Parser.Lex(); // Eat the token. 3903 3904 if (Val == -1) { 3905 Error(S, "'be' or 'le' operand expected"); 3906 return MatchOperand_ParseFail; 3907 } 3908 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3909 getContext()), 3910 S, Tok.getEndLoc())); 3911 return MatchOperand_Success; 3912} 3913 3914/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3915/// instructions. Legal values are: 3916/// lsl #n 'n' in [0,31] 3917/// asr #n 'n' in [1,32] 3918/// n == 32 encoded as n == 0. 3919ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3920parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3921 const AsmToken &Tok = Parser.getTok(); 3922 SMLoc S = Tok.getLoc(); 3923 if (Tok.isNot(AsmToken::Identifier)) { 3924 Error(S, "shift operator 'asr' or 'lsl' expected"); 3925 return MatchOperand_ParseFail; 3926 } 3927 StringRef ShiftName = Tok.getString(); 3928 bool isASR; 3929 if (ShiftName == "lsl" || ShiftName == "LSL") 3930 isASR = false; 3931 else if (ShiftName == "asr" || ShiftName == "ASR") 3932 isASR = true; 3933 else { 3934 Error(S, "shift operator 'asr' or 'lsl' expected"); 3935 return MatchOperand_ParseFail; 3936 } 3937 Parser.Lex(); // Eat the operator. 3938 3939 // A '#' and a shift amount. 3940 if (Parser.getTok().isNot(AsmToken::Hash) && 3941 Parser.getTok().isNot(AsmToken::Dollar)) { 3942 Error(Parser.getTok().getLoc(), "'#' expected"); 3943 return MatchOperand_ParseFail; 3944 } 3945 Parser.Lex(); // Eat hash token. 3946 SMLoc ExLoc = Parser.getTok().getLoc(); 3947 3948 const MCExpr *ShiftAmount; 3949 SMLoc EndLoc; 3950 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3951 Error(ExLoc, "malformed shift expression"); 3952 return MatchOperand_ParseFail; 3953 } 3954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3955 if (!CE) { 3956 Error(ExLoc, "shift amount must be an immediate"); 3957 return MatchOperand_ParseFail; 3958 } 3959 3960 int64_t Val = CE->getValue(); 3961 if (isASR) { 3962 // Shift amount must be in [1,32] 3963 if (Val < 1 || Val > 32) { 3964 Error(ExLoc, "'asr' shift amount must be in range [1,32]"); 3965 return MatchOperand_ParseFail; 3966 } 3967 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 3968 if (isThumb() && Val == 32) { 3969 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); 3970 return MatchOperand_ParseFail; 3971 } 3972 if (Val == 32) Val = 0; 3973 } else { 3974 // Shift amount must be in [1,32] 3975 if (Val < 0 || Val > 31) { 3976 Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); 3977 return MatchOperand_ParseFail; 3978 } 3979 } 3980 3981 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); 3982 3983 return MatchOperand_Success; 3984} 3985 3986/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 3987/// of instructions. Legal values are: 3988/// ror #n 'n' in {0, 8, 16, 24} 3989ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3990parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3991 const AsmToken &Tok = Parser.getTok(); 3992 SMLoc S = Tok.getLoc(); 3993 if (Tok.isNot(AsmToken::Identifier)) 3994 return MatchOperand_NoMatch; 3995 StringRef ShiftName = Tok.getString(); 3996 if (ShiftName != "ror" && ShiftName != "ROR") 3997 return MatchOperand_NoMatch; 3998 Parser.Lex(); // Eat the operator. 3999 4000 // A '#' and a rotate amount. 4001 if (Parser.getTok().isNot(AsmToken::Hash) && 4002 Parser.getTok().isNot(AsmToken::Dollar)) { 4003 Error(Parser.getTok().getLoc(), "'#' expected"); 4004 return MatchOperand_ParseFail; 4005 } 4006 Parser.Lex(); // Eat hash token. 4007 SMLoc ExLoc = Parser.getTok().getLoc(); 4008 4009 const MCExpr *ShiftAmount; 4010 SMLoc EndLoc; 4011 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4012 Error(ExLoc, "malformed rotate expression"); 4013 return MatchOperand_ParseFail; 4014 } 4015 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4016 if (!CE) { 4017 Error(ExLoc, "rotate amount must be an immediate"); 4018 return MatchOperand_ParseFail; 4019 } 4020 4021 int64_t Val = CE->getValue(); 4022 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 4023 // normally, zero is represented in asm by omitting the rotate operand 4024 // entirely. 4025 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 4026 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 4027 return MatchOperand_ParseFail; 4028 } 4029 4030 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 4031 4032 return MatchOperand_Success; 4033} 4034 4035ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4036parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4037 SMLoc S = Parser.getTok().getLoc(); 4038 // The bitfield descriptor is really two operands, the LSB and the width. 4039 if (Parser.getTok().isNot(AsmToken::Hash) && 4040 Parser.getTok().isNot(AsmToken::Dollar)) { 4041 Error(Parser.getTok().getLoc(), "'#' expected"); 4042 return MatchOperand_ParseFail; 4043 } 4044 Parser.Lex(); // Eat hash token. 4045 4046 const MCExpr *LSBExpr; 4047 SMLoc E = Parser.getTok().getLoc(); 4048 if (getParser().parseExpression(LSBExpr)) { 4049 Error(E, "malformed immediate expression"); 4050 return MatchOperand_ParseFail; 4051 } 4052 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 4053 if (!CE) { 4054 Error(E, "'lsb' operand must be an immediate"); 4055 return MatchOperand_ParseFail; 4056 } 4057 4058 int64_t LSB = CE->getValue(); 4059 // The LSB must be in the range [0,31] 4060 if (LSB < 0 || LSB > 31) { 4061 Error(E, "'lsb' operand must be in the range [0,31]"); 4062 return MatchOperand_ParseFail; 4063 } 4064 E = Parser.getTok().getLoc(); 4065 4066 // Expect another immediate operand. 4067 if (Parser.getTok().isNot(AsmToken::Comma)) { 4068 Error(Parser.getTok().getLoc(), "too few operands"); 4069 return MatchOperand_ParseFail; 4070 } 4071 Parser.Lex(); // Eat hash token. 4072 if (Parser.getTok().isNot(AsmToken::Hash) && 4073 Parser.getTok().isNot(AsmToken::Dollar)) { 4074 Error(Parser.getTok().getLoc(), "'#' expected"); 4075 return MatchOperand_ParseFail; 4076 } 4077 Parser.Lex(); // Eat hash token. 4078 4079 const MCExpr *WidthExpr; 4080 SMLoc EndLoc; 4081 if (getParser().parseExpression(WidthExpr, EndLoc)) { 4082 Error(E, "malformed immediate expression"); 4083 return MatchOperand_ParseFail; 4084 } 4085 CE = dyn_cast<MCConstantExpr>(WidthExpr); 4086 if (!CE) { 4087 Error(E, "'width' operand must be an immediate"); 4088 return MatchOperand_ParseFail; 4089 } 4090 4091 int64_t Width = CE->getValue(); 4092 // The LSB must be in the range [1,32-lsb] 4093 if (Width < 1 || Width > 32 - LSB) { 4094 Error(E, "'width' operand must be in the range [1,32-lsb]"); 4095 return MatchOperand_ParseFail; 4096 } 4097 4098 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); 4099 4100 return MatchOperand_Success; 4101} 4102 4103ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4104parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4105 // Check for a post-index addressing register operand. Specifically: 4106 // postidx_reg := '+' register {, shift} 4107 // | '-' register {, shift} 4108 // | register {, shift} 4109 4110 // This method must return MatchOperand_NoMatch without consuming any tokens 4111 // in the case where there is no match, as other alternatives take other 4112 // parse methods. 4113 AsmToken Tok = Parser.getTok(); 4114 SMLoc S = Tok.getLoc(); 4115 bool haveEaten = false; 4116 bool isAdd = true; 4117 if (Tok.is(AsmToken::Plus)) { 4118 Parser.Lex(); // Eat the '+' token. 4119 haveEaten = true; 4120 } else if (Tok.is(AsmToken::Minus)) { 4121 Parser.Lex(); // Eat the '-' token. 4122 isAdd = false; 4123 haveEaten = true; 4124 } 4125 4126 SMLoc E = Parser.getTok().getEndLoc(); 4127 int Reg = tryParseRegister(); 4128 if (Reg == -1) { 4129 if (!haveEaten) 4130 return MatchOperand_NoMatch; 4131 Error(Parser.getTok().getLoc(), "register expected"); 4132 return MatchOperand_ParseFail; 4133 } 4134 4135 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 4136 unsigned ShiftImm = 0; 4137 if (Parser.getTok().is(AsmToken::Comma)) { 4138 Parser.Lex(); // Eat the ','. 4139 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 4140 return MatchOperand_ParseFail; 4141 4142 // FIXME: Only approximates end...may include intervening whitespace. 4143 E = Parser.getTok().getLoc(); 4144 } 4145 4146 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 4147 ShiftImm, S, E)); 4148 4149 return MatchOperand_Success; 4150} 4151 4152ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4153parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4154 // Check for a post-index addressing register operand. Specifically: 4155 // am3offset := '+' register 4156 // | '-' register 4157 // | register 4158 // | # imm 4159 // | # + imm 4160 // | # - imm 4161 4162 // This method must return MatchOperand_NoMatch without consuming any tokens 4163 // in the case where there is no match, as other alternatives take other 4164 // parse methods. 4165 AsmToken Tok = Parser.getTok(); 4166 SMLoc S = Tok.getLoc(); 4167 4168 // Do immediates first, as we always parse those if we have a '#'. 4169 if (Parser.getTok().is(AsmToken::Hash) || 4170 Parser.getTok().is(AsmToken::Dollar)) { 4171 Parser.Lex(); // Eat '#' or '$'. 4172 // Explicitly look for a '-', as we need to encode negative zero 4173 // differently. 4174 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4175 const MCExpr *Offset; 4176 SMLoc E; 4177 if (getParser().parseExpression(Offset, E)) 4178 return MatchOperand_ParseFail; 4179 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4180 if (!CE) { 4181 Error(S, "constant expression expected"); 4182 return MatchOperand_ParseFail; 4183 } 4184 // Negative zero is encoded as the flag value INT32_MIN. 4185 int32_t Val = CE->getValue(); 4186 if (isNegative && Val == 0) 4187 Val = INT32_MIN; 4188 4189 Operands.push_back( 4190 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 4191 4192 return MatchOperand_Success; 4193 } 4194 4195 4196 bool haveEaten = false; 4197 bool isAdd = true; 4198 if (Tok.is(AsmToken::Plus)) { 4199 Parser.Lex(); // Eat the '+' token. 4200 haveEaten = true; 4201 } else if (Tok.is(AsmToken::Minus)) { 4202 Parser.Lex(); // Eat the '-' token. 4203 isAdd = false; 4204 haveEaten = true; 4205 } 4206 4207 Tok = Parser.getTok(); 4208 int Reg = tryParseRegister(); 4209 if (Reg == -1) { 4210 if (!haveEaten) 4211 return MatchOperand_NoMatch; 4212 Error(Tok.getLoc(), "register expected"); 4213 return MatchOperand_ParseFail; 4214 } 4215 4216 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 4217 0, S, Tok.getEndLoc())); 4218 4219 return MatchOperand_Success; 4220} 4221 4222/// Convert parsed operands to MCInst. Needed here because this instruction 4223/// only has two register operands, but multiplication is commutative so 4224/// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". 4225void ARMAsmParser:: 4226cvtThumbMultiply(MCInst &Inst, 4227 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4228 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4229 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 4230 // If we have a three-operand form, make sure to set Rn to be the operand 4231 // that isn't the same as Rd. 4232 unsigned RegOp = 4; 4233 if (Operands.size() == 6 && 4234 ((ARMOperand*)Operands[4])->getReg() == 4235 ((ARMOperand*)Operands[3])->getReg()) 4236 RegOp = 5; 4237 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 4238 Inst.addOperand(Inst.getOperand(0)); 4239 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 4240} 4241 4242void ARMAsmParser:: 4243cvtThumbBranches(MCInst &Inst, 4244 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4245 int CondOp = -1, ImmOp = -1; 4246 switch(Inst.getOpcode()) { 4247 case ARM::tB: 4248 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; 4249 4250 case ARM::t2B: 4251 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; 4252 4253 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches"); 4254 } 4255 // first decide whether or not the branch should be conditional 4256 // by looking at it's location relative to an IT block 4257 if(inITBlock()) { 4258 // inside an IT block we cannot have any conditional branches. any 4259 // such instructions needs to be converted to unconditional form 4260 switch(Inst.getOpcode()) { 4261 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; 4262 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; 4263 } 4264 } else { 4265 // outside IT blocks we can only have unconditional branches with AL 4266 // condition code or conditional branches with non-AL condition code 4267 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode(); 4268 switch(Inst.getOpcode()) { 4269 case ARM::tB: 4270 case ARM::tBcc: 4271 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); 4272 break; 4273 case ARM::t2B: 4274 case ARM::t2Bcc: 4275 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); 4276 break; 4277 } 4278 } 4279 4280 // now decide on encoding size based on branch target range 4281 switch(Inst.getOpcode()) { 4282 // classify tB as either t2B or t1B based on range of immediate operand 4283 case ARM::tB: { 4284 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]); 4285 if(!op->isSignedOffset<11, 1>() && isThumbTwo()) 4286 Inst.setOpcode(ARM::t2B); 4287 break; 4288 } 4289 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand 4290 case ARM::tBcc: { 4291 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]); 4292 if(!op->isSignedOffset<8, 1>() && isThumbTwo()) 4293 Inst.setOpcode(ARM::t2Bcc); 4294 break; 4295 } 4296 } 4297 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1); 4298 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2); 4299} 4300 4301/// Parse an ARM memory expression, return false if successful else return true 4302/// or an error. The first token must be a '[' when called. 4303bool ARMAsmParser:: 4304parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4305 SMLoc S, E; 4306 assert(Parser.getTok().is(AsmToken::LBrac) && 4307 "Token is not a Left Bracket"); 4308 S = Parser.getTok().getLoc(); 4309 Parser.Lex(); // Eat left bracket token. 4310 4311 const AsmToken &BaseRegTok = Parser.getTok(); 4312 int BaseRegNum = tryParseRegister(); 4313 if (BaseRegNum == -1) 4314 return Error(BaseRegTok.getLoc(), "register expected"); 4315 4316 // The next token must either be a comma, a colon or a closing bracket. 4317 const AsmToken &Tok = Parser.getTok(); 4318 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && 4319 !Tok.is(AsmToken::RBrac)) 4320 return Error(Tok.getLoc(), "malformed memory operand"); 4321 4322 if (Tok.is(AsmToken::RBrac)) { 4323 E = Tok.getEndLoc(); 4324 Parser.Lex(); // Eat right bracket token. 4325 4326 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 4327 0, 0, false, S, E)); 4328 4329 // If there's a pre-indexing writeback marker, '!', just add it as a token 4330 // operand. It's rather odd, but syntactically valid. 4331 if (Parser.getTok().is(AsmToken::Exclaim)) { 4332 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4333 Parser.Lex(); // Eat the '!'. 4334 } 4335 4336 return false; 4337 } 4338 4339 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && 4340 "Lost colon or comma in memory operand?!"); 4341 if (Tok.is(AsmToken::Comma)) { 4342 Parser.Lex(); // Eat the comma. 4343 } 4344 4345 // If we have a ':', it's an alignment specifier. 4346 if (Parser.getTok().is(AsmToken::Colon)) { 4347 Parser.Lex(); // Eat the ':'. 4348 E = Parser.getTok().getLoc(); 4349 4350 const MCExpr *Expr; 4351 if (getParser().parseExpression(Expr)) 4352 return true; 4353 4354 // The expression has to be a constant. Memory references with relocations 4355 // don't come through here, as they use the <label> forms of the relevant 4356 // instructions. 4357 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4358 if (!CE) 4359 return Error (E, "constant expression expected"); 4360 4361 unsigned Align = 0; 4362 switch (CE->getValue()) { 4363 default: 4364 return Error(E, 4365 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4366 case 16: Align = 2; break; 4367 case 32: Align = 4; break; 4368 case 64: Align = 8; break; 4369 case 128: Align = 16; break; 4370 case 256: Align = 32; break; 4371 } 4372 4373 // Now we should have the closing ']' 4374 if (Parser.getTok().isNot(AsmToken::RBrac)) 4375 return Error(Parser.getTok().getLoc(), "']' expected"); 4376 E = Parser.getTok().getEndLoc(); 4377 Parser.Lex(); // Eat right bracket token. 4378 4379 // Don't worry about range checking the value here. That's handled by 4380 // the is*() predicates. 4381 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 4382 ARM_AM::no_shift, 0, Align, 4383 false, S, E)); 4384 4385 // If there's a pre-indexing writeback marker, '!', just add it as a token 4386 // operand. 4387 if (Parser.getTok().is(AsmToken::Exclaim)) { 4388 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4389 Parser.Lex(); // Eat the '!'. 4390 } 4391 4392 return false; 4393 } 4394 4395 // If we have a '#', it's an immediate offset, else assume it's a register 4396 // offset. Be friendly and also accept a plain integer (without a leading 4397 // hash) for gas compatibility. 4398 if (Parser.getTok().is(AsmToken::Hash) || 4399 Parser.getTok().is(AsmToken::Dollar) || 4400 Parser.getTok().is(AsmToken::Integer)) { 4401 if (Parser.getTok().isNot(AsmToken::Integer)) 4402 Parser.Lex(); // Eat '#' or '$'. 4403 E = Parser.getTok().getLoc(); 4404 4405 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4406 const MCExpr *Offset; 4407 if (getParser().parseExpression(Offset)) 4408 return true; 4409 4410 // The expression has to be a constant. Memory references with relocations 4411 // don't come through here, as they use the <label> forms of the relevant 4412 // instructions. 4413 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4414 if (!CE) 4415 return Error (E, "constant expression expected"); 4416 4417 // If the constant was #-0, represent it as INT32_MIN. 4418 int32_t Val = CE->getValue(); 4419 if (isNegative && Val == 0) 4420 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 4421 4422 // Now we should have the closing ']' 4423 if (Parser.getTok().isNot(AsmToken::RBrac)) 4424 return Error(Parser.getTok().getLoc(), "']' expected"); 4425 E = Parser.getTok().getEndLoc(); 4426 Parser.Lex(); // Eat right bracket token. 4427 4428 // Don't worry about range checking the value here. That's handled by 4429 // the is*() predicates. 4430 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4431 ARM_AM::no_shift, 0, 0, 4432 false, S, E)); 4433 4434 // If there's a pre-indexing writeback marker, '!', just add it as a token 4435 // operand. 4436 if (Parser.getTok().is(AsmToken::Exclaim)) { 4437 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4438 Parser.Lex(); // Eat the '!'. 4439 } 4440 4441 return false; 4442 } 4443 4444 // The register offset is optionally preceded by a '+' or '-' 4445 bool isNegative = false; 4446 if (Parser.getTok().is(AsmToken::Minus)) { 4447 isNegative = true; 4448 Parser.Lex(); // Eat the '-'. 4449 } else if (Parser.getTok().is(AsmToken::Plus)) { 4450 // Nothing to do. 4451 Parser.Lex(); // Eat the '+'. 4452 } 4453 4454 E = Parser.getTok().getLoc(); 4455 int OffsetRegNum = tryParseRegister(); 4456 if (OffsetRegNum == -1) 4457 return Error(E, "register expected"); 4458 4459 // If there's a shift operator, handle it. 4460 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4461 unsigned ShiftImm = 0; 4462 if (Parser.getTok().is(AsmToken::Comma)) { 4463 Parser.Lex(); // Eat the ','. 4464 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4465 return true; 4466 } 4467 4468 // Now we should have the closing ']' 4469 if (Parser.getTok().isNot(AsmToken::RBrac)) 4470 return Error(Parser.getTok().getLoc(), "']' expected"); 4471 E = Parser.getTok().getEndLoc(); 4472 Parser.Lex(); // Eat right bracket token. 4473 4474 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 4475 ShiftType, ShiftImm, 0, isNegative, 4476 S, E)); 4477 4478 // If there's a pre-indexing writeback marker, '!', just add it as a token 4479 // operand. 4480 if (Parser.getTok().is(AsmToken::Exclaim)) { 4481 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4482 Parser.Lex(); // Eat the '!'. 4483 } 4484 4485 return false; 4486} 4487 4488/// parseMemRegOffsetShift - one of these two: 4489/// ( lsl | lsr | asr | ror ) , # shift_amount 4490/// rrx 4491/// return true if it parses a shift otherwise it returns false. 4492bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4493 unsigned &Amount) { 4494 SMLoc Loc = Parser.getTok().getLoc(); 4495 const AsmToken &Tok = Parser.getTok(); 4496 if (Tok.isNot(AsmToken::Identifier)) 4497 return true; 4498 StringRef ShiftName = Tok.getString(); 4499 if (ShiftName == "lsl" || ShiftName == "LSL" || 4500 ShiftName == "asl" || ShiftName == "ASL") 4501 St = ARM_AM::lsl; 4502 else if (ShiftName == "lsr" || ShiftName == "LSR") 4503 St = ARM_AM::lsr; 4504 else if (ShiftName == "asr" || ShiftName == "ASR") 4505 St = ARM_AM::asr; 4506 else if (ShiftName == "ror" || ShiftName == "ROR") 4507 St = ARM_AM::ror; 4508 else if (ShiftName == "rrx" || ShiftName == "RRX") 4509 St = ARM_AM::rrx; 4510 else 4511 return Error(Loc, "illegal shift operator"); 4512 Parser.Lex(); // Eat shift type token. 4513 4514 // rrx stands alone. 4515 Amount = 0; 4516 if (St != ARM_AM::rrx) { 4517 Loc = Parser.getTok().getLoc(); 4518 // A '#' and a shift amount. 4519 const AsmToken &HashTok = Parser.getTok(); 4520 if (HashTok.isNot(AsmToken::Hash) && 4521 HashTok.isNot(AsmToken::Dollar)) 4522 return Error(HashTok.getLoc(), "'#' expected"); 4523 Parser.Lex(); // Eat hash token. 4524 4525 const MCExpr *Expr; 4526 if (getParser().parseExpression(Expr)) 4527 return true; 4528 // Range check the immediate. 4529 // lsl, ror: 0 <= imm <= 31 4530 // lsr, asr: 0 <= imm <= 32 4531 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4532 if (!CE) 4533 return Error(Loc, "shift amount must be an immediate"); 4534 int64_t Imm = CE->getValue(); 4535 if (Imm < 0 || 4536 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4537 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4538 return Error(Loc, "immediate shift value out of range"); 4539 // If <ShiftTy> #0, turn it into a no_shift. 4540 if (Imm == 0) 4541 St = ARM_AM::lsl; 4542 // For consistency, treat lsr #32 and asr #32 as having immediate value 0. 4543 if (Imm == 32) 4544 Imm = 0; 4545 Amount = Imm; 4546 } 4547 4548 return false; 4549} 4550 4551/// parseFPImm - A floating point immediate expression operand. 4552ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4553parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4554 // Anything that can accept a floating point constant as an operand 4555 // needs to go through here, as the regular parseExpression is 4556 // integer only. 4557 // 4558 // This routine still creates a generic Immediate operand, containing 4559 // a bitcast of the 64-bit floating point value. The various operands 4560 // that accept floats can check whether the value is valid for them 4561 // via the standard is*() predicates. 4562 4563 SMLoc S = Parser.getTok().getLoc(); 4564 4565 if (Parser.getTok().isNot(AsmToken::Hash) && 4566 Parser.getTok().isNot(AsmToken::Dollar)) 4567 return MatchOperand_NoMatch; 4568 4569 // Disambiguate the VMOV forms that can accept an FP immediate. 4570 // vmov.f32 <sreg>, #imm 4571 // vmov.f64 <dreg>, #imm 4572 // vmov.f32 <dreg>, #imm @ vector f32x2 4573 // vmov.f32 <qreg>, #imm @ vector f32x4 4574 // 4575 // There are also the NEON VMOV instructions which expect an 4576 // integer constant. Make sure we don't try to parse an FPImm 4577 // for these: 4578 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4579 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 4580 bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" || 4581 TyOp->getToken() == ".f64"); 4582 ARMOperand *Mnemonic = static_cast<ARMOperand*>(Operands[0]); 4583 bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" || 4584 Mnemonic->getToken() == "fconsts"); 4585 if (!(isVmovf || isFconst)) 4586 return MatchOperand_NoMatch; 4587 4588 Parser.Lex(); // Eat '#' or '$'. 4589 4590 // Handle negation, as that still comes through as a separate token. 4591 bool isNegative = false; 4592 if (Parser.getTok().is(AsmToken::Minus)) { 4593 isNegative = true; 4594 Parser.Lex(); 4595 } 4596 const AsmToken &Tok = Parser.getTok(); 4597 SMLoc Loc = Tok.getLoc(); 4598 if (Tok.is(AsmToken::Real) && isVmovf) { 4599 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4600 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4601 // If we had a '-' in front, toggle the sign bit. 4602 IntVal ^= (uint64_t)isNegative << 31; 4603 Parser.Lex(); // Eat the token. 4604 Operands.push_back(ARMOperand::CreateImm( 4605 MCConstantExpr::Create(IntVal, getContext()), 4606 S, Parser.getTok().getLoc())); 4607 return MatchOperand_Success; 4608 } 4609 // Also handle plain integers. Instructions which allow floating point 4610 // immediates also allow a raw encoded 8-bit value. 4611 if (Tok.is(AsmToken::Integer) && isFconst) { 4612 int64_t Val = Tok.getIntVal(); 4613 Parser.Lex(); // Eat the token. 4614 if (Val > 255 || Val < 0) { 4615 Error(Loc, "encoded floating point value out of range"); 4616 return MatchOperand_ParseFail; 4617 } 4618 float RealVal = ARM_AM::getFPImmFloat(Val); 4619 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue(); 4620 4621 Operands.push_back(ARMOperand::CreateImm( 4622 MCConstantExpr::Create(Val, getContext()), S, 4623 Parser.getTok().getLoc())); 4624 return MatchOperand_Success; 4625 } 4626 4627 Error(Loc, "invalid floating point immediate"); 4628 return MatchOperand_ParseFail; 4629} 4630 4631/// Parse a arm instruction operand. For now this parses the operand regardless 4632/// of the mnemonic. 4633bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4634 StringRef Mnemonic) { 4635 SMLoc S, E; 4636 4637 // Check if the current operand has a custom associated parser, if so, try to 4638 // custom parse the operand, or fallback to the general approach. 4639 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4640 if (ResTy == MatchOperand_Success) 4641 return false; 4642 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4643 // there was a match, but an error occurred, in which case, just return that 4644 // the operand parsing failed. 4645 if (ResTy == MatchOperand_ParseFail) 4646 return true; 4647 4648 switch (getLexer().getKind()) { 4649 default: 4650 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4651 return true; 4652 case AsmToken::Identifier: { 4653 // If we've seen a branch mnemonic, the next operand must be a label. This 4654 // is true even if the label is a register name. So "br r1" means branch to 4655 // label "r1". 4656 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; 4657 if (!ExpectLabel) { 4658 if (!tryParseRegisterWithWriteBack(Operands)) 4659 return false; 4660 int Res = tryParseShiftRegister(Operands); 4661 if (Res == 0) // success 4662 return false; 4663 else if (Res == -1) // irrecoverable error 4664 return true; 4665 // If this is VMRS, check for the apsr_nzcv operand. 4666 if (Mnemonic == "vmrs" && 4667 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 4668 S = Parser.getTok().getLoc(); 4669 Parser.Lex(); 4670 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 4671 return false; 4672 } 4673 } 4674 4675 // Fall though for the Identifier case that is not a register or a 4676 // special name. 4677 } 4678 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4679 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4680 case AsmToken::String: // quoted label names. 4681 case AsmToken::Dot: { // . as a branch target 4682 // This was not a register so parse other operands that start with an 4683 // identifier (like labels) as expressions and create them as immediates. 4684 const MCExpr *IdVal; 4685 S = Parser.getTok().getLoc(); 4686 if (getParser().parseExpression(IdVal)) 4687 return true; 4688 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4689 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4690 return false; 4691 } 4692 case AsmToken::LBrac: 4693 return parseMemory(Operands); 4694 case AsmToken::LCurly: 4695 return parseRegisterList(Operands); 4696 case AsmToken::Dollar: 4697 case AsmToken::Hash: { 4698 // #42 -> immediate. 4699 S = Parser.getTok().getLoc(); 4700 Parser.Lex(); 4701 4702 if (Parser.getTok().isNot(AsmToken::Colon)) { 4703 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4704 const MCExpr *ImmVal; 4705 if (getParser().parseExpression(ImmVal)) 4706 return true; 4707 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4708 if (CE) { 4709 int32_t Val = CE->getValue(); 4710 if (isNegative && Val == 0) 4711 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4712 } 4713 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4714 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4715 4716 // There can be a trailing '!' on operands that we want as a separate 4717 // '!' Token operand. Handle that here. For example, the compatibility 4718 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. 4719 if (Parser.getTok().is(AsmToken::Exclaim)) { 4720 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), 4721 Parser.getTok().getLoc())); 4722 Parser.Lex(); // Eat exclaim token 4723 } 4724 return false; 4725 } 4726 // w/ a ':' after the '#', it's just like a plain ':'. 4727 // FALLTHROUGH 4728 } 4729 case AsmToken::Colon: { 4730 // ":lower16:" and ":upper16:" expression prefixes 4731 // FIXME: Check it's an expression prefix, 4732 // e.g. (FOO - :lower16:BAR) isn't legal. 4733 ARMMCExpr::VariantKind RefKind; 4734 if (parsePrefix(RefKind)) 4735 return true; 4736 4737 const MCExpr *SubExprVal; 4738 if (getParser().parseExpression(SubExprVal)) 4739 return true; 4740 4741 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 4742 getContext()); 4743 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4744 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 4745 return false; 4746 } 4747 case AsmToken::Equal: { 4748 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val) 4749 return Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4750 4751 Parser.Lex(); // Eat '=' 4752 const MCExpr *SubExprVal; 4753 if (getParser().parseExpression(SubExprVal)) 4754 return true; 4755 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4756 4757 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal); 4758 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E)); 4759 return false; 4760 } 4761 } 4762} 4763 4764// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 4765// :lower16: and :upper16:. 4766bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 4767 RefKind = ARMMCExpr::VK_ARM_None; 4768 4769 // consume an optional '#' (GNU compatibility) 4770 if (getLexer().is(AsmToken::Hash)) 4771 Parser.Lex(); 4772 4773 // :lower16: and :upper16: modifiers 4774 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 4775 Parser.Lex(); // Eat ':' 4776 4777 if (getLexer().isNot(AsmToken::Identifier)) { 4778 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 4779 return true; 4780 } 4781 4782 StringRef IDVal = Parser.getTok().getIdentifier(); 4783 if (IDVal == "lower16") { 4784 RefKind = ARMMCExpr::VK_ARM_LO16; 4785 } else if (IDVal == "upper16") { 4786 RefKind = ARMMCExpr::VK_ARM_HI16; 4787 } else { 4788 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 4789 return true; 4790 } 4791 Parser.Lex(); 4792 4793 if (getLexer().isNot(AsmToken::Colon)) { 4794 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 4795 return true; 4796 } 4797 Parser.Lex(); // Eat the last ':' 4798 return false; 4799} 4800 4801/// \brief Given a mnemonic, split out possible predication code and carry 4802/// setting letters to form a canonical mnemonic and flags. 4803// 4804// FIXME: Would be nice to autogen this. 4805// FIXME: This is a bit of a maze of special cases. 4806StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 4807 unsigned &PredicationCode, 4808 bool &CarrySetting, 4809 unsigned &ProcessorIMod, 4810 StringRef &ITMask) { 4811 PredicationCode = ARMCC::AL; 4812 CarrySetting = false; 4813 ProcessorIMod = 0; 4814 4815 // Ignore some mnemonics we know aren't predicated forms. 4816 // 4817 // FIXME: Would be nice to autogen this. 4818 if ((Mnemonic == "movs" && isThumb()) || 4819 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 4820 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 4821 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 4822 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 4823 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" || 4824 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 4825 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 4826 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 4827 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || 4828 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || 4829 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" || 4830 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel")) 4831 return Mnemonic; 4832 4833 // First, split out any predication code. Ignore mnemonics we know aren't 4834 // predicated but do have a carry-set and so weren't caught above. 4835 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 4836 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 4837 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 4838 Mnemonic != "sbcs" && Mnemonic != "rscs") { 4839 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 4840 .Case("eq", ARMCC::EQ) 4841 .Case("ne", ARMCC::NE) 4842 .Case("hs", ARMCC::HS) 4843 .Case("cs", ARMCC::HS) 4844 .Case("lo", ARMCC::LO) 4845 .Case("cc", ARMCC::LO) 4846 .Case("mi", ARMCC::MI) 4847 .Case("pl", ARMCC::PL) 4848 .Case("vs", ARMCC::VS) 4849 .Case("vc", ARMCC::VC) 4850 .Case("hi", ARMCC::HI) 4851 .Case("ls", ARMCC::LS) 4852 .Case("ge", ARMCC::GE) 4853 .Case("lt", ARMCC::LT) 4854 .Case("gt", ARMCC::GT) 4855 .Case("le", ARMCC::LE) 4856 .Case("al", ARMCC::AL) 4857 .Default(~0U); 4858 if (CC != ~0U) { 4859 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 4860 PredicationCode = CC; 4861 } 4862 } 4863 4864 // Next, determine if we have a carry setting bit. We explicitly ignore all 4865 // the instructions we know end in 's'. 4866 if (Mnemonic.endswith("s") && 4867 !(Mnemonic == "cps" || Mnemonic == "mls" || 4868 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 4869 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 4870 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 4871 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 4872 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 4873 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 4874 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 4875 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" || 4876 (Mnemonic == "movs" && isThumb()))) { 4877 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4878 CarrySetting = true; 4879 } 4880 4881 // The "cps" instruction can have a interrupt mode operand which is glued into 4882 // the mnemonic. Check if this is the case, split it and parse the imod op 4883 if (Mnemonic.startswith("cps")) { 4884 // Split out any imod code. 4885 unsigned IMod = 4886 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4887 .Case("ie", ARM_PROC::IE) 4888 .Case("id", ARM_PROC::ID) 4889 .Default(~0U); 4890 if (IMod != ~0U) { 4891 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4892 ProcessorIMod = IMod; 4893 } 4894 } 4895 4896 // The "it" instruction has the condition mask on the end of the mnemonic. 4897 if (Mnemonic.startswith("it")) { 4898 ITMask = Mnemonic.slice(2, Mnemonic.size()); 4899 Mnemonic = Mnemonic.slice(0, 2); 4900 } 4901 4902 return Mnemonic; 4903} 4904 4905/// \brief Given a canonical mnemonic, determine if the instruction ever allows 4906/// inclusion of carry set or predication code operands. 4907// 4908// FIXME: It would be nice to autogen this. 4909void ARMAsmParser:: 4910getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 4911 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) { 4912 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4913 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4914 Mnemonic == "add" || Mnemonic == "adc" || 4915 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4916 Mnemonic == "orr" || Mnemonic == "mvn" || 4917 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4918 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4919 Mnemonic == "vfm" || Mnemonic == "vfnm" || 4920 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4921 Mnemonic == "mla" || Mnemonic == "smlal" || 4922 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4923 CanAcceptCarrySet = true; 4924 } else 4925 CanAcceptCarrySet = false; 4926 4927 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || 4928 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || 4929 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") || 4930 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") || 4931 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" || 4932 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || 4933 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" || 4934 Mnemonic == "vrintm" || Mnemonic.startswith("aes") || 4935 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") || 4936 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) { 4937 // These mnemonics are never predicable 4938 CanAcceptPredicationCode = false; 4939 } else if (!isThumb()) { 4940 // Some instructions are only predicable in Thumb mode 4941 CanAcceptPredicationCode 4942 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" && 4943 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" && 4944 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" && 4945 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" && 4946 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && 4947 Mnemonic != "stc2" && Mnemonic != "stc2l" && 4948 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs"); 4949 } else if (isThumbOne()) { 4950 if (hasV6MOps()) 4951 CanAcceptPredicationCode = Mnemonic != "movs"; 4952 else 4953 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs"; 4954 } else 4955 CanAcceptPredicationCode = true; 4956} 4957 4958bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4959 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4960 // FIXME: This is all horribly hacky. We really need a better way to deal 4961 // with optional operands like this in the matcher table. 4962 4963 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4964 // another does not. Specifically, the MOVW instruction does not. So we 4965 // special case it here and remove the defaulted (non-setting) cc_out 4966 // operand if that's the instruction we're trying to match. 4967 // 4968 // We do this as post-processing of the explicit operands rather than just 4969 // conditionally adding the cc_out in the first place because we need 4970 // to check the type of the parsed immediate operand. 4971 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4972 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4973 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4974 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4975 return true; 4976 4977 // Register-register 'add' for thumb does not have a cc_out operand 4978 // when there are only two register operands. 4979 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 4980 static_cast<ARMOperand*>(Operands[3])->isReg() && 4981 static_cast<ARMOperand*>(Operands[4])->isReg() && 4982 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4983 return true; 4984 // Register-register 'add' for thumb does not have a cc_out operand 4985 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 4986 // have to check the immediate range here since Thumb2 has a variant 4987 // that can handle a different range and has a cc_out operand. 4988 if (((isThumb() && Mnemonic == "add") || 4989 (isThumbTwo() && Mnemonic == "sub")) && 4990 Operands.size() == 6 && 4991 static_cast<ARMOperand*>(Operands[3])->isReg() && 4992 static_cast<ARMOperand*>(Operands[4])->isReg() && 4993 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 4994 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4995 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || 4996 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 4997 return true; 4998 // For Thumb2, add/sub immediate does not have a cc_out operand for the 4999 // imm0_4095 variant. That's the least-preferred variant when 5000 // selecting via the generic "add" mnemonic, so to know that we 5001 // should remove the cc_out operand, we have to explicitly check that 5002 // it's not one of the other variants. Ugh. 5003 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 5004 Operands.size() == 6 && 5005 static_cast<ARMOperand*>(Operands[3])->isReg() && 5006 static_cast<ARMOperand*>(Operands[4])->isReg() && 5007 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5008 // Nest conditions rather than one big 'if' statement for readability. 5009 // 5010 // If both registers are low, we're in an IT block, and the immediate is 5011 // in range, we should use encoding T1 instead, which has a cc_out. 5012 if (inITBlock() && 5013 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 5014 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 5015 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 5016 return false; 5017 // Check against T3. If the second register is the PC, this is an 5018 // alternate form of ADR, which uses encoding T4, so check for that too. 5019 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 5020 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 5021 return false; 5022 5023 // Otherwise, we use encoding T4, which does not have a cc_out 5024 // operand. 5025 return true; 5026 } 5027 5028 // The thumb2 multiply instruction doesn't have a CCOut register, so 5029 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 5030 // use the 16-bit encoding or not. 5031 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 5032 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5033 static_cast<ARMOperand*>(Operands[3])->isReg() && 5034 static_cast<ARMOperand*>(Operands[4])->isReg() && 5035 static_cast<ARMOperand*>(Operands[5])->isReg() && 5036 // If the registers aren't low regs, the destination reg isn't the 5037 // same as one of the source regs, or the cc_out operand is zero 5038 // outside of an IT block, we have to use the 32-bit encoding, so 5039 // remove the cc_out operand. 5040 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 5041 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 5042 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 5043 !inITBlock() || 5044 (static_cast<ARMOperand*>(Operands[3])->getReg() != 5045 static_cast<ARMOperand*>(Operands[5])->getReg() && 5046 static_cast<ARMOperand*>(Operands[3])->getReg() != 5047 static_cast<ARMOperand*>(Operands[4])->getReg()))) 5048 return true; 5049 5050 // Also check the 'mul' syntax variant that doesn't specify an explicit 5051 // destination register. 5052 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 5053 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5054 static_cast<ARMOperand*>(Operands[3])->isReg() && 5055 static_cast<ARMOperand*>(Operands[4])->isReg() && 5056 // If the registers aren't low regs or the cc_out operand is zero 5057 // outside of an IT block, we have to use the 32-bit encoding, so 5058 // remove the cc_out operand. 5059 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 5060 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 5061 !inITBlock())) 5062 return true; 5063 5064 5065 5066 // Register-register 'add/sub' for thumb does not have a cc_out operand 5067 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 5068 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 5069 // right, this will result in better diagnostics (which operand is off) 5070 // anyway. 5071 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 5072 (Operands.size() == 5 || Operands.size() == 6) && 5073 static_cast<ARMOperand*>(Operands[3])->isReg() && 5074 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 5075 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5076 (static_cast<ARMOperand*>(Operands[4])->isImm() || 5077 (Operands.size() == 6 && 5078 static_cast<ARMOperand*>(Operands[5])->isImm()))) 5079 return true; 5080 5081 return false; 5082} 5083 5084bool ARMAsmParser::shouldOmitPredicateOperand( 5085 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) { 5086 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON 5087 unsigned RegIdx = 3; 5088 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") && 5089 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") { 5090 if (static_cast<ARMOperand *>(Operands[3])->isToken() && 5091 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32") 5092 RegIdx = 4; 5093 5094 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() && 5095 (ARMMCRegisterClasses[ARM::DPRRegClassID] 5096 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) || 5097 ARMMCRegisterClasses[ARM::QPRRegClassID] 5098 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()))) 5099 return true; 5100 } 5101 return false; 5102} 5103 5104static bool isDataTypeToken(StringRef Tok) { 5105 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 5106 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 5107 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 5108 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 5109 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 5110 Tok == ".f" || Tok == ".d"; 5111} 5112 5113// FIXME: This bit should probably be handled via an explicit match class 5114// in the .td files that matches the suffix instead of having it be 5115// a literal string token the way it is now. 5116static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 5117 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 5118} 5119static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features, 5120 unsigned VariantID); 5121 5122static bool RequiresVFPRegListValidation(StringRef Inst, 5123 bool &AcceptSinglePrecisionOnly, 5124 bool &AcceptDoublePrecisionOnly) { 5125 if (Inst.size() < 7) 5126 return false; 5127 5128 if (Inst.startswith("fldm") || Inst.startswith("fstm")) { 5129 StringRef AddressingMode = Inst.substr(4, 2); 5130 if (AddressingMode == "ia" || AddressingMode == "db" || 5131 AddressingMode == "ea" || AddressingMode == "fd") { 5132 AcceptSinglePrecisionOnly = Inst[6] == 's'; 5133 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x'; 5134 return true; 5135 } 5136 } 5137 5138 return false; 5139} 5140 5141/// Parse an arm instruction mnemonic followed by its operands. 5142bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 5143 SMLoc NameLoc, 5144 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5145 // FIXME: Can this be done via tablegen in some fashion? 5146 bool RequireVFPRegisterListCheck; 5147 bool AcceptSinglePrecisionOnly; 5148 bool AcceptDoublePrecisionOnly; 5149 RequireVFPRegisterListCheck = 5150 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly, 5151 AcceptDoublePrecisionOnly); 5152 5153 // Apply mnemonic aliases before doing anything else, as the destination 5154 // mnemonic may include suffices and we want to handle them normally. 5155 // The generic tblgen'erated code does this later, at the start of 5156 // MatchInstructionImpl(), but that's too late for aliases that include 5157 // any sort of suffix. 5158 unsigned AvailableFeatures = getAvailableFeatures(); 5159 unsigned AssemblerDialect = getParser().getAssemblerDialect(); 5160 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); 5161 5162 // First check for the ARM-specific .req directive. 5163 if (Parser.getTok().is(AsmToken::Identifier) && 5164 Parser.getTok().getIdentifier() == ".req") { 5165 parseDirectiveReq(Name, NameLoc); 5166 // We always return 'error' for this, as we're done with this 5167 // statement and don't need to match the 'instruction." 5168 return true; 5169 } 5170 5171 // Create the leading tokens for the mnemonic, split by '.' characters. 5172 size_t Start = 0, Next = Name.find('.'); 5173 StringRef Mnemonic = Name.slice(Start, Next); 5174 5175 // Split out the predication code and carry setting flag from the mnemonic. 5176 unsigned PredicationCode; 5177 unsigned ProcessorIMod; 5178 bool CarrySetting; 5179 StringRef ITMask; 5180 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 5181 ProcessorIMod, ITMask); 5182 5183 // In Thumb1, only the branch (B) instruction can be predicated. 5184 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 5185 Parser.eatToEndOfStatement(); 5186 return Error(NameLoc, "conditional execution not supported in Thumb1"); 5187 } 5188 5189 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 5190 5191 // Handle the IT instruction ITMask. Convert it to a bitmask. This 5192 // is the mask as it will be for the IT encoding if the conditional 5193 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 5194 // where the conditional bit0 is zero, the instruction post-processing 5195 // will adjust the mask accordingly. 5196 if (Mnemonic == "it") { 5197 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 5198 if (ITMask.size() > 3) { 5199 Parser.eatToEndOfStatement(); 5200 return Error(Loc, "too many conditions on IT instruction"); 5201 } 5202 unsigned Mask = 8; 5203 for (unsigned i = ITMask.size(); i != 0; --i) { 5204 char pos = ITMask[i - 1]; 5205 if (pos != 't' && pos != 'e') { 5206 Parser.eatToEndOfStatement(); 5207 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5208 } 5209 Mask >>= 1; 5210 if (ITMask[i - 1] == 't') 5211 Mask |= 8; 5212 } 5213 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5214 } 5215 5216 // FIXME: This is all a pretty gross hack. We should automatically handle 5217 // optional operands like this via tblgen. 5218 5219 // Next, add the CCOut and ConditionCode operands, if needed. 5220 // 5221 // For mnemonics which can ever incorporate a carry setting bit or predication 5222 // code, our matching model involves us always generating CCOut and 5223 // ConditionCode operands to match the mnemonic "as written" and then we let 5224 // the matcher deal with finding the right instruction or generating an 5225 // appropriate error. 5226 bool CanAcceptCarrySet, CanAcceptPredicationCode; 5227 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode); 5228 5229 // If we had a carry-set on an instruction that can't do that, issue an 5230 // error. 5231 if (!CanAcceptCarrySet && CarrySetting) { 5232 Parser.eatToEndOfStatement(); 5233 return Error(NameLoc, "instruction '" + Mnemonic + 5234 "' can not set flags, but 's' suffix specified"); 5235 } 5236 // If we had a predication code on an instruction that can't do that, issue an 5237 // error. 5238 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5239 Parser.eatToEndOfStatement(); 5240 return Error(NameLoc, "instruction '" + Mnemonic + 5241 "' is not predicable, but condition code specified"); 5242 } 5243 5244 // Add the carry setting operand, if necessary. 5245 if (CanAcceptCarrySet) { 5246 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5247 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5248 Loc)); 5249 } 5250 5251 // Add the predication code operand, if necessary. 5252 if (CanAcceptPredicationCode) { 5253 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5254 CarrySetting); 5255 Operands.push_back(ARMOperand::CreateCondCode( 5256 ARMCC::CondCodes(PredicationCode), Loc)); 5257 } 5258 5259 // Add the processor imod operand, if necessary. 5260 if (ProcessorIMod) { 5261 Operands.push_back(ARMOperand::CreateImm( 5262 MCConstantExpr::Create(ProcessorIMod, getContext()), 5263 NameLoc, NameLoc)); 5264 } 5265 5266 // Add the remaining tokens in the mnemonic. 5267 while (Next != StringRef::npos) { 5268 Start = Next; 5269 Next = Name.find('.', Start + 1); 5270 StringRef ExtraToken = Name.slice(Start, Next); 5271 5272 // Some NEON instructions have an optional datatype suffix that is 5273 // completely ignored. Check for that. 5274 if (isDataTypeToken(ExtraToken) && 5275 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5276 continue; 5277 5278 // For for ARM mode generate an error if the .n qualifier is used. 5279 if (ExtraToken == ".n" && !isThumb()) { 5280 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5281 Parser.eatToEndOfStatement(); 5282 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in " 5283 "arm mode"); 5284 } 5285 5286 // The .n qualifier is always discarded as that is what the tables 5287 // and matcher expect. In ARM mode the .w qualifier has no effect, 5288 // so discard it to avoid errors that can be caused by the matcher. 5289 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) { 5290 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5291 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5292 } 5293 } 5294 5295 // Read the remaining operands. 5296 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5297 // Read the first operand. 5298 if (parseOperand(Operands, Mnemonic)) { 5299 Parser.eatToEndOfStatement(); 5300 return true; 5301 } 5302 5303 while (getLexer().is(AsmToken::Comma)) { 5304 Parser.Lex(); // Eat the comma. 5305 5306 // Parse and remember the operand. 5307 if (parseOperand(Operands, Mnemonic)) { 5308 Parser.eatToEndOfStatement(); 5309 return true; 5310 } 5311 } 5312 } 5313 5314 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5315 SMLoc Loc = getLexer().getLoc(); 5316 Parser.eatToEndOfStatement(); 5317 return Error(Loc, "unexpected token in argument list"); 5318 } 5319 5320 Parser.Lex(); // Consume the EndOfStatement 5321 5322 if (RequireVFPRegisterListCheck) { 5323 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back()); 5324 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList()) 5325 return Error(Op->getStartLoc(), 5326 "VFP/Neon single precision register expected"); 5327 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList()) 5328 return Error(Op->getStartLoc(), 5329 "VFP/Neon double precision register expected"); 5330 } 5331 5332 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5333 // do and don't have a cc_out optional-def operand. With some spot-checks 5334 // of the operand list, we can figure out which variant we're trying to 5335 // parse and adjust accordingly before actually matching. We shouldn't ever 5336 // try to remove a cc_out operand that was explicitly set on the the 5337 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5338 // table driven matcher doesn't fit well with the ARM instruction set. 5339 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 5340 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5341 Operands.erase(Operands.begin() + 1); 5342 delete Op; 5343 } 5344 5345 // Some instructions have the same mnemonic, but don't always 5346 // have a predicate. Distinguish them here and delete the 5347 // predicate if needed. 5348 if (shouldOmitPredicateOperand(Mnemonic, Operands)) { 5349 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5350 Operands.erase(Operands.begin() + 1); 5351 delete Op; 5352 } 5353 5354 // ARM mode 'blx' need special handling, as the register operand version 5355 // is predicable, but the label operand version is not. So, we can't rely 5356 // on the Mnemonic based checking to correctly figure out when to put 5357 // a k_CondCode operand in the list. If we're trying to match the label 5358 // version, remove the k_CondCode operand here. 5359 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5360 static_cast<ARMOperand*>(Operands[2])->isImm()) { 5361 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5362 Operands.erase(Operands.begin() + 1); 5363 delete Op; 5364 } 5365 5366 // Adjust operands of ldrexd/strexd to MCK_GPRPair. 5367 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 5368 // a single GPRPair reg operand is used in the .td file to replace the two 5369 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically 5370 // expressed as a GPRPair, so we have to manually merge them. 5371 // FIXME: We would really like to be able to tablegen'erate this. 5372 if (!isThumb() && Operands.size() > 4 && 5373 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" || 5374 Mnemonic == "stlexd")) { 5375 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd"); 5376 unsigned Idx = isLoad ? 2 : 3; 5377 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]); 5378 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]); 5379 5380 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); 5381 // Adjust only if Op1 and Op2 are GPRs. 5382 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) && 5383 MRC.contains(Op2->getReg())) { 5384 unsigned Reg1 = Op1->getReg(); 5385 unsigned Reg2 = Op2->getReg(); 5386 unsigned Rt = MRI->getEncodingValue(Reg1); 5387 unsigned Rt2 = MRI->getEncodingValue(Reg2); 5388 5389 // Rt2 must be Rt + 1 and Rt must be even. 5390 if (Rt + 1 != Rt2 || (Rt & 1)) { 5391 Error(Op2->getStartLoc(), isLoad ? 5392 "destination operands must be sequential" : 5393 "source operands must be sequential"); 5394 return true; 5395 } 5396 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, 5397 &(MRI->getRegClass(ARM::GPRPairRegClassID))); 5398 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2); 5399 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg( 5400 NewReg, Op1->getStartLoc(), Op2->getEndLoc())); 5401 delete Op1; 5402 delete Op2; 5403 } 5404 } 5405 5406 // GNU Assembler extension (compatibility) 5407 if ((Mnemonic == "ldrd" || Mnemonic == "strd") && !isThumb() && 5408 Operands.size() == 4) { 5409 ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]); 5410 assert(Op->isReg() && "expected register argument"); 5411 5412 unsigned SuperReg = MRI->getMatchingSuperReg( 5413 Op->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID)); 5414 5415 assert(SuperReg && "expected register pair"); 5416 5417 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); 5418 5419 Operands.insert(Operands.begin() + 3, 5420 ARMOperand::CreateReg(PairedReg, Op->getStartLoc(), 5421 Op->getEndLoc())); 5422 } 5423 5424 // FIXME: As said above, this is all a pretty gross hack. This instruction 5425 // does not fit with other "subs" and tblgen. 5426 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction 5427 // so the Mnemonic is the original name "subs" and delete the predicate 5428 // operand so it will match the table entry. 5429 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && 5430 static_cast<ARMOperand*>(Operands[3])->isReg() && 5431 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC && 5432 static_cast<ARMOperand*>(Operands[4])->isReg() && 5433 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR && 5434 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5435 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]); 5436 Operands.erase(Operands.begin()); 5437 delete Op0; 5438 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc)); 5439 5440 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]); 5441 Operands.erase(Operands.begin() + 1); 5442 delete Op1; 5443 } 5444 return false; 5445} 5446 5447// Validate context-sensitive operand constraints. 5448 5449// return 'true' if register list contains non-low GPR registers, 5450// 'false' otherwise. If Reg is in the register list or is HiReg, set 5451// 'containsReg' to true. 5452static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5453 unsigned HiReg, bool &containsReg) { 5454 containsReg = false; 5455 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5456 unsigned OpReg = Inst.getOperand(i).getReg(); 5457 if (OpReg == Reg) 5458 containsReg = true; 5459 // Anything other than a low register isn't legal here. 5460 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5461 return true; 5462 } 5463 return false; 5464} 5465 5466// Check if the specified regisgter is in the register list of the inst, 5467// starting at the indicated operand number. 5468static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 5469 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5470 unsigned OpReg = Inst.getOperand(i).getReg(); 5471 if (OpReg == Reg) 5472 return true; 5473 } 5474 return false; 5475} 5476 5477// Return true if instruction has the interesting property of being 5478// allowed in IT blocks, but not being predicable. 5479static bool instIsBreakpoint(const MCInst &Inst) { 5480 return Inst.getOpcode() == ARM::tBKPT || 5481 Inst.getOpcode() == ARM::BKPT || 5482 Inst.getOpcode() == ARM::tHLT || 5483 Inst.getOpcode() == ARM::HLT; 5484 5485} 5486 5487// FIXME: We would really like to be able to tablegen'erate this. 5488bool ARMAsmParser:: 5489validateInstruction(MCInst &Inst, 5490 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5491 const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); 5492 SMLoc Loc = Operands[0]->getStartLoc(); 5493 5494 // Check the IT block state first. 5495 // NOTE: BKPT and HLT instructions have the interesting property of being 5496 // allowed in IT blocks, but not being predicable. They just always execute. 5497 if (inITBlock() && !instIsBreakpoint(Inst)) { 5498 unsigned Bit = 1; 5499 if (ITState.FirstCond) 5500 ITState.FirstCond = false; 5501 else 5502 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5503 // The instruction must be predicable. 5504 if (!MCID.isPredicable()) 5505 return Error(Loc, "instructions in IT block must be predicable"); 5506 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5507 unsigned ITCond = Bit ? ITState.Cond : 5508 ARMCC::getOppositeCondition(ITState.Cond); 5509 if (Cond != ITCond) { 5510 // Find the condition code Operand to get its SMLoc information. 5511 SMLoc CondLoc; 5512 for (unsigned I = 1; I < Operands.size(); ++I) 5513 if (static_cast<ARMOperand*>(Operands[I])->isCondCode()) 5514 CondLoc = Operands[I]->getStartLoc(); 5515 return Error(CondLoc, "incorrect condition in IT block; got '" + 5516 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5517 "', but expected '" + 5518 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5519 } 5520 // Check for non-'al' condition codes outside of the IT block. 5521 } else if (isThumbTwo() && MCID.isPredicable() && 5522 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 5523 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && 5524 Inst.getOpcode() != ARM::t2Bcc) 5525 return Error(Loc, "predicated instructions must be in IT block"); 5526 5527 const unsigned Opcode = Inst.getOpcode(); 5528 switch (Opcode) { 5529 case ARM::LDRD: 5530 case ARM::LDRD_PRE: 5531 case ARM::LDRD_POST: { 5532 const unsigned RtReg = Inst.getOperand(0).getReg(); 5533 5534 // Rt can't be R14. 5535 if (RtReg == ARM::LR) 5536 return Error(Operands[3]->getStartLoc(), 5537 "Rt can't be R14"); 5538 5539 const unsigned Rt = MRI->getEncodingValue(RtReg); 5540 // Rt must be even-numbered. 5541 if ((Rt & 1) == 1) 5542 return Error(Operands[3]->getStartLoc(), 5543 "Rt must be even-numbered"); 5544 5545 // Rt2 must be Rt + 1. 5546 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5547 if (Rt2 != Rt + 1) 5548 return Error(Operands[3]->getStartLoc(), 5549 "destination operands must be sequential"); 5550 5551 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) { 5552 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); 5553 // For addressing modes with writeback, the base register needs to be 5554 // different from the destination registers. 5555 if (Rn == Rt || Rn == Rt2) 5556 return Error(Operands[3]->getStartLoc(), 5557 "base register needs to be different from destination " 5558 "registers"); 5559 } 5560 5561 return false; 5562 } 5563 case ARM::t2LDRDi8: 5564 case ARM::t2LDRD_PRE: 5565 case ARM::t2LDRD_POST: { 5566 // Rt2 must be different from Rt. 5567 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5568 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5569 if (Rt2 == Rt) 5570 return Error(Operands[3]->getStartLoc(), 5571 "destination operands can't be identical"); 5572 return false; 5573 } 5574 case ARM::STRD: { 5575 // Rt2 must be Rt + 1. 5576 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5577 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5578 if (Rt2 != Rt + 1) 5579 return Error(Operands[3]->getStartLoc(), 5580 "source operands must be sequential"); 5581 return false; 5582 } 5583 case ARM::STRD_PRE: 5584 case ARM::STRD_POST: { 5585 // Rt2 must be Rt + 1. 5586 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5587 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 5588 if (Rt2 != Rt + 1) 5589 return Error(Operands[3]->getStartLoc(), 5590 "source operands must be sequential"); 5591 return false; 5592 } 5593 case ARM::SBFX: 5594 case ARM::UBFX: { 5595 // Width must be in range [1, 32-lsb]. 5596 unsigned LSB = Inst.getOperand(2).getImm(); 5597 unsigned Widthm1 = Inst.getOperand(3).getImm(); 5598 if (Widthm1 >= 32 - LSB) 5599 return Error(Operands[5]->getStartLoc(), 5600 "bitfield width must be in range [1,32-lsb]"); 5601 return false; 5602 } 5603 // Notionally handles ARM::tLDMIA_UPD too. 5604 case ARM::tLDMIA: { 5605 // If we're parsing Thumb2, the .w variant is available and handles 5606 // most cases that are normally illegal for a Thumb1 LDM instruction. 5607 // We'll make the transformation in processInstruction() if necessary. 5608 // 5609 // Thumb LDM instructions are writeback iff the base register is not 5610 // in the register list. 5611 unsigned Rn = Inst.getOperand(0).getReg(); 5612 bool HasWritebackToken = 5613 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5614 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5615 bool ListContainsBase; 5616 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo()) 5617 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), 5618 "registers must be in range r0-r7"); 5619 // If we should have writeback, then there should be a '!' token. 5620 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo()) 5621 return Error(Operands[2]->getStartLoc(), 5622 "writeback operator '!' expected"); 5623 // If we should not have writeback, there must not be a '!'. This is 5624 // true even for the 32-bit wide encodings. 5625 if (ListContainsBase && HasWritebackToken) 5626 return Error(Operands[3]->getStartLoc(), 5627 "writeback operator '!' not allowed when base register " 5628 "in register list"); 5629 5630 break; 5631 } 5632 case ARM::LDMIA_UPD: 5633 case ARM::LDMDB_UPD: 5634 case ARM::LDMIB_UPD: 5635 case ARM::LDMDA_UPD: 5636 // ARM variants loading and updating the same register are only officially 5637 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before. 5638 if (!hasV7Ops()) 5639 break; 5640 // Fallthrough 5641 case ARM::t2LDMIA_UPD: 5642 case ARM::t2LDMDB_UPD: 5643 case ARM::t2STMIA_UPD: 5644 case ARM::t2STMDB_UPD: { 5645 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 5646 return Error(Operands.back()->getStartLoc(), 5647 "writeback register not allowed in register list"); 5648 break; 5649 } 5650 case ARM::sysLDMIA_UPD: 5651 case ARM::sysLDMDA_UPD: 5652 case ARM::sysLDMDB_UPD: 5653 case ARM::sysLDMIB_UPD: 5654 if (!listContainsReg(Inst, 3, ARM::PC)) 5655 return Error(Operands[4]->getStartLoc(), 5656 "writeback register only allowed on system LDM " 5657 "if PC in register-list"); 5658 break; 5659 case ARM::sysSTMIA_UPD: 5660 case ARM::sysSTMDA_UPD: 5661 case ARM::sysSTMDB_UPD: 5662 case ARM::sysSTMIB_UPD: 5663 return Error(Operands[2]->getStartLoc(), 5664 "system STM cannot have writeback register"); 5665 case ARM::tMUL: { 5666 // The second source operand must be the same register as the destination 5667 // operand. 5668 // 5669 // In this case, we must directly check the parsed operands because the 5670 // cvtThumbMultiply() function is written in such a way that it guarantees 5671 // this first statement is always true for the new Inst. Essentially, the 5672 // destination is unconditionally copied into the second source operand 5673 // without checking to see if it matches what we actually parsed. 5674 if (Operands.size() == 6 && 5675 (((ARMOperand*)Operands[3])->getReg() != 5676 ((ARMOperand*)Operands[5])->getReg()) && 5677 (((ARMOperand*)Operands[3])->getReg() != 5678 ((ARMOperand*)Operands[4])->getReg())) { 5679 return Error(Operands[3]->getStartLoc(), 5680 "destination register must match source register"); 5681 } 5682 break; 5683 } 5684 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 5685 // so only issue a diagnostic for thumb1. The instructions will be 5686 // switched to the t2 encodings in processInstruction() if necessary. 5687 case ARM::tPOP: { 5688 bool ListContainsBase; 5689 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && 5690 !isThumbTwo()) 5691 return Error(Operands[2]->getStartLoc(), 5692 "registers must be in range r0-r7 or pc"); 5693 break; 5694 } 5695 case ARM::tPUSH: { 5696 bool ListContainsBase; 5697 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && 5698 !isThumbTwo()) 5699 return Error(Operands[2]->getStartLoc(), 5700 "registers must be in range r0-r7 or lr"); 5701 break; 5702 } 5703 case ARM::tSTMIA_UPD: { 5704 bool ListContainsBase, InvalidLowList; 5705 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(), 5706 0, ListContainsBase); 5707 if (InvalidLowList && !isThumbTwo()) 5708 return Error(Operands[4]->getStartLoc(), 5709 "registers must be in range r0-r7"); 5710 5711 // This would be converted to a 32-bit stm, but that's not valid if the 5712 // writeback register is in the list. 5713 if (InvalidLowList && ListContainsBase) 5714 return Error(Operands[4]->getStartLoc(), 5715 "writeback operator '!' not allowed when base register " 5716 "in register list"); 5717 break; 5718 } 5719 case ARM::tADDrSP: { 5720 // If the non-SP source operand and the destination operand are not the 5721 // same, we need thumb2 (for the wide encoding), or we have an error. 5722 if (!isThumbTwo() && 5723 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 5724 return Error(Operands[4]->getStartLoc(), 5725 "source register must be the same as destination"); 5726 } 5727 break; 5728 } 5729 // Final range checking for Thumb unconditional branch instructions. 5730 case ARM::tB: 5731 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>()) 5732 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 5733 break; 5734 case ARM::t2B: { 5735 int op = (Operands[2]->isImm()) ? 2 : 3; 5736 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>()) 5737 return Error(Operands[op]->getStartLoc(), "branch target out of range"); 5738 break; 5739 } 5740 // Final range checking for Thumb conditional branch instructions. 5741 case ARM::tBcc: 5742 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>()) 5743 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 5744 break; 5745 case ARM::t2Bcc: { 5746 int Op = (Operands[2]->isImm()) ? 2 : 3; 5747 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>()) 5748 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); 5749 break; 5750 } 5751 } 5752 5753 return false; 5754} 5755 5756static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 5757 switch(Opc) { 5758 default: llvm_unreachable("unexpected opcode!"); 5759 // VST1LN 5760 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5761 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5762 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5763 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5764 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5765 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5766 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 5767 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 5768 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 5769 5770 // VST2LN 5771 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5772 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5773 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5774 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5775 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5776 5777 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5778 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5779 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5780 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5781 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5782 5783 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 5784 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 5785 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 5786 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 5787 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 5788 5789 // VST3LN 5790 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5791 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5792 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5793 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 5794 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5795 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5796 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5797 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5798 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 5799 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5800 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 5801 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 5802 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 5803 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 5804 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 5805 5806 // VST3 5807 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5808 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5809 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5810 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5811 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5812 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5813 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5814 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5815 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5816 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5817 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5818 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5819 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 5820 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 5821 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 5822 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 5823 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 5824 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 5825 5826 // VST4LN 5827 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5828 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5829 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5830 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 5831 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5832 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5833 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5834 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5835 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 5836 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5837 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 5838 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 5839 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 5840 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 5841 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 5842 5843 // VST4 5844 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5845 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5846 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5847 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5848 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5849 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5850 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5851 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5852 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5853 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5854 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5855 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5856 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 5857 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 5858 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 5859 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 5860 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 5861 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 5862 } 5863} 5864 5865static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 5866 switch(Opc) { 5867 default: llvm_unreachable("unexpected opcode!"); 5868 // VLD1LN 5869 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5870 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5871 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5872 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5873 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5874 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5875 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 5876 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 5877 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 5878 5879 // VLD2LN 5880 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5881 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5882 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5883 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 5884 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5885 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5886 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5887 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5888 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 5889 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5890 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 5891 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 5892 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 5893 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 5894 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 5895 5896 // VLD3DUP 5897 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5898 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5899 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5900 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 5901 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD; 5902 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5903 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5904 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5905 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5906 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 5907 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 5908 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5909 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 5910 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 5911 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 5912 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 5913 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 5914 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 5915 5916 // VLD3LN 5917 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5918 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5919 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5920 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 5921 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5922 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5923 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5924 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5925 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 5926 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5927 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 5928 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 5929 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 5930 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 5931 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 5932 5933 // VLD3 5934 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5935 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5936 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5937 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5938 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5939 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5940 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5941 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5942 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5943 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5944 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5945 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5946 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 5947 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 5948 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 5949 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 5950 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 5951 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 5952 5953 // VLD4LN 5954 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5955 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5956 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5957 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5958 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5959 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5960 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5961 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5962 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5963 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5964 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 5965 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 5966 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 5967 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 5968 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 5969 5970 // VLD4DUP 5971 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5972 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5973 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5974 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 5975 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 5976 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5977 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5978 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5979 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5980 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 5981 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 5982 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5983 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 5984 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 5985 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 5986 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 5987 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 5988 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 5989 5990 // VLD4 5991 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5992 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5993 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5994 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5995 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5996 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5997 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5998 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5999 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 6000 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 6001 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 6002 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 6003 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 6004 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 6005 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 6006 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 6007 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 6008 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 6009 } 6010} 6011 6012bool ARMAsmParser:: 6013processInstruction(MCInst &Inst, 6014 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 6015 switch (Inst.getOpcode()) { 6016 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction. 6017 case ARM::LDRT_POST: 6018 case ARM::LDRBT_POST: { 6019 const unsigned Opcode = 6020 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM 6021 : ARM::LDRBT_POST_IMM; 6022 MCInst TmpInst; 6023 TmpInst.setOpcode(Opcode); 6024 TmpInst.addOperand(Inst.getOperand(0)); 6025 TmpInst.addOperand(Inst.getOperand(1)); 6026 TmpInst.addOperand(Inst.getOperand(1)); 6027 TmpInst.addOperand(MCOperand::CreateReg(0)); 6028 TmpInst.addOperand(MCOperand::CreateImm(0)); 6029 TmpInst.addOperand(Inst.getOperand(2)); 6030 TmpInst.addOperand(Inst.getOperand(3)); 6031 Inst = TmpInst; 6032 return true; 6033 } 6034 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction. 6035 case ARM::STRT_POST: 6036 case ARM::STRBT_POST: { 6037 const unsigned Opcode = 6038 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM 6039 : ARM::STRBT_POST_IMM; 6040 MCInst TmpInst; 6041 TmpInst.setOpcode(Opcode); 6042 TmpInst.addOperand(Inst.getOperand(1)); 6043 TmpInst.addOperand(Inst.getOperand(0)); 6044 TmpInst.addOperand(Inst.getOperand(1)); 6045 TmpInst.addOperand(MCOperand::CreateReg(0)); 6046 TmpInst.addOperand(MCOperand::CreateImm(0)); 6047 TmpInst.addOperand(Inst.getOperand(2)); 6048 TmpInst.addOperand(Inst.getOperand(3)); 6049 Inst = TmpInst; 6050 return true; 6051 } 6052 // Alias for alternate form of 'ADR Rd, #imm' instruction. 6053 case ARM::ADDri: { 6054 if (Inst.getOperand(1).getReg() != ARM::PC || 6055 Inst.getOperand(5).getReg() != 0) 6056 return false; 6057 MCInst TmpInst; 6058 TmpInst.setOpcode(ARM::ADR); 6059 TmpInst.addOperand(Inst.getOperand(0)); 6060 TmpInst.addOperand(Inst.getOperand(2)); 6061 TmpInst.addOperand(Inst.getOperand(3)); 6062 TmpInst.addOperand(Inst.getOperand(4)); 6063 Inst = TmpInst; 6064 return true; 6065 } 6066 // Aliases for alternate PC+imm syntax of LDR instructions. 6067 case ARM::t2LDRpcrel: 6068 // Select the narrow version if the immediate will fit. 6069 if (Inst.getOperand(1).getImm() > 0 && 6070 Inst.getOperand(1).getImm() <= 0xff && 6071 !(static_cast<ARMOperand*>(Operands[2])->isToken() && 6072 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w")) 6073 Inst.setOpcode(ARM::tLDRpci); 6074 else 6075 Inst.setOpcode(ARM::t2LDRpci); 6076 return true; 6077 case ARM::t2LDRBpcrel: 6078 Inst.setOpcode(ARM::t2LDRBpci); 6079 return true; 6080 case ARM::t2LDRHpcrel: 6081 Inst.setOpcode(ARM::t2LDRHpci); 6082 return true; 6083 case ARM::t2LDRSBpcrel: 6084 Inst.setOpcode(ARM::t2LDRSBpci); 6085 return true; 6086 case ARM::t2LDRSHpcrel: 6087 Inst.setOpcode(ARM::t2LDRSHpci); 6088 return true; 6089 // Handle NEON VST complex aliases. 6090 case ARM::VST1LNdWB_register_Asm_8: 6091 case ARM::VST1LNdWB_register_Asm_16: 6092 case ARM::VST1LNdWB_register_Asm_32: { 6093 MCInst TmpInst; 6094 // Shuffle the operands around so the lane index operand is in the 6095 // right place. 6096 unsigned Spacing; 6097 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6098 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6099 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6100 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6101 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6102 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6103 TmpInst.addOperand(Inst.getOperand(1)); // lane 6104 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6105 TmpInst.addOperand(Inst.getOperand(6)); 6106 Inst = TmpInst; 6107 return true; 6108 } 6109 6110 case ARM::VST2LNdWB_register_Asm_8: 6111 case ARM::VST2LNdWB_register_Asm_16: 6112 case ARM::VST2LNdWB_register_Asm_32: 6113 case ARM::VST2LNqWB_register_Asm_16: 6114 case ARM::VST2LNqWB_register_Asm_32: { 6115 MCInst TmpInst; 6116 // Shuffle the operands around so the lane index operand is in the 6117 // right place. 6118 unsigned Spacing; 6119 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6120 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6121 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6122 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6123 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6124 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6125 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6126 Spacing)); 6127 TmpInst.addOperand(Inst.getOperand(1)); // lane 6128 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6129 TmpInst.addOperand(Inst.getOperand(6)); 6130 Inst = TmpInst; 6131 return true; 6132 } 6133 6134 case ARM::VST3LNdWB_register_Asm_8: 6135 case ARM::VST3LNdWB_register_Asm_16: 6136 case ARM::VST3LNdWB_register_Asm_32: 6137 case ARM::VST3LNqWB_register_Asm_16: 6138 case ARM::VST3LNqWB_register_Asm_32: { 6139 MCInst TmpInst; 6140 // Shuffle the operands around so the lane index operand is in the 6141 // right place. 6142 unsigned Spacing; 6143 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6144 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6145 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6146 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6147 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6148 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6149 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6150 Spacing)); 6151 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6152 Spacing * 2)); 6153 TmpInst.addOperand(Inst.getOperand(1)); // lane 6154 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6155 TmpInst.addOperand(Inst.getOperand(6)); 6156 Inst = TmpInst; 6157 return true; 6158 } 6159 6160 case ARM::VST4LNdWB_register_Asm_8: 6161 case ARM::VST4LNdWB_register_Asm_16: 6162 case ARM::VST4LNdWB_register_Asm_32: 6163 case ARM::VST4LNqWB_register_Asm_16: 6164 case ARM::VST4LNqWB_register_Asm_32: { 6165 MCInst TmpInst; 6166 // Shuffle the operands around so the lane index operand is in the 6167 // right place. 6168 unsigned Spacing; 6169 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6170 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6171 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6172 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6173 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6174 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6175 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6176 Spacing)); 6177 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6178 Spacing * 2)); 6179 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6180 Spacing * 3)); 6181 TmpInst.addOperand(Inst.getOperand(1)); // lane 6182 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6183 TmpInst.addOperand(Inst.getOperand(6)); 6184 Inst = TmpInst; 6185 return true; 6186 } 6187 6188 case ARM::VST1LNdWB_fixed_Asm_8: 6189 case ARM::VST1LNdWB_fixed_Asm_16: 6190 case ARM::VST1LNdWB_fixed_Asm_32: { 6191 MCInst TmpInst; 6192 // Shuffle the operands around so the lane index operand is in the 6193 // right place. 6194 unsigned Spacing; 6195 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6196 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6197 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6198 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6199 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6200 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6201 TmpInst.addOperand(Inst.getOperand(1)); // lane 6202 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6203 TmpInst.addOperand(Inst.getOperand(5)); 6204 Inst = TmpInst; 6205 return true; 6206 } 6207 6208 case ARM::VST2LNdWB_fixed_Asm_8: 6209 case ARM::VST2LNdWB_fixed_Asm_16: 6210 case ARM::VST2LNdWB_fixed_Asm_32: 6211 case ARM::VST2LNqWB_fixed_Asm_16: 6212 case ARM::VST2LNqWB_fixed_Asm_32: { 6213 MCInst TmpInst; 6214 // Shuffle the operands around so the lane index operand is in the 6215 // right place. 6216 unsigned Spacing; 6217 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6218 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6219 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6220 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6221 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6222 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6223 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6224 Spacing)); 6225 TmpInst.addOperand(Inst.getOperand(1)); // lane 6226 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6227 TmpInst.addOperand(Inst.getOperand(5)); 6228 Inst = TmpInst; 6229 return true; 6230 } 6231 6232 case ARM::VST3LNdWB_fixed_Asm_8: 6233 case ARM::VST3LNdWB_fixed_Asm_16: 6234 case ARM::VST3LNdWB_fixed_Asm_32: 6235 case ARM::VST3LNqWB_fixed_Asm_16: 6236 case ARM::VST3LNqWB_fixed_Asm_32: { 6237 MCInst TmpInst; 6238 // Shuffle the operands around so the lane index operand is in the 6239 // right place. 6240 unsigned Spacing; 6241 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6242 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6243 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6244 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6245 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6246 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6247 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6248 Spacing)); 6249 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6250 Spacing * 2)); 6251 TmpInst.addOperand(Inst.getOperand(1)); // lane 6252 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6253 TmpInst.addOperand(Inst.getOperand(5)); 6254 Inst = TmpInst; 6255 return true; 6256 } 6257 6258 case ARM::VST4LNdWB_fixed_Asm_8: 6259 case ARM::VST4LNdWB_fixed_Asm_16: 6260 case ARM::VST4LNdWB_fixed_Asm_32: 6261 case ARM::VST4LNqWB_fixed_Asm_16: 6262 case ARM::VST4LNqWB_fixed_Asm_32: { 6263 MCInst TmpInst; 6264 // Shuffle the operands around so the lane index operand is in the 6265 // right place. 6266 unsigned Spacing; 6267 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6268 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6269 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6270 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6271 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6272 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6273 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6274 Spacing)); 6275 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6276 Spacing * 2)); 6277 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6278 Spacing * 3)); 6279 TmpInst.addOperand(Inst.getOperand(1)); // lane 6280 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6281 TmpInst.addOperand(Inst.getOperand(5)); 6282 Inst = TmpInst; 6283 return true; 6284 } 6285 6286 case ARM::VST1LNdAsm_8: 6287 case ARM::VST1LNdAsm_16: 6288 case ARM::VST1LNdAsm_32: { 6289 MCInst TmpInst; 6290 // Shuffle the operands around so the lane index operand is in the 6291 // right place. 6292 unsigned Spacing; 6293 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6294 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6295 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6296 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6297 TmpInst.addOperand(Inst.getOperand(1)); // lane 6298 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6299 TmpInst.addOperand(Inst.getOperand(5)); 6300 Inst = TmpInst; 6301 return true; 6302 } 6303 6304 case ARM::VST2LNdAsm_8: 6305 case ARM::VST2LNdAsm_16: 6306 case ARM::VST2LNdAsm_32: 6307 case ARM::VST2LNqAsm_16: 6308 case ARM::VST2LNqAsm_32: { 6309 MCInst TmpInst; 6310 // Shuffle the operands around so the lane index operand is in the 6311 // right place. 6312 unsigned Spacing; 6313 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6314 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6315 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6316 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6317 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6318 Spacing)); 6319 TmpInst.addOperand(Inst.getOperand(1)); // lane 6320 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6321 TmpInst.addOperand(Inst.getOperand(5)); 6322 Inst = TmpInst; 6323 return true; 6324 } 6325 6326 case ARM::VST3LNdAsm_8: 6327 case ARM::VST3LNdAsm_16: 6328 case ARM::VST3LNdAsm_32: 6329 case ARM::VST3LNqAsm_16: 6330 case ARM::VST3LNqAsm_32: { 6331 MCInst TmpInst; 6332 // Shuffle the operands around so the lane index operand is in the 6333 // right place. 6334 unsigned Spacing; 6335 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6336 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6337 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6338 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6339 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6340 Spacing)); 6341 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6342 Spacing * 2)); 6343 TmpInst.addOperand(Inst.getOperand(1)); // lane 6344 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6345 TmpInst.addOperand(Inst.getOperand(5)); 6346 Inst = TmpInst; 6347 return true; 6348 } 6349 6350 case ARM::VST4LNdAsm_8: 6351 case ARM::VST4LNdAsm_16: 6352 case ARM::VST4LNdAsm_32: 6353 case ARM::VST4LNqAsm_16: 6354 case ARM::VST4LNqAsm_32: { 6355 MCInst TmpInst; 6356 // Shuffle the operands around so the lane index operand is in the 6357 // right place. 6358 unsigned Spacing; 6359 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6360 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6361 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6362 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6363 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6364 Spacing)); 6365 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6366 Spacing * 2)); 6367 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6368 Spacing * 3)); 6369 TmpInst.addOperand(Inst.getOperand(1)); // lane 6370 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6371 TmpInst.addOperand(Inst.getOperand(5)); 6372 Inst = TmpInst; 6373 return true; 6374 } 6375 6376 // Handle NEON VLD complex aliases. 6377 case ARM::VLD1LNdWB_register_Asm_8: 6378 case ARM::VLD1LNdWB_register_Asm_16: 6379 case ARM::VLD1LNdWB_register_Asm_32: { 6380 MCInst TmpInst; 6381 // Shuffle the operands around so the lane index operand is in the 6382 // right place. 6383 unsigned Spacing; 6384 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6385 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6386 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6387 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6388 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6389 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6390 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6391 TmpInst.addOperand(Inst.getOperand(1)); // lane 6392 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6393 TmpInst.addOperand(Inst.getOperand(6)); 6394 Inst = TmpInst; 6395 return true; 6396 } 6397 6398 case ARM::VLD2LNdWB_register_Asm_8: 6399 case ARM::VLD2LNdWB_register_Asm_16: 6400 case ARM::VLD2LNdWB_register_Asm_32: 6401 case ARM::VLD2LNqWB_register_Asm_16: 6402 case ARM::VLD2LNqWB_register_Asm_32: { 6403 MCInst TmpInst; 6404 // Shuffle the operands around so the lane index operand is in the 6405 // right place. 6406 unsigned Spacing; 6407 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6408 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6409 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6410 Spacing)); 6411 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6412 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6413 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6414 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6415 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6416 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6417 Spacing)); 6418 TmpInst.addOperand(Inst.getOperand(1)); // lane 6419 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6420 TmpInst.addOperand(Inst.getOperand(6)); 6421 Inst = TmpInst; 6422 return true; 6423 } 6424 6425 case ARM::VLD3LNdWB_register_Asm_8: 6426 case ARM::VLD3LNdWB_register_Asm_16: 6427 case ARM::VLD3LNdWB_register_Asm_32: 6428 case ARM::VLD3LNqWB_register_Asm_16: 6429 case ARM::VLD3LNqWB_register_Asm_32: { 6430 MCInst TmpInst; 6431 // Shuffle the operands around so the lane index operand is in the 6432 // right place. 6433 unsigned Spacing; 6434 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6435 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6436 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6437 Spacing)); 6438 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6439 Spacing * 2)); 6440 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6441 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6442 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6443 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6444 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6445 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6446 Spacing)); 6447 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6448 Spacing * 2)); 6449 TmpInst.addOperand(Inst.getOperand(1)); // lane 6450 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6451 TmpInst.addOperand(Inst.getOperand(6)); 6452 Inst = TmpInst; 6453 return true; 6454 } 6455 6456 case ARM::VLD4LNdWB_register_Asm_8: 6457 case ARM::VLD4LNdWB_register_Asm_16: 6458 case ARM::VLD4LNdWB_register_Asm_32: 6459 case ARM::VLD4LNqWB_register_Asm_16: 6460 case ARM::VLD4LNqWB_register_Asm_32: { 6461 MCInst TmpInst; 6462 // Shuffle the operands around so the lane index operand is in the 6463 // right place. 6464 unsigned Spacing; 6465 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6466 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6467 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6468 Spacing)); 6469 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6470 Spacing * 2)); 6471 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6472 Spacing * 3)); 6473 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6474 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6475 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6476 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6477 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6478 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6479 Spacing)); 6480 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6481 Spacing * 2)); 6482 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6483 Spacing * 3)); 6484 TmpInst.addOperand(Inst.getOperand(1)); // lane 6485 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6486 TmpInst.addOperand(Inst.getOperand(6)); 6487 Inst = TmpInst; 6488 return true; 6489 } 6490 6491 case ARM::VLD1LNdWB_fixed_Asm_8: 6492 case ARM::VLD1LNdWB_fixed_Asm_16: 6493 case ARM::VLD1LNdWB_fixed_Asm_32: { 6494 MCInst TmpInst; 6495 // Shuffle the operands around so the lane index operand is in the 6496 // right place. 6497 unsigned Spacing; 6498 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6499 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6500 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6501 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6502 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6503 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6504 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6505 TmpInst.addOperand(Inst.getOperand(1)); // lane 6506 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6507 TmpInst.addOperand(Inst.getOperand(5)); 6508 Inst = TmpInst; 6509 return true; 6510 } 6511 6512 case ARM::VLD2LNdWB_fixed_Asm_8: 6513 case ARM::VLD2LNdWB_fixed_Asm_16: 6514 case ARM::VLD2LNdWB_fixed_Asm_32: 6515 case ARM::VLD2LNqWB_fixed_Asm_16: 6516 case ARM::VLD2LNqWB_fixed_Asm_32: { 6517 MCInst TmpInst; 6518 // Shuffle the operands around so the lane index operand is in the 6519 // right place. 6520 unsigned Spacing; 6521 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6522 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6523 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6524 Spacing)); 6525 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6526 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6527 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6528 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6529 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6530 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6531 Spacing)); 6532 TmpInst.addOperand(Inst.getOperand(1)); // lane 6533 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6534 TmpInst.addOperand(Inst.getOperand(5)); 6535 Inst = TmpInst; 6536 return true; 6537 } 6538 6539 case ARM::VLD3LNdWB_fixed_Asm_8: 6540 case ARM::VLD3LNdWB_fixed_Asm_16: 6541 case ARM::VLD3LNdWB_fixed_Asm_32: 6542 case ARM::VLD3LNqWB_fixed_Asm_16: 6543 case ARM::VLD3LNqWB_fixed_Asm_32: { 6544 MCInst TmpInst; 6545 // Shuffle the operands around so the lane index operand is in the 6546 // right place. 6547 unsigned Spacing; 6548 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6549 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6550 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6551 Spacing)); 6552 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6553 Spacing * 2)); 6554 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6555 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6556 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6557 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6558 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6559 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6560 Spacing)); 6561 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6562 Spacing * 2)); 6563 TmpInst.addOperand(Inst.getOperand(1)); // lane 6564 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6565 TmpInst.addOperand(Inst.getOperand(5)); 6566 Inst = TmpInst; 6567 return true; 6568 } 6569 6570 case ARM::VLD4LNdWB_fixed_Asm_8: 6571 case ARM::VLD4LNdWB_fixed_Asm_16: 6572 case ARM::VLD4LNdWB_fixed_Asm_32: 6573 case ARM::VLD4LNqWB_fixed_Asm_16: 6574 case ARM::VLD4LNqWB_fixed_Asm_32: { 6575 MCInst TmpInst; 6576 // Shuffle the operands around so the lane index operand is in the 6577 // right place. 6578 unsigned Spacing; 6579 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6580 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6581 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6582 Spacing)); 6583 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6584 Spacing * 2)); 6585 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6586 Spacing * 3)); 6587 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6588 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6589 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6590 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6591 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6592 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6593 Spacing)); 6594 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6595 Spacing * 2)); 6596 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6597 Spacing * 3)); 6598 TmpInst.addOperand(Inst.getOperand(1)); // lane 6599 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6600 TmpInst.addOperand(Inst.getOperand(5)); 6601 Inst = TmpInst; 6602 return true; 6603 } 6604 6605 case ARM::VLD1LNdAsm_8: 6606 case ARM::VLD1LNdAsm_16: 6607 case ARM::VLD1LNdAsm_32: { 6608 MCInst TmpInst; 6609 // Shuffle the operands around so the lane index operand is in the 6610 // right place. 6611 unsigned Spacing; 6612 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6613 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6614 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6615 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6616 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6617 TmpInst.addOperand(Inst.getOperand(1)); // lane 6618 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6619 TmpInst.addOperand(Inst.getOperand(5)); 6620 Inst = TmpInst; 6621 return true; 6622 } 6623 6624 case ARM::VLD2LNdAsm_8: 6625 case ARM::VLD2LNdAsm_16: 6626 case ARM::VLD2LNdAsm_32: 6627 case ARM::VLD2LNqAsm_16: 6628 case ARM::VLD2LNqAsm_32: { 6629 MCInst TmpInst; 6630 // Shuffle the operands around so the lane index operand is in the 6631 // right place. 6632 unsigned Spacing; 6633 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6634 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6635 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6636 Spacing)); 6637 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6638 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6639 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6640 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6641 Spacing)); 6642 TmpInst.addOperand(Inst.getOperand(1)); // lane 6643 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6644 TmpInst.addOperand(Inst.getOperand(5)); 6645 Inst = TmpInst; 6646 return true; 6647 } 6648 6649 case ARM::VLD3LNdAsm_8: 6650 case ARM::VLD3LNdAsm_16: 6651 case ARM::VLD3LNdAsm_32: 6652 case ARM::VLD3LNqAsm_16: 6653 case ARM::VLD3LNqAsm_32: { 6654 MCInst TmpInst; 6655 // Shuffle the operands around so the lane index operand is in the 6656 // right place. 6657 unsigned Spacing; 6658 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6659 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6660 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6661 Spacing)); 6662 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6663 Spacing * 2)); 6664 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6665 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6666 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6667 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6668 Spacing)); 6669 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6670 Spacing * 2)); 6671 TmpInst.addOperand(Inst.getOperand(1)); // lane 6672 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6673 TmpInst.addOperand(Inst.getOperand(5)); 6674 Inst = TmpInst; 6675 return true; 6676 } 6677 6678 case ARM::VLD4LNdAsm_8: 6679 case ARM::VLD4LNdAsm_16: 6680 case ARM::VLD4LNdAsm_32: 6681 case ARM::VLD4LNqAsm_16: 6682 case ARM::VLD4LNqAsm_32: { 6683 MCInst TmpInst; 6684 // Shuffle the operands around so the lane index operand is in the 6685 // right place. 6686 unsigned Spacing; 6687 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6688 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6689 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6690 Spacing)); 6691 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6692 Spacing * 2)); 6693 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6694 Spacing * 3)); 6695 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6696 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6697 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6698 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6699 Spacing)); 6700 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6701 Spacing * 2)); 6702 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6703 Spacing * 3)); 6704 TmpInst.addOperand(Inst.getOperand(1)); // lane 6705 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6706 TmpInst.addOperand(Inst.getOperand(5)); 6707 Inst = TmpInst; 6708 return true; 6709 } 6710 6711 // VLD3DUP single 3-element structure to all lanes instructions. 6712 case ARM::VLD3DUPdAsm_8: 6713 case ARM::VLD3DUPdAsm_16: 6714 case ARM::VLD3DUPdAsm_32: 6715 case ARM::VLD3DUPqAsm_8: 6716 case ARM::VLD3DUPqAsm_16: 6717 case ARM::VLD3DUPqAsm_32: { 6718 MCInst TmpInst; 6719 unsigned Spacing; 6720 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6721 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6722 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6723 Spacing)); 6724 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6725 Spacing * 2)); 6726 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6727 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6728 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6729 TmpInst.addOperand(Inst.getOperand(4)); 6730 Inst = TmpInst; 6731 return true; 6732 } 6733 6734 case ARM::VLD3DUPdWB_fixed_Asm_8: 6735 case ARM::VLD3DUPdWB_fixed_Asm_16: 6736 case ARM::VLD3DUPdWB_fixed_Asm_32: 6737 case ARM::VLD3DUPqWB_fixed_Asm_8: 6738 case ARM::VLD3DUPqWB_fixed_Asm_16: 6739 case ARM::VLD3DUPqWB_fixed_Asm_32: { 6740 MCInst TmpInst; 6741 unsigned Spacing; 6742 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6743 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6744 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6745 Spacing)); 6746 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6747 Spacing * 2)); 6748 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6749 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6750 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6751 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6752 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6753 TmpInst.addOperand(Inst.getOperand(4)); 6754 Inst = TmpInst; 6755 return true; 6756 } 6757 6758 case ARM::VLD3DUPdWB_register_Asm_8: 6759 case ARM::VLD3DUPdWB_register_Asm_16: 6760 case ARM::VLD3DUPdWB_register_Asm_32: 6761 case ARM::VLD3DUPqWB_register_Asm_8: 6762 case ARM::VLD3DUPqWB_register_Asm_16: 6763 case ARM::VLD3DUPqWB_register_Asm_32: { 6764 MCInst TmpInst; 6765 unsigned Spacing; 6766 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6767 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6768 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6769 Spacing)); 6770 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6771 Spacing * 2)); 6772 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6773 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6774 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6775 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6776 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6777 TmpInst.addOperand(Inst.getOperand(5)); 6778 Inst = TmpInst; 6779 return true; 6780 } 6781 6782 // VLD3 multiple 3-element structure instructions. 6783 case ARM::VLD3dAsm_8: 6784 case ARM::VLD3dAsm_16: 6785 case ARM::VLD3dAsm_32: 6786 case ARM::VLD3qAsm_8: 6787 case ARM::VLD3qAsm_16: 6788 case ARM::VLD3qAsm_32: { 6789 MCInst TmpInst; 6790 unsigned Spacing; 6791 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6792 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6793 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6794 Spacing)); 6795 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6796 Spacing * 2)); 6797 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6798 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6799 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6800 TmpInst.addOperand(Inst.getOperand(4)); 6801 Inst = TmpInst; 6802 return true; 6803 } 6804 6805 case ARM::VLD3dWB_fixed_Asm_8: 6806 case ARM::VLD3dWB_fixed_Asm_16: 6807 case ARM::VLD3dWB_fixed_Asm_32: 6808 case ARM::VLD3qWB_fixed_Asm_8: 6809 case ARM::VLD3qWB_fixed_Asm_16: 6810 case ARM::VLD3qWB_fixed_Asm_32: { 6811 MCInst TmpInst; 6812 unsigned Spacing; 6813 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6814 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6815 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6816 Spacing)); 6817 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6818 Spacing * 2)); 6819 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6820 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6821 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6822 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6823 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6824 TmpInst.addOperand(Inst.getOperand(4)); 6825 Inst = TmpInst; 6826 return true; 6827 } 6828 6829 case ARM::VLD3dWB_register_Asm_8: 6830 case ARM::VLD3dWB_register_Asm_16: 6831 case ARM::VLD3dWB_register_Asm_32: 6832 case ARM::VLD3qWB_register_Asm_8: 6833 case ARM::VLD3qWB_register_Asm_16: 6834 case ARM::VLD3qWB_register_Asm_32: { 6835 MCInst TmpInst; 6836 unsigned Spacing; 6837 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6838 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6839 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6840 Spacing)); 6841 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6842 Spacing * 2)); 6843 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6844 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6845 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6846 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6847 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6848 TmpInst.addOperand(Inst.getOperand(5)); 6849 Inst = TmpInst; 6850 return true; 6851 } 6852 6853 // VLD4DUP single 3-element structure to all lanes instructions. 6854 case ARM::VLD4DUPdAsm_8: 6855 case ARM::VLD4DUPdAsm_16: 6856 case ARM::VLD4DUPdAsm_32: 6857 case ARM::VLD4DUPqAsm_8: 6858 case ARM::VLD4DUPqAsm_16: 6859 case ARM::VLD4DUPqAsm_32: { 6860 MCInst TmpInst; 6861 unsigned Spacing; 6862 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6863 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6864 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6865 Spacing)); 6866 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6867 Spacing * 2)); 6868 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6869 Spacing * 3)); 6870 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6871 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6872 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6873 TmpInst.addOperand(Inst.getOperand(4)); 6874 Inst = TmpInst; 6875 return true; 6876 } 6877 6878 case ARM::VLD4DUPdWB_fixed_Asm_8: 6879 case ARM::VLD4DUPdWB_fixed_Asm_16: 6880 case ARM::VLD4DUPdWB_fixed_Asm_32: 6881 case ARM::VLD4DUPqWB_fixed_Asm_8: 6882 case ARM::VLD4DUPqWB_fixed_Asm_16: 6883 case ARM::VLD4DUPqWB_fixed_Asm_32: { 6884 MCInst TmpInst; 6885 unsigned Spacing; 6886 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6887 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6889 Spacing)); 6890 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6891 Spacing * 2)); 6892 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6893 Spacing * 3)); 6894 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6895 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6896 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6897 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6898 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6899 TmpInst.addOperand(Inst.getOperand(4)); 6900 Inst = TmpInst; 6901 return true; 6902 } 6903 6904 case ARM::VLD4DUPdWB_register_Asm_8: 6905 case ARM::VLD4DUPdWB_register_Asm_16: 6906 case ARM::VLD4DUPdWB_register_Asm_32: 6907 case ARM::VLD4DUPqWB_register_Asm_8: 6908 case ARM::VLD4DUPqWB_register_Asm_16: 6909 case ARM::VLD4DUPqWB_register_Asm_32: { 6910 MCInst TmpInst; 6911 unsigned Spacing; 6912 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6913 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6914 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6915 Spacing)); 6916 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6917 Spacing * 2)); 6918 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6919 Spacing * 3)); 6920 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6921 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6922 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6923 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6924 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6925 TmpInst.addOperand(Inst.getOperand(5)); 6926 Inst = TmpInst; 6927 return true; 6928 } 6929 6930 // VLD4 multiple 4-element structure instructions. 6931 case ARM::VLD4dAsm_8: 6932 case ARM::VLD4dAsm_16: 6933 case ARM::VLD4dAsm_32: 6934 case ARM::VLD4qAsm_8: 6935 case ARM::VLD4qAsm_16: 6936 case ARM::VLD4qAsm_32: { 6937 MCInst TmpInst; 6938 unsigned Spacing; 6939 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6940 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6941 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6942 Spacing)); 6943 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6944 Spacing * 2)); 6945 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6946 Spacing * 3)); 6947 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6948 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6949 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6950 TmpInst.addOperand(Inst.getOperand(4)); 6951 Inst = TmpInst; 6952 return true; 6953 } 6954 6955 case ARM::VLD4dWB_fixed_Asm_8: 6956 case ARM::VLD4dWB_fixed_Asm_16: 6957 case ARM::VLD4dWB_fixed_Asm_32: 6958 case ARM::VLD4qWB_fixed_Asm_8: 6959 case ARM::VLD4qWB_fixed_Asm_16: 6960 case ARM::VLD4qWB_fixed_Asm_32: { 6961 MCInst TmpInst; 6962 unsigned Spacing; 6963 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6964 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6965 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6966 Spacing)); 6967 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6968 Spacing * 2)); 6969 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6970 Spacing * 3)); 6971 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6972 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6973 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6974 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6975 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6976 TmpInst.addOperand(Inst.getOperand(4)); 6977 Inst = TmpInst; 6978 return true; 6979 } 6980 6981 case ARM::VLD4dWB_register_Asm_8: 6982 case ARM::VLD4dWB_register_Asm_16: 6983 case ARM::VLD4dWB_register_Asm_32: 6984 case ARM::VLD4qWB_register_Asm_8: 6985 case ARM::VLD4qWB_register_Asm_16: 6986 case ARM::VLD4qWB_register_Asm_32: { 6987 MCInst TmpInst; 6988 unsigned Spacing; 6989 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6990 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6991 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6992 Spacing)); 6993 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6994 Spacing * 2)); 6995 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6996 Spacing * 3)); 6997 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6998 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6999 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7000 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7001 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7002 TmpInst.addOperand(Inst.getOperand(5)); 7003 Inst = TmpInst; 7004 return true; 7005 } 7006 7007 // VST3 multiple 3-element structure instructions. 7008 case ARM::VST3dAsm_8: 7009 case ARM::VST3dAsm_16: 7010 case ARM::VST3dAsm_32: 7011 case ARM::VST3qAsm_8: 7012 case ARM::VST3qAsm_16: 7013 case ARM::VST3qAsm_32: { 7014 MCInst TmpInst; 7015 unsigned Spacing; 7016 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7017 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7018 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7019 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7020 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7021 Spacing)); 7022 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7023 Spacing * 2)); 7024 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7025 TmpInst.addOperand(Inst.getOperand(4)); 7026 Inst = TmpInst; 7027 return true; 7028 } 7029 7030 case ARM::VST3dWB_fixed_Asm_8: 7031 case ARM::VST3dWB_fixed_Asm_16: 7032 case ARM::VST3dWB_fixed_Asm_32: 7033 case ARM::VST3qWB_fixed_Asm_8: 7034 case ARM::VST3qWB_fixed_Asm_16: 7035 case ARM::VST3qWB_fixed_Asm_32: { 7036 MCInst TmpInst; 7037 unsigned Spacing; 7038 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7039 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7040 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7041 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7042 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 7043 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7044 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7045 Spacing)); 7046 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7047 Spacing * 2)); 7048 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7049 TmpInst.addOperand(Inst.getOperand(4)); 7050 Inst = TmpInst; 7051 return true; 7052 } 7053 7054 case ARM::VST3dWB_register_Asm_8: 7055 case ARM::VST3dWB_register_Asm_16: 7056 case ARM::VST3dWB_register_Asm_32: 7057 case ARM::VST3qWB_register_Asm_8: 7058 case ARM::VST3qWB_register_Asm_16: 7059 case ARM::VST3qWB_register_Asm_32: { 7060 MCInst TmpInst; 7061 unsigned Spacing; 7062 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7063 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7064 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7065 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7066 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7067 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7068 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7069 Spacing)); 7070 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7071 Spacing * 2)); 7072 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7073 TmpInst.addOperand(Inst.getOperand(5)); 7074 Inst = TmpInst; 7075 return true; 7076 } 7077 7078 // VST4 multiple 3-element structure instructions. 7079 case ARM::VST4dAsm_8: 7080 case ARM::VST4dAsm_16: 7081 case ARM::VST4dAsm_32: 7082 case ARM::VST4qAsm_8: 7083 case ARM::VST4qAsm_16: 7084 case ARM::VST4qAsm_32: { 7085 MCInst TmpInst; 7086 unsigned Spacing; 7087 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7088 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7089 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7090 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7091 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7092 Spacing)); 7093 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7094 Spacing * 2)); 7095 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7096 Spacing * 3)); 7097 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7098 TmpInst.addOperand(Inst.getOperand(4)); 7099 Inst = TmpInst; 7100 return true; 7101 } 7102 7103 case ARM::VST4dWB_fixed_Asm_8: 7104 case ARM::VST4dWB_fixed_Asm_16: 7105 case ARM::VST4dWB_fixed_Asm_32: 7106 case ARM::VST4qWB_fixed_Asm_8: 7107 case ARM::VST4qWB_fixed_Asm_16: 7108 case ARM::VST4qWB_fixed_Asm_32: { 7109 MCInst TmpInst; 7110 unsigned Spacing; 7111 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7112 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7113 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7114 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7115 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 7116 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7117 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7118 Spacing)); 7119 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7120 Spacing * 2)); 7121 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7122 Spacing * 3)); 7123 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7124 TmpInst.addOperand(Inst.getOperand(4)); 7125 Inst = TmpInst; 7126 return true; 7127 } 7128 7129 case ARM::VST4dWB_register_Asm_8: 7130 case ARM::VST4dWB_register_Asm_16: 7131 case ARM::VST4dWB_register_Asm_32: 7132 case ARM::VST4qWB_register_Asm_8: 7133 case ARM::VST4qWB_register_Asm_16: 7134 case ARM::VST4qWB_register_Asm_32: { 7135 MCInst TmpInst; 7136 unsigned Spacing; 7137 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7138 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7139 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7140 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7141 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7142 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7143 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7144 Spacing)); 7145 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7146 Spacing * 2)); 7147 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7148 Spacing * 3)); 7149 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7150 TmpInst.addOperand(Inst.getOperand(5)); 7151 Inst = TmpInst; 7152 return true; 7153 } 7154 7155 // Handle encoding choice for the shift-immediate instructions. 7156 case ARM::t2LSLri: 7157 case ARM::t2LSRri: 7158 case ARM::t2ASRri: { 7159 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7160 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7161 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 7162 !(static_cast<ARMOperand*>(Operands[3])->isToken() && 7163 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) { 7164 unsigned NewOpc; 7165 switch (Inst.getOpcode()) { 7166 default: llvm_unreachable("unexpected opcode"); 7167 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 7168 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 7169 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 7170 } 7171 // The Thumb1 operands aren't in the same order. Awesome, eh? 7172 MCInst TmpInst; 7173 TmpInst.setOpcode(NewOpc); 7174 TmpInst.addOperand(Inst.getOperand(0)); 7175 TmpInst.addOperand(Inst.getOperand(5)); 7176 TmpInst.addOperand(Inst.getOperand(1)); 7177 TmpInst.addOperand(Inst.getOperand(2)); 7178 TmpInst.addOperand(Inst.getOperand(3)); 7179 TmpInst.addOperand(Inst.getOperand(4)); 7180 Inst = TmpInst; 7181 return true; 7182 } 7183 return false; 7184 } 7185 7186 // Handle the Thumb2 mode MOV complex aliases. 7187 case ARM::t2MOVsr: 7188 case ARM::t2MOVSsr: { 7189 // Which instruction to expand to depends on the CCOut operand and 7190 // whether we're in an IT block if the register operands are low 7191 // registers. 7192 bool isNarrow = false; 7193 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7194 isARMLowRegister(Inst.getOperand(1).getReg()) && 7195 isARMLowRegister(Inst.getOperand(2).getReg()) && 7196 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7197 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 7198 isNarrow = true; 7199 MCInst TmpInst; 7200 unsigned newOpc; 7201 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 7202 default: llvm_unreachable("unexpected opcode!"); 7203 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 7204 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 7205 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 7206 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 7207 } 7208 TmpInst.setOpcode(newOpc); 7209 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7210 if (isNarrow) 7211 TmpInst.addOperand(MCOperand::CreateReg( 7212 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7213 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7214 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7215 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7216 TmpInst.addOperand(Inst.getOperand(5)); 7217 if (!isNarrow) 7218 TmpInst.addOperand(MCOperand::CreateReg( 7219 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7220 Inst = TmpInst; 7221 return true; 7222 } 7223 case ARM::t2MOVsi: 7224 case ARM::t2MOVSsi: { 7225 // Which instruction to expand to depends on the CCOut operand and 7226 // whether we're in an IT block if the register operands are low 7227 // registers. 7228 bool isNarrow = false; 7229 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7230 isARMLowRegister(Inst.getOperand(1).getReg()) && 7231 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 7232 isNarrow = true; 7233 MCInst TmpInst; 7234 unsigned newOpc; 7235 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 7236 default: llvm_unreachable("unexpected opcode!"); 7237 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 7238 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 7239 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 7240 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 7241 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 7242 } 7243 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 7244 if (Amount == 32) Amount = 0; 7245 TmpInst.setOpcode(newOpc); 7246 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7247 if (isNarrow) 7248 TmpInst.addOperand(MCOperand::CreateReg( 7249 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7250 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7251 if (newOpc != ARM::t2RRX) 7252 TmpInst.addOperand(MCOperand::CreateImm(Amount)); 7253 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7254 TmpInst.addOperand(Inst.getOperand(4)); 7255 if (!isNarrow) 7256 TmpInst.addOperand(MCOperand::CreateReg( 7257 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7258 Inst = TmpInst; 7259 return true; 7260 } 7261 // Handle the ARM mode MOV complex aliases. 7262 case ARM::ASRr: 7263 case ARM::LSRr: 7264 case ARM::LSLr: 7265 case ARM::RORr: { 7266 ARM_AM::ShiftOpc ShiftTy; 7267 switch(Inst.getOpcode()) { 7268 default: llvm_unreachable("unexpected opcode!"); 7269 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 7270 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 7271 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 7272 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 7273 } 7274 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 7275 MCInst TmpInst; 7276 TmpInst.setOpcode(ARM::MOVsr); 7277 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7278 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7279 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7280 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7281 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7282 TmpInst.addOperand(Inst.getOperand(4)); 7283 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7284 Inst = TmpInst; 7285 return true; 7286 } 7287 case ARM::ASRi: 7288 case ARM::LSRi: 7289 case ARM::LSLi: 7290 case ARM::RORi: { 7291 ARM_AM::ShiftOpc ShiftTy; 7292 switch(Inst.getOpcode()) { 7293 default: llvm_unreachable("unexpected opcode!"); 7294 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 7295 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 7296 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 7297 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 7298 } 7299 // A shift by zero is a plain MOVr, not a MOVsi. 7300 unsigned Amt = Inst.getOperand(2).getImm(); 7301 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 7302 // A shift by 32 should be encoded as 0 when permitted 7303 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 7304 Amt = 0; 7305 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 7306 MCInst TmpInst; 7307 TmpInst.setOpcode(Opc); 7308 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7309 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7310 if (Opc == ARM::MOVsi) 7311 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7312 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7313 TmpInst.addOperand(Inst.getOperand(4)); 7314 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7315 Inst = TmpInst; 7316 return true; 7317 } 7318 case ARM::RRXi: { 7319 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 7320 MCInst TmpInst; 7321 TmpInst.setOpcode(ARM::MOVsi); 7322 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7323 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7324 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7325 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7326 TmpInst.addOperand(Inst.getOperand(3)); 7327 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 7328 Inst = TmpInst; 7329 return true; 7330 } 7331 case ARM::t2LDMIA_UPD: { 7332 // If this is a load of a single register, then we should use 7333 // a post-indexed LDR instruction instead, per the ARM ARM. 7334 if (Inst.getNumOperands() != 5) 7335 return false; 7336 MCInst TmpInst; 7337 TmpInst.setOpcode(ARM::t2LDR_POST); 7338 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7339 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7340 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7341 TmpInst.addOperand(MCOperand::CreateImm(4)); 7342 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7343 TmpInst.addOperand(Inst.getOperand(3)); 7344 Inst = TmpInst; 7345 return true; 7346 } 7347 case ARM::t2STMDB_UPD: { 7348 // If this is a store of a single register, then we should use 7349 // a pre-indexed STR instruction instead, per the ARM ARM. 7350 if (Inst.getNumOperands() != 5) 7351 return false; 7352 MCInst TmpInst; 7353 TmpInst.setOpcode(ARM::t2STR_PRE); 7354 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7355 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7356 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7357 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7358 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7359 TmpInst.addOperand(Inst.getOperand(3)); 7360 Inst = TmpInst; 7361 return true; 7362 } 7363 case ARM::LDMIA_UPD: 7364 // If this is a load of a single register via a 'pop', then we should use 7365 // a post-indexed LDR instruction instead, per the ARM ARM. 7366 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 7367 Inst.getNumOperands() == 5) { 7368 MCInst TmpInst; 7369 TmpInst.setOpcode(ARM::LDR_POST_IMM); 7370 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7371 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7372 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7373 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 7374 TmpInst.addOperand(MCOperand::CreateImm(4)); 7375 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7376 TmpInst.addOperand(Inst.getOperand(3)); 7377 Inst = TmpInst; 7378 return true; 7379 } 7380 break; 7381 case ARM::STMDB_UPD: 7382 // If this is a store of a single register via a 'push', then we should use 7383 // a pre-indexed STR instruction instead, per the ARM ARM. 7384 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 7385 Inst.getNumOperands() == 5) { 7386 MCInst TmpInst; 7387 TmpInst.setOpcode(ARM::STR_PRE_IMM); 7388 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7389 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7390 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 7391 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7392 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7393 TmpInst.addOperand(Inst.getOperand(3)); 7394 Inst = TmpInst; 7395 } 7396 break; 7397 case ARM::t2ADDri12: 7398 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 7399 // mnemonic was used (not "addw"), encoding T3 is preferred. 7400 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 7401 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7402 break; 7403 Inst.setOpcode(ARM::t2ADDri); 7404 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7405 break; 7406 case ARM::t2SUBri12: 7407 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 7408 // mnemonic was used (not "subw"), encoding T3 is preferred. 7409 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 7410 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7411 break; 7412 Inst.setOpcode(ARM::t2SUBri); 7413 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7414 break; 7415 case ARM::tADDi8: 7416 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7417 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7418 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7419 // to encoding T1 if <Rd> is omitted." 7420 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7421 Inst.setOpcode(ARM::tADDi3); 7422 return true; 7423 } 7424 break; 7425 case ARM::tSUBi8: 7426 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7427 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7428 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7429 // to encoding T1 if <Rd> is omitted." 7430 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7431 Inst.setOpcode(ARM::tSUBi3); 7432 return true; 7433 } 7434 break; 7435 case ARM::t2ADDri: 7436 case ARM::t2SUBri: { 7437 // If the destination and first source operand are the same, and 7438 // the flags are compatible with the current IT status, use encoding T2 7439 // instead of T3. For compatibility with the system 'as'. Make sure the 7440 // wide encoding wasn't explicit. 7441 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7442 !isARMLowRegister(Inst.getOperand(0).getReg()) || 7443 (unsigned)Inst.getOperand(2).getImm() > 255 || 7444 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 7445 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 7446 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7447 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7448 break; 7449 MCInst TmpInst; 7450 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 7451 ARM::tADDi8 : ARM::tSUBi8); 7452 TmpInst.addOperand(Inst.getOperand(0)); 7453 TmpInst.addOperand(Inst.getOperand(5)); 7454 TmpInst.addOperand(Inst.getOperand(0)); 7455 TmpInst.addOperand(Inst.getOperand(2)); 7456 TmpInst.addOperand(Inst.getOperand(3)); 7457 TmpInst.addOperand(Inst.getOperand(4)); 7458 Inst = TmpInst; 7459 return true; 7460 } 7461 case ARM::t2ADDrr: { 7462 // If the destination and first source operand are the same, and 7463 // there's no setting of the flags, use encoding T2 instead of T3. 7464 // Note that this is only for ADD, not SUB. This mirrors the system 7465 // 'as' behaviour. Make sure the wide encoding wasn't explicit. 7466 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7467 Inst.getOperand(5).getReg() != 0 || 7468 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7469 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7470 break; 7471 MCInst TmpInst; 7472 TmpInst.setOpcode(ARM::tADDhirr); 7473 TmpInst.addOperand(Inst.getOperand(0)); 7474 TmpInst.addOperand(Inst.getOperand(0)); 7475 TmpInst.addOperand(Inst.getOperand(2)); 7476 TmpInst.addOperand(Inst.getOperand(3)); 7477 TmpInst.addOperand(Inst.getOperand(4)); 7478 Inst = TmpInst; 7479 return true; 7480 } 7481 case ARM::tADDrSP: { 7482 // If the non-SP source operand and the destination operand are not the 7483 // same, we need to use the 32-bit encoding if it's available. 7484 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7485 Inst.setOpcode(ARM::t2ADDrr); 7486 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7487 return true; 7488 } 7489 break; 7490 } 7491 case ARM::tB: 7492 // A Thumb conditional branch outside of an IT block is a tBcc. 7493 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 7494 Inst.setOpcode(ARM::tBcc); 7495 return true; 7496 } 7497 break; 7498 case ARM::t2B: 7499 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 7500 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 7501 Inst.setOpcode(ARM::t2Bcc); 7502 return true; 7503 } 7504 break; 7505 case ARM::t2Bcc: 7506 // If the conditional is AL or we're in an IT block, we really want t2B. 7507 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 7508 Inst.setOpcode(ARM::t2B); 7509 return true; 7510 } 7511 break; 7512 case ARM::tBcc: 7513 // If the conditional is AL, we really want tB. 7514 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 7515 Inst.setOpcode(ARM::tB); 7516 return true; 7517 } 7518 break; 7519 case ARM::tLDMIA: { 7520 // If the register list contains any high registers, or if the writeback 7521 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 7522 // instead if we're in Thumb2. Otherwise, this should have generated 7523 // an error in validateInstruction(). 7524 unsigned Rn = Inst.getOperand(0).getReg(); 7525 bool hasWritebackToken = 7526 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7527 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 7528 bool listContainsBase; 7529 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 7530 (!listContainsBase && !hasWritebackToken) || 7531 (listContainsBase && hasWritebackToken)) { 7532 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7533 assert (isThumbTwo()); 7534 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 7535 // If we're switching to the updating version, we need to insert 7536 // the writeback tied operand. 7537 if (hasWritebackToken) 7538 Inst.insert(Inst.begin(), 7539 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 7540 return true; 7541 } 7542 break; 7543 } 7544 case ARM::tSTMIA_UPD: { 7545 // If the register list contains any high registers, we need to use 7546 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7547 // should have generated an error in validateInstruction(). 7548 unsigned Rn = Inst.getOperand(0).getReg(); 7549 bool listContainsBase; 7550 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 7551 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7552 assert (isThumbTwo()); 7553 Inst.setOpcode(ARM::t2STMIA_UPD); 7554 return true; 7555 } 7556 break; 7557 } 7558 case ARM::tPOP: { 7559 bool listContainsBase; 7560 // If the register list contains any high registers, we need to use 7561 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7562 // should have generated an error in validateInstruction(). 7563 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 7564 return false; 7565 assert (isThumbTwo()); 7566 Inst.setOpcode(ARM::t2LDMIA_UPD); 7567 // Add the base register and writeback operands. 7568 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7569 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7570 return true; 7571 } 7572 case ARM::tPUSH: { 7573 bool listContainsBase; 7574 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 7575 return false; 7576 assert (isThumbTwo()); 7577 Inst.setOpcode(ARM::t2STMDB_UPD); 7578 // Add the base register and writeback operands. 7579 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7580 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7581 return true; 7582 } 7583 case ARM::t2MOVi: { 7584 // If we can use the 16-bit encoding and the user didn't explicitly 7585 // request the 32-bit variant, transform it here. 7586 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7587 (unsigned)Inst.getOperand(1).getImm() <= 255 && 7588 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 7589 Inst.getOperand(4).getReg() == ARM::CPSR) || 7590 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 7591 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7592 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7593 // The operands aren't in the same order for tMOVi8... 7594 MCInst TmpInst; 7595 TmpInst.setOpcode(ARM::tMOVi8); 7596 TmpInst.addOperand(Inst.getOperand(0)); 7597 TmpInst.addOperand(Inst.getOperand(4)); 7598 TmpInst.addOperand(Inst.getOperand(1)); 7599 TmpInst.addOperand(Inst.getOperand(2)); 7600 TmpInst.addOperand(Inst.getOperand(3)); 7601 Inst = TmpInst; 7602 return true; 7603 } 7604 break; 7605 } 7606 case ARM::t2MOVr: { 7607 // If we can use the 16-bit encoding and the user didn't explicitly 7608 // request the 32-bit variant, transform it here. 7609 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7610 isARMLowRegister(Inst.getOperand(1).getReg()) && 7611 Inst.getOperand(2).getImm() == ARMCC::AL && 7612 Inst.getOperand(4).getReg() == ARM::CPSR && 7613 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7614 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7615 // The operands aren't the same for tMOV[S]r... (no cc_out) 7616 MCInst TmpInst; 7617 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 7618 TmpInst.addOperand(Inst.getOperand(0)); 7619 TmpInst.addOperand(Inst.getOperand(1)); 7620 TmpInst.addOperand(Inst.getOperand(2)); 7621 TmpInst.addOperand(Inst.getOperand(3)); 7622 Inst = TmpInst; 7623 return true; 7624 } 7625 break; 7626 } 7627 case ARM::t2SXTH: 7628 case ARM::t2SXTB: 7629 case ARM::t2UXTH: 7630 case ARM::t2UXTB: { 7631 // If we can use the 16-bit encoding and the user didn't explicitly 7632 // request the 32-bit variant, transform it here. 7633 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7634 isARMLowRegister(Inst.getOperand(1).getReg()) && 7635 Inst.getOperand(2).getImm() == 0 && 7636 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7637 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7638 unsigned NewOpc; 7639 switch (Inst.getOpcode()) { 7640 default: llvm_unreachable("Illegal opcode!"); 7641 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 7642 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 7643 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 7644 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 7645 } 7646 // The operands aren't the same for thumb1 (no rotate operand). 7647 MCInst TmpInst; 7648 TmpInst.setOpcode(NewOpc); 7649 TmpInst.addOperand(Inst.getOperand(0)); 7650 TmpInst.addOperand(Inst.getOperand(1)); 7651 TmpInst.addOperand(Inst.getOperand(3)); 7652 TmpInst.addOperand(Inst.getOperand(4)); 7653 Inst = TmpInst; 7654 return true; 7655 } 7656 break; 7657 } 7658 case ARM::MOVsi: { 7659 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 7660 // rrx shifts and asr/lsr of #32 is encoded as 0 7661 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 7662 return false; 7663 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 7664 // Shifting by zero is accepted as a vanilla 'MOVr' 7665 MCInst TmpInst; 7666 TmpInst.setOpcode(ARM::MOVr); 7667 TmpInst.addOperand(Inst.getOperand(0)); 7668 TmpInst.addOperand(Inst.getOperand(1)); 7669 TmpInst.addOperand(Inst.getOperand(3)); 7670 TmpInst.addOperand(Inst.getOperand(4)); 7671 TmpInst.addOperand(Inst.getOperand(5)); 7672 Inst = TmpInst; 7673 return true; 7674 } 7675 return false; 7676 } 7677 case ARM::ANDrsi: 7678 case ARM::ORRrsi: 7679 case ARM::EORrsi: 7680 case ARM::BICrsi: 7681 case ARM::SUBrsi: 7682 case ARM::ADDrsi: { 7683 unsigned newOpc; 7684 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 7685 if (SOpc == ARM_AM::rrx) return false; 7686 switch (Inst.getOpcode()) { 7687 default: llvm_unreachable("unexpected opcode!"); 7688 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 7689 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 7690 case ARM::EORrsi: newOpc = ARM::EORrr; break; 7691 case ARM::BICrsi: newOpc = ARM::BICrr; break; 7692 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 7693 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 7694 } 7695 // If the shift is by zero, use the non-shifted instruction definition. 7696 // The exception is for right shifts, where 0 == 32 7697 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 7698 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 7699 MCInst TmpInst; 7700 TmpInst.setOpcode(newOpc); 7701 TmpInst.addOperand(Inst.getOperand(0)); 7702 TmpInst.addOperand(Inst.getOperand(1)); 7703 TmpInst.addOperand(Inst.getOperand(2)); 7704 TmpInst.addOperand(Inst.getOperand(4)); 7705 TmpInst.addOperand(Inst.getOperand(5)); 7706 TmpInst.addOperand(Inst.getOperand(6)); 7707 Inst = TmpInst; 7708 return true; 7709 } 7710 return false; 7711 } 7712 case ARM::ITasm: 7713 case ARM::t2IT: { 7714 // The mask bits for all but the first condition are represented as 7715 // the low bit of the condition code value implies 't'. We currently 7716 // always have 1 implies 't', so XOR toggle the bits if the low bit 7717 // of the condition code is zero. 7718 MCOperand &MO = Inst.getOperand(1); 7719 unsigned Mask = MO.getImm(); 7720 unsigned OrigMask = Mask; 7721 unsigned TZ = countTrailingZeros(Mask); 7722 if ((Inst.getOperand(0).getImm() & 1) == 0) { 7723 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 7724 Mask ^= (0xE << TZ) & 0xF; 7725 } 7726 MO.setImm(Mask); 7727 7728 // Set up the IT block state according to the IT instruction we just 7729 // matched. 7730 assert(!inITBlock() && "nested IT blocks?!"); 7731 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 7732 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 7733 ITState.CurPosition = 0; 7734 ITState.FirstCond = true; 7735 break; 7736 } 7737 case ARM::t2LSLrr: 7738 case ARM::t2LSRrr: 7739 case ARM::t2ASRrr: 7740 case ARM::t2SBCrr: 7741 case ARM::t2RORrr: 7742 case ARM::t2BICrr: 7743 { 7744 // Assemblers should use the narrow encodings of these instructions when permissible. 7745 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7746 isARMLowRegister(Inst.getOperand(2).getReg())) && 7747 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7748 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7749 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7750 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7751 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7752 unsigned NewOpc; 7753 switch (Inst.getOpcode()) { 7754 default: llvm_unreachable("unexpected opcode"); 7755 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 7756 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 7757 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 7758 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 7759 case ARM::t2RORrr: NewOpc = ARM::tROR; break; 7760 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 7761 } 7762 MCInst TmpInst; 7763 TmpInst.setOpcode(NewOpc); 7764 TmpInst.addOperand(Inst.getOperand(0)); 7765 TmpInst.addOperand(Inst.getOperand(5)); 7766 TmpInst.addOperand(Inst.getOperand(1)); 7767 TmpInst.addOperand(Inst.getOperand(2)); 7768 TmpInst.addOperand(Inst.getOperand(3)); 7769 TmpInst.addOperand(Inst.getOperand(4)); 7770 Inst = TmpInst; 7771 return true; 7772 } 7773 return false; 7774 } 7775 case ARM::t2ANDrr: 7776 case ARM::t2EORrr: 7777 case ARM::t2ADCrr: 7778 case ARM::t2ORRrr: 7779 { 7780 // Assemblers should use the narrow encodings of these instructions when permissible. 7781 // These instructions are special in that they are commutable, so shorter encodings 7782 // are available more often. 7783 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7784 isARMLowRegister(Inst.getOperand(2).getReg())) && 7785 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 7786 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 7787 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7788 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7789 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7790 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7791 unsigned NewOpc; 7792 switch (Inst.getOpcode()) { 7793 default: llvm_unreachable("unexpected opcode"); 7794 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 7795 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 7796 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 7797 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 7798 } 7799 MCInst TmpInst; 7800 TmpInst.setOpcode(NewOpc); 7801 TmpInst.addOperand(Inst.getOperand(0)); 7802 TmpInst.addOperand(Inst.getOperand(5)); 7803 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 7804 TmpInst.addOperand(Inst.getOperand(1)); 7805 TmpInst.addOperand(Inst.getOperand(2)); 7806 } else { 7807 TmpInst.addOperand(Inst.getOperand(2)); 7808 TmpInst.addOperand(Inst.getOperand(1)); 7809 } 7810 TmpInst.addOperand(Inst.getOperand(3)); 7811 TmpInst.addOperand(Inst.getOperand(4)); 7812 Inst = TmpInst; 7813 return true; 7814 } 7815 return false; 7816 } 7817 } 7818 return false; 7819} 7820 7821unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 7822 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 7823 // suffix depending on whether they're in an IT block or not. 7824 unsigned Opc = Inst.getOpcode(); 7825 const MCInstrDesc &MCID = MII.get(Opc); 7826 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 7827 assert(MCID.hasOptionalDef() && 7828 "optionally flag setting instruction missing optional def operand"); 7829 assert(MCID.NumOperands == Inst.getNumOperands() && 7830 "operand count mismatch!"); 7831 // Find the optional-def operand (cc_out). 7832 unsigned OpNo; 7833 for (OpNo = 0; 7834 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 7835 ++OpNo) 7836 ; 7837 // If we're parsing Thumb1, reject it completely. 7838 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 7839 return Match_MnemonicFail; 7840 // If we're parsing Thumb2, which form is legal depends on whether we're 7841 // in an IT block. 7842 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 7843 !inITBlock()) 7844 return Match_RequiresITBlock; 7845 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 7846 inITBlock()) 7847 return Match_RequiresNotITBlock; 7848 } 7849 // Some high-register supporting Thumb1 encodings only allow both registers 7850 // to be from r0-r7 when in Thumb2. 7851 else if (Opc == ARM::tADDhirr && isThumbOne() && 7852 isARMLowRegister(Inst.getOperand(1).getReg()) && 7853 isARMLowRegister(Inst.getOperand(2).getReg())) 7854 return Match_RequiresThumb2; 7855 // Others only require ARMv6 or later. 7856 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 7857 isARMLowRegister(Inst.getOperand(0).getReg()) && 7858 isARMLowRegister(Inst.getOperand(1).getReg())) 7859 return Match_RequiresV6; 7860 return Match_Success; 7861} 7862 7863template<> inline bool IsCPSRDead<MCInst>(MCInst* Instr) { 7864 return true; // In an assembly source, no need to second-guess 7865} 7866 7867static const char *getSubtargetFeatureName(unsigned Val); 7868bool ARMAsmParser:: 7869MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 7870 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 7871 MCStreamer &Out, unsigned &ErrorInfo, 7872 bool MatchingInlineAsm) { 7873 MCInst Inst; 7874 unsigned MatchResult; 7875 7876 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 7877 MatchingInlineAsm); 7878 switch (MatchResult) { 7879 default: break; 7880 case Match_Success: 7881 // Context sensitive operand constraints aren't handled by the matcher, 7882 // so check them here. 7883 if (validateInstruction(Inst, Operands)) { 7884 // Still progress the IT block, otherwise one wrong condition causes 7885 // nasty cascading errors. 7886 forwardITPosition(); 7887 return true; 7888 } 7889 7890 { // processInstruction() updates inITBlock state, we need to save it away 7891 bool wasInITBlock = inITBlock(); 7892 7893 // Some instructions need post-processing to, for example, tweak which 7894 // encoding is selected. Loop on it while changes happen so the 7895 // individual transformations can chain off each other. E.g., 7896 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 7897 while (processInstruction(Inst, Operands)) 7898 ; 7899 7900 // Only after the instruction is fully processed, we can validate it 7901 if (wasInITBlock && hasV8Ops() && isThumb() && 7902 !isV8EligibleForIT(&Inst)) { 7903 Warning(IDLoc, "deprecated instruction in IT block"); 7904 } 7905 } 7906 7907 // Only move forward at the very end so that everything in validate 7908 // and process gets a consistent answer about whether we're in an IT 7909 // block. 7910 forwardITPosition(); 7911 7912 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 7913 // doesn't actually encode. 7914 if (Inst.getOpcode() == ARM::ITasm) 7915 return false; 7916 7917 Inst.setLoc(IDLoc); 7918 Out.EmitInstruction(Inst, STI); 7919 return false; 7920 case Match_MissingFeature: { 7921 assert(ErrorInfo && "Unknown missing feature!"); 7922 // Special case the error message for the very common case where only 7923 // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 7924 std::string Msg = "instruction requires:"; 7925 unsigned Mask = 1; 7926 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 7927 if (ErrorInfo & Mask) { 7928 Msg += " "; 7929 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 7930 } 7931 Mask <<= 1; 7932 } 7933 return Error(IDLoc, Msg); 7934 } 7935 case Match_InvalidOperand: { 7936 SMLoc ErrorLoc = IDLoc; 7937 if (ErrorInfo != ~0U) { 7938 if (ErrorInfo >= Operands.size()) 7939 return Error(IDLoc, "too few operands for instruction"); 7940 7941 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7942 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7943 } 7944 7945 return Error(ErrorLoc, "invalid operand for instruction"); 7946 } 7947 case Match_MnemonicFail: 7948 return Error(IDLoc, "invalid instruction", 7949 ((ARMOperand*)Operands[0])->getLocRange()); 7950 case Match_RequiresNotITBlock: 7951 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 7952 case Match_RequiresITBlock: 7953 return Error(IDLoc, "instruction only valid inside IT block"); 7954 case Match_RequiresV6: 7955 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 7956 case Match_RequiresThumb2: 7957 return Error(IDLoc, "instruction variant requires Thumb2"); 7958 case Match_ImmRange0_15: { 7959 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7960 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7961 return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 7962 } 7963 case Match_ImmRange0_239: { 7964 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7965 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7966 return Error(ErrorLoc, "immediate operand must be in the range [0,239]"); 7967 } 7968 } 7969 7970 llvm_unreachable("Implement any new match types added!"); 7971} 7972 7973/// parseDirective parses the arm specific directives 7974bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 7975 StringRef IDVal = DirectiveID.getIdentifier(); 7976 if (IDVal == ".word") 7977 return parseLiteralValues(4, DirectiveID.getLoc()); 7978 else if (IDVal == ".short" || IDVal == ".hword") 7979 return parseLiteralValues(2, DirectiveID.getLoc()); 7980 else if (IDVal == ".thumb") 7981 return parseDirectiveThumb(DirectiveID.getLoc()); 7982 else if (IDVal == ".arm") 7983 return parseDirectiveARM(DirectiveID.getLoc()); 7984 else if (IDVal == ".thumb_func") 7985 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 7986 else if (IDVal == ".code") 7987 return parseDirectiveCode(DirectiveID.getLoc()); 7988 else if (IDVal == ".syntax") 7989 return parseDirectiveSyntax(DirectiveID.getLoc()); 7990 else if (IDVal == ".unreq") 7991 return parseDirectiveUnreq(DirectiveID.getLoc()); 7992 else if (IDVal == ".arch") 7993 return parseDirectiveArch(DirectiveID.getLoc()); 7994 else if (IDVal == ".eabi_attribute") 7995 return parseDirectiveEabiAttr(DirectiveID.getLoc()); 7996 else if (IDVal == ".cpu") 7997 return parseDirectiveCPU(DirectiveID.getLoc()); 7998 else if (IDVal == ".fpu") 7999 return parseDirectiveFPU(DirectiveID.getLoc()); 8000 else if (IDVal == ".fnstart") 8001 return parseDirectiveFnStart(DirectiveID.getLoc()); 8002 else if (IDVal == ".fnend") 8003 return parseDirectiveFnEnd(DirectiveID.getLoc()); 8004 else if (IDVal == ".cantunwind") 8005 return parseDirectiveCantUnwind(DirectiveID.getLoc()); 8006 else if (IDVal == ".personality") 8007 return parseDirectivePersonality(DirectiveID.getLoc()); 8008 else if (IDVal == ".handlerdata") 8009 return parseDirectiveHandlerData(DirectiveID.getLoc()); 8010 else if (IDVal == ".setfp") 8011 return parseDirectiveSetFP(DirectiveID.getLoc()); 8012 else if (IDVal == ".pad") 8013 return parseDirectivePad(DirectiveID.getLoc()); 8014 else if (IDVal == ".save") 8015 return parseDirectiveRegSave(DirectiveID.getLoc(), false); 8016 else if (IDVal == ".vsave") 8017 return parseDirectiveRegSave(DirectiveID.getLoc(), true); 8018 else if (IDVal == ".inst") 8019 return parseDirectiveInst(DirectiveID.getLoc()); 8020 else if (IDVal == ".inst.n") 8021 return parseDirectiveInst(DirectiveID.getLoc(), 'n'); 8022 else if (IDVal == ".inst.w") 8023 return parseDirectiveInst(DirectiveID.getLoc(), 'w'); 8024 else if (IDVal == ".ltorg" || IDVal == ".pool") 8025 return parseDirectiveLtorg(DirectiveID.getLoc()); 8026 else if (IDVal == ".even") 8027 return parseDirectiveEven(DirectiveID.getLoc()); 8028 else if (IDVal == ".personalityindex") 8029 return parseDirectivePersonalityIndex(DirectiveID.getLoc()); 8030 else if (IDVal == ".unwind_raw") 8031 return parseDirectiveUnwindRaw(DirectiveID.getLoc()); 8032 else if (IDVal == ".tlsdescseq") 8033 return parseDirectiveTLSDescSeq(DirectiveID.getLoc()); 8034 else if (IDVal == ".movsp") 8035 return parseDirectiveMovSP(DirectiveID.getLoc()); 8036 else if (IDVal == ".object_arch") 8037 return parseDirectiveObjectArch(DirectiveID.getLoc()); 8038 else if (IDVal == ".arch_extension") 8039 return parseDirectiveArchExtension(DirectiveID.getLoc()); 8040 else if (IDVal == ".align") 8041 return parseDirectiveAlign(DirectiveID.getLoc()); 8042 else if (IDVal == ".thumb_set") 8043 return parseDirectiveThumbSet(DirectiveID.getLoc()); 8044 return true; 8045} 8046 8047/// parseLiteralValues 8048/// ::= .hword expression [, expression]* 8049/// ::= .short expression [, expression]* 8050/// ::= .word expression [, expression]* 8051bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) { 8052 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8053 for (;;) { 8054 const MCExpr *Value; 8055 if (getParser().parseExpression(Value)) { 8056 Parser.eatToEndOfStatement(); 8057 return false; 8058 } 8059 8060 getParser().getStreamer().EmitValue(Value, Size); 8061 8062 if (getLexer().is(AsmToken::EndOfStatement)) 8063 break; 8064 8065 // FIXME: Improve diagnostic. 8066 if (getLexer().isNot(AsmToken::Comma)) { 8067 Error(L, "unexpected token in directive"); 8068 return false; 8069 } 8070 Parser.Lex(); 8071 } 8072 } 8073 8074 Parser.Lex(); 8075 return false; 8076} 8077 8078/// parseDirectiveThumb 8079/// ::= .thumb 8080bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 8081 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8082 Error(L, "unexpected token in directive"); 8083 return false; 8084 } 8085 Parser.Lex(); 8086 8087 if (!hasThumb()) { 8088 Error(L, "target does not support Thumb mode"); 8089 return false; 8090 } 8091 8092 if (!isThumb()) 8093 SwitchMode(); 8094 8095 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 8096 return false; 8097} 8098 8099/// parseDirectiveARM 8100/// ::= .arm 8101bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 8102 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8103 Error(L, "unexpected token in directive"); 8104 return false; 8105 } 8106 Parser.Lex(); 8107 8108 if (!hasARM()) { 8109 Error(L, "target does not support ARM mode"); 8110 return false; 8111 } 8112 8113 if (isThumb()) 8114 SwitchMode(); 8115 8116 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 8117 return false; 8118} 8119 8120void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) { 8121 if (NextSymbolIsThumb) { 8122 getParser().getStreamer().EmitThumbFunc(Symbol); 8123 NextSymbolIsThumb = false; 8124 return; 8125 } 8126 8127 if (!isThumb()) 8128 return; 8129 8130 const MCObjectFileInfo::Environment Format = 8131 getContext().getObjectFileInfo()->getObjectFileType(); 8132 switch (Format) { 8133 case MCObjectFileInfo::IsCOFF: { 8134 const MCSymbolData &SD = 8135 getParser().getStreamer().getOrCreateSymbolData(Symbol); 8136 char Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT; 8137 if (SD.getFlags() & (Type << COFF::SF_TypeShift)) 8138 getParser().getStreamer().EmitThumbFunc(Symbol); 8139 break; 8140 } 8141 case MCObjectFileInfo::IsELF: { 8142 const MCSymbolData &SD = 8143 getParser().getStreamer().getOrCreateSymbolData(Symbol); 8144 if (MCELF::GetType(SD) & (ELF::STT_FUNC << ELF_STT_Shift)) 8145 getParser().getStreamer().EmitThumbFunc(Symbol); 8146 break; 8147 } 8148 case MCObjectFileInfo::IsMachO: 8149 break; 8150 } 8151} 8152 8153/// parseDirectiveThumbFunc 8154/// ::= .thumbfunc symbol_name 8155bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 8156 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 8157 bool isMachO = MAI->hasSubsectionsViaSymbols(); 8158 8159 // Darwin asm has (optionally) function name after .thumb_func direction 8160 // ELF doesn't 8161 if (isMachO) { 8162 const AsmToken &Tok = Parser.getTok(); 8163 if (Tok.isNot(AsmToken::EndOfStatement)) { 8164 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) { 8165 Error(L, "unexpected token in .thumb_func directive"); 8166 return false; 8167 } 8168 8169 MCSymbol *Func = 8170 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier()); 8171 getParser().getStreamer().EmitThumbFunc(Func); 8172 Parser.Lex(); // Consume the identifier token. 8173 return false; 8174 } 8175 } 8176 8177 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8178 Error(L, "unexpected token in directive"); 8179 return false; 8180 } 8181 8182 NextSymbolIsThumb = true; 8183 return false; 8184} 8185 8186/// parseDirectiveSyntax 8187/// ::= .syntax unified | divided 8188bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 8189 const AsmToken &Tok = Parser.getTok(); 8190 if (Tok.isNot(AsmToken::Identifier)) { 8191 Error(L, "unexpected token in .syntax directive"); 8192 return false; 8193 } 8194 8195 StringRef Mode = Tok.getString(); 8196 if (Mode == "unified" || Mode == "UNIFIED") { 8197 Parser.Lex(); 8198 } else if (Mode == "divided" || Mode == "DIVIDED") { 8199 Error(L, "'.syntax divided' arm asssembly not supported"); 8200 return false; 8201 } else { 8202 Error(L, "unrecognized syntax mode in .syntax directive"); 8203 return false; 8204 } 8205 8206 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8207 Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8208 return false; 8209 } 8210 Parser.Lex(); 8211 8212 // TODO tell the MC streamer the mode 8213 // getParser().getStreamer().Emit???(); 8214 return false; 8215} 8216 8217/// parseDirectiveCode 8218/// ::= .code 16 | 32 8219bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 8220 const AsmToken &Tok = Parser.getTok(); 8221 if (Tok.isNot(AsmToken::Integer)) { 8222 Error(L, "unexpected token in .code directive"); 8223 return false; 8224 } 8225 int64_t Val = Parser.getTok().getIntVal(); 8226 if (Val != 16 && Val != 32) { 8227 Error(L, "invalid operand to .code directive"); 8228 return false; 8229 } 8230 Parser.Lex(); 8231 8232 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8233 Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8234 return false; 8235 } 8236 Parser.Lex(); 8237 8238 if (Val == 16) { 8239 if (!hasThumb()) { 8240 Error(L, "target does not support Thumb mode"); 8241 return false; 8242 } 8243 8244 if (!isThumb()) 8245 SwitchMode(); 8246 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 8247 } else { 8248 if (!hasARM()) { 8249 Error(L, "target does not support ARM mode"); 8250 return false; 8251 } 8252 8253 if (isThumb()) 8254 SwitchMode(); 8255 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 8256 } 8257 8258 return false; 8259} 8260 8261/// parseDirectiveReq 8262/// ::= name .req registername 8263bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 8264 Parser.Lex(); // Eat the '.req' token. 8265 unsigned Reg; 8266 SMLoc SRegLoc, ERegLoc; 8267 if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 8268 Parser.eatToEndOfStatement(); 8269 Error(SRegLoc, "register name expected"); 8270 return false; 8271 } 8272 8273 // Shouldn't be anything else. 8274 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 8275 Parser.eatToEndOfStatement(); 8276 Error(Parser.getTok().getLoc(), "unexpected input in .req directive."); 8277 return false; 8278 } 8279 8280 Parser.Lex(); // Consume the EndOfStatement 8281 8282 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) { 8283 Error(SRegLoc, "redefinition of '" + Name + "' does not match original."); 8284 return false; 8285 } 8286 8287 return false; 8288} 8289 8290/// parseDirectiveUneq 8291/// ::= .unreq registername 8292bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 8293 if (Parser.getTok().isNot(AsmToken::Identifier)) { 8294 Parser.eatToEndOfStatement(); 8295 Error(L, "unexpected input in .unreq directive."); 8296 return false; 8297 } 8298 RegisterReqs.erase(Parser.getTok().getIdentifier().lower()); 8299 Parser.Lex(); // Eat the identifier. 8300 return false; 8301} 8302 8303/// parseDirectiveArch 8304/// ::= .arch token 8305bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 8306 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 8307 bool isMachO = MAI->hasSubsectionsViaSymbols(); 8308 if (isMachO) { 8309 Error(L, ".arch directive not valid for Mach-O"); 8310 Parser.eatToEndOfStatement(); 8311 return false; 8312 } 8313 8314 StringRef Arch = getParser().parseStringToEndOfStatement().trim(); 8315 8316 unsigned ID = StringSwitch<unsigned>(Arch) 8317#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \ 8318 .Case(NAME, ARM::ID) 8319#define ARM_ARCH_ALIAS(NAME, ID) \ 8320 .Case(NAME, ARM::ID) 8321#include "MCTargetDesc/ARMArchName.def" 8322 .Default(ARM::INVALID_ARCH); 8323 8324 if (ID == ARM::INVALID_ARCH) { 8325 Error(L, "Unknown arch name"); 8326 return false; 8327 } 8328 8329 getTargetStreamer().emitArch(ID); 8330 return false; 8331} 8332 8333/// parseDirectiveEabiAttr 8334/// ::= .eabi_attribute int, int [, "str"] 8335/// ::= .eabi_attribute Tag_name, int [, "str"] 8336bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 8337 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 8338 bool isMachO = MAI->hasSubsectionsViaSymbols(); 8339 if (isMachO) { 8340 Error(L, ".eabi_attribute directive not valid for Mach-O"); 8341 Parser.eatToEndOfStatement(); 8342 return false; 8343 } 8344 8345 int64_t Tag; 8346 SMLoc TagLoc; 8347 TagLoc = Parser.getTok().getLoc(); 8348 if (Parser.getTok().is(AsmToken::Identifier)) { 8349 StringRef Name = Parser.getTok().getIdentifier(); 8350 Tag = ARMBuildAttrs::AttrTypeFromString(Name); 8351 if (Tag == -1) { 8352 Error(TagLoc, "attribute name not recognised: " + Name); 8353 Parser.eatToEndOfStatement(); 8354 return false; 8355 } 8356 Parser.Lex(); 8357 } else { 8358 const MCExpr *AttrExpr; 8359 8360 TagLoc = Parser.getTok().getLoc(); 8361 if (Parser.parseExpression(AttrExpr)) { 8362 Parser.eatToEndOfStatement(); 8363 return false; 8364 } 8365 8366 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr); 8367 if (!CE) { 8368 Error(TagLoc, "expected numeric constant"); 8369 Parser.eatToEndOfStatement(); 8370 return false; 8371 } 8372 8373 Tag = CE->getValue(); 8374 } 8375 8376 if (Parser.getTok().isNot(AsmToken::Comma)) { 8377 Error(Parser.getTok().getLoc(), "comma expected"); 8378 Parser.eatToEndOfStatement(); 8379 return false; 8380 } 8381 Parser.Lex(); // skip comma 8382 8383 StringRef StringValue = ""; 8384 bool IsStringValue = false; 8385 8386 int64_t IntegerValue = 0; 8387 bool IsIntegerValue = false; 8388 8389 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name) 8390 IsStringValue = true; 8391 else if (Tag == ARMBuildAttrs::compatibility) { 8392 IsStringValue = true; 8393 IsIntegerValue = true; 8394 } else if (Tag < 32 || Tag % 2 == 0) 8395 IsIntegerValue = true; 8396 else if (Tag % 2 == 1) 8397 IsStringValue = true; 8398 else 8399 llvm_unreachable("invalid tag type"); 8400 8401 if (IsIntegerValue) { 8402 const MCExpr *ValueExpr; 8403 SMLoc ValueExprLoc = Parser.getTok().getLoc(); 8404 if (Parser.parseExpression(ValueExpr)) { 8405 Parser.eatToEndOfStatement(); 8406 return false; 8407 } 8408 8409 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr); 8410 if (!CE) { 8411 Error(ValueExprLoc, "expected numeric constant"); 8412 Parser.eatToEndOfStatement(); 8413 return false; 8414 } 8415 8416 IntegerValue = CE->getValue(); 8417 } 8418 8419 if (Tag == ARMBuildAttrs::compatibility) { 8420 if (Parser.getTok().isNot(AsmToken::Comma)) 8421 IsStringValue = false; 8422 else 8423 Parser.Lex(); 8424 } 8425 8426 if (IsStringValue) { 8427 if (Parser.getTok().isNot(AsmToken::String)) { 8428 Error(Parser.getTok().getLoc(), "bad string constant"); 8429 Parser.eatToEndOfStatement(); 8430 return false; 8431 } 8432 8433 StringValue = Parser.getTok().getStringContents(); 8434 Parser.Lex(); 8435 } 8436 8437 if (IsIntegerValue && IsStringValue) { 8438 assert(Tag == ARMBuildAttrs::compatibility); 8439 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue); 8440 } else if (IsIntegerValue) 8441 getTargetStreamer().emitAttribute(Tag, IntegerValue); 8442 else if (IsStringValue) 8443 getTargetStreamer().emitTextAttribute(Tag, StringValue); 8444 return false; 8445} 8446 8447/// parseDirectiveCPU 8448/// ::= .cpu str 8449bool ARMAsmParser::parseDirectiveCPU(SMLoc L) { 8450 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 8451 bool isMachO = MAI->hasSubsectionsViaSymbols(); 8452 if (isMachO) { 8453 Error(L, ".cpu directive not valid for Mach-O"); 8454 Parser.eatToEndOfStatement(); 8455 return false; 8456 } 8457 8458 StringRef CPU = getParser().parseStringToEndOfStatement().trim(); 8459 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU); 8460 return false; 8461} 8462 8463/// parseDirectiveFPU 8464/// ::= .fpu str 8465bool ARMAsmParser::parseDirectiveFPU(SMLoc L) { 8466 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 8467 bool isMachO = MAI->hasSubsectionsViaSymbols(); 8468 if (isMachO) { 8469 Error(L, ".fpu directive not valid for Mach-O"); 8470 Parser.eatToEndOfStatement(); 8471 return false; 8472 } 8473 8474 StringRef FPU = getParser().parseStringToEndOfStatement().trim(); 8475 8476 unsigned ID = StringSwitch<unsigned>(FPU) 8477#define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID) 8478#include "ARMFPUName.def" 8479 .Default(ARM::INVALID_FPU); 8480 8481 if (ID == ARM::INVALID_FPU) { 8482 Error(L, "Unknown FPU name"); 8483 return false; 8484 } 8485 8486 getTargetStreamer().emitFPU(ID); 8487 return false; 8488} 8489 8490/// parseDirectiveFnStart 8491/// ::= .fnstart 8492bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { 8493 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 8494 bool isMachO = MAI->hasSubsectionsViaSymbols(); 8495 if (isMachO) { 8496 Error(L, ".fnstart directive not valid for Mach-O"); 8497 Parser.eatToEndOfStatement(); 8498 return false; 8499 } 8500 8501 if (UC.hasFnStart()) { 8502 Error(L, ".fnstart starts before the end of previous one"); 8503 UC.emitFnStartLocNotes(); 8504 return false; 8505 } 8506 8507 // Reset the unwind directives parser state 8508 UC.reset(); 8509 8510 getTargetStreamer().emitFnStart(); 8511 8512 UC.recordFnStart(L); 8513 return false; 8514} 8515 8516/// parseDirectiveFnEnd 8517/// ::= .fnend 8518bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { 8519 // Check the ordering of unwind directives 8520 if (!UC.hasFnStart()) { 8521 Error(L, ".fnstart must precede .fnend directive"); 8522 return false; 8523 } 8524 8525 // Reset the unwind directives parser state 8526 getTargetStreamer().emitFnEnd(); 8527 8528 UC.reset(); 8529 return false; 8530} 8531 8532/// parseDirectiveCantUnwind 8533/// ::= .cantunwind 8534bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { 8535 UC.recordCantUnwind(L); 8536 8537 // Check the ordering of unwind directives 8538 if (!UC.hasFnStart()) { 8539 Error(L, ".fnstart must precede .cantunwind directive"); 8540 return false; 8541 } 8542 if (UC.hasHandlerData()) { 8543 Error(L, ".cantunwind can't be used with .handlerdata directive"); 8544 UC.emitHandlerDataLocNotes(); 8545 return false; 8546 } 8547 if (UC.hasPersonality()) { 8548 Error(L, ".cantunwind can't be used with .personality directive"); 8549 UC.emitPersonalityLocNotes(); 8550 return false; 8551 } 8552 8553 getTargetStreamer().emitCantUnwind(); 8554 return false; 8555} 8556 8557/// parseDirectivePersonality 8558/// ::= .personality name 8559bool ARMAsmParser::parseDirectivePersonality(SMLoc L) { 8560 bool HasExistingPersonality = UC.hasPersonality(); 8561 8562 UC.recordPersonality(L); 8563 8564 // Check the ordering of unwind directives 8565 if (!UC.hasFnStart()) { 8566 Error(L, ".fnstart must precede .personality directive"); 8567 return false; 8568 } 8569 if (UC.cantUnwind()) { 8570 Error(L, ".personality can't be used with .cantunwind directive"); 8571 UC.emitCantUnwindLocNotes(); 8572 return false; 8573 } 8574 if (UC.hasHandlerData()) { 8575 Error(L, ".personality must precede .handlerdata directive"); 8576 UC.emitHandlerDataLocNotes(); 8577 return false; 8578 } 8579 if (HasExistingPersonality) { 8580 Parser.eatToEndOfStatement(); 8581 Error(L, "multiple personality directives"); 8582 UC.emitPersonalityLocNotes(); 8583 return false; 8584 } 8585 8586 // Parse the name of the personality routine 8587 if (Parser.getTok().isNot(AsmToken::Identifier)) { 8588 Parser.eatToEndOfStatement(); 8589 Error(L, "unexpected input in .personality directive."); 8590 return false; 8591 } 8592 StringRef Name(Parser.getTok().getIdentifier()); 8593 Parser.Lex(); 8594 8595 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name); 8596 getTargetStreamer().emitPersonality(PR); 8597 return false; 8598} 8599 8600/// parseDirectiveHandlerData 8601/// ::= .handlerdata 8602bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { 8603 UC.recordHandlerData(L); 8604 8605 // Check the ordering of unwind directives 8606 if (!UC.hasFnStart()) { 8607 Error(L, ".fnstart must precede .personality directive"); 8608 return false; 8609 } 8610 if (UC.cantUnwind()) { 8611 Error(L, ".handlerdata can't be used with .cantunwind directive"); 8612 UC.emitCantUnwindLocNotes(); 8613 return false; 8614 } 8615 8616 getTargetStreamer().emitHandlerData(); 8617 return false; 8618} 8619 8620/// parseDirectiveSetFP 8621/// ::= .setfp fpreg, spreg [, offset] 8622bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { 8623 // Check the ordering of unwind directives 8624 if (!UC.hasFnStart()) { 8625 Error(L, ".fnstart must precede .setfp directive"); 8626 return false; 8627 } 8628 if (UC.hasHandlerData()) { 8629 Error(L, ".setfp must precede .handlerdata directive"); 8630 return false; 8631 } 8632 8633 // Parse fpreg 8634 SMLoc FPRegLoc = Parser.getTok().getLoc(); 8635 int FPReg = tryParseRegister(); 8636 if (FPReg == -1) { 8637 Error(FPRegLoc, "frame pointer register expected"); 8638 return false; 8639 } 8640 8641 // Consume comma 8642 if (Parser.getTok().isNot(AsmToken::Comma)) { 8643 Error(Parser.getTok().getLoc(), "comma expected"); 8644 return false; 8645 } 8646 Parser.Lex(); // skip comma 8647 8648 // Parse spreg 8649 SMLoc SPRegLoc = Parser.getTok().getLoc(); 8650 int SPReg = tryParseRegister(); 8651 if (SPReg == -1) { 8652 Error(SPRegLoc, "stack pointer register expected"); 8653 return false; 8654 } 8655 8656 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) { 8657 Error(SPRegLoc, "register should be either $sp or the latest fp register"); 8658 return false; 8659 } 8660 8661 // Update the frame pointer register 8662 UC.saveFPReg(FPReg); 8663 8664 // Parse offset 8665 int64_t Offset = 0; 8666 if (Parser.getTok().is(AsmToken::Comma)) { 8667 Parser.Lex(); // skip comma 8668 8669 if (Parser.getTok().isNot(AsmToken::Hash) && 8670 Parser.getTok().isNot(AsmToken::Dollar)) { 8671 Error(Parser.getTok().getLoc(), "'#' expected"); 8672 return false; 8673 } 8674 Parser.Lex(); // skip hash token. 8675 8676 const MCExpr *OffsetExpr; 8677 SMLoc ExLoc = Parser.getTok().getLoc(); 8678 SMLoc EndLoc; 8679 if (getParser().parseExpression(OffsetExpr, EndLoc)) { 8680 Error(ExLoc, "malformed setfp offset"); 8681 return false; 8682 } 8683 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8684 if (!CE) { 8685 Error(ExLoc, "setfp offset must be an immediate"); 8686 return false; 8687 } 8688 8689 Offset = CE->getValue(); 8690 } 8691 8692 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg), 8693 static_cast<unsigned>(SPReg), Offset); 8694 return false; 8695} 8696 8697/// parseDirective 8698/// ::= .pad offset 8699bool ARMAsmParser::parseDirectivePad(SMLoc L) { 8700 // Check the ordering of unwind directives 8701 if (!UC.hasFnStart()) { 8702 Error(L, ".fnstart must precede .pad directive"); 8703 return false; 8704 } 8705 if (UC.hasHandlerData()) { 8706 Error(L, ".pad must precede .handlerdata directive"); 8707 return false; 8708 } 8709 8710 // Parse the offset 8711 if (Parser.getTok().isNot(AsmToken::Hash) && 8712 Parser.getTok().isNot(AsmToken::Dollar)) { 8713 Error(Parser.getTok().getLoc(), "'#' expected"); 8714 return false; 8715 } 8716 Parser.Lex(); // skip hash token. 8717 8718 const MCExpr *OffsetExpr; 8719 SMLoc ExLoc = Parser.getTok().getLoc(); 8720 SMLoc EndLoc; 8721 if (getParser().parseExpression(OffsetExpr, EndLoc)) { 8722 Error(ExLoc, "malformed pad offset"); 8723 return false; 8724 } 8725 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8726 if (!CE) { 8727 Error(ExLoc, "pad offset must be an immediate"); 8728 return false; 8729 } 8730 8731 getTargetStreamer().emitPad(CE->getValue()); 8732 return false; 8733} 8734 8735/// parseDirectiveRegSave 8736/// ::= .save { registers } 8737/// ::= .vsave { registers } 8738bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { 8739 // Check the ordering of unwind directives 8740 if (!UC.hasFnStart()) { 8741 Error(L, ".fnstart must precede .save or .vsave directives"); 8742 return false; 8743 } 8744 if (UC.hasHandlerData()) { 8745 Error(L, ".save or .vsave must precede .handlerdata directive"); 8746 return false; 8747 } 8748 8749 // RAII object to make sure parsed operands are deleted. 8750 struct CleanupObject { 8751 SmallVector<MCParsedAsmOperand *, 1> Operands; 8752 ~CleanupObject() { 8753 for (unsigned I = 0, E = Operands.size(); I != E; ++I) 8754 delete Operands[I]; 8755 } 8756 } CO; 8757 8758 // Parse the register list 8759 if (parseRegisterList(CO.Operands)) 8760 return false; 8761 ARMOperand *Op = (ARMOperand*)CO.Operands[0]; 8762 if (!IsVector && !Op->isRegList()) { 8763 Error(L, ".save expects GPR registers"); 8764 return false; 8765 } 8766 if (IsVector && !Op->isDPRRegList()) { 8767 Error(L, ".vsave expects DPR registers"); 8768 return false; 8769 } 8770 8771 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector); 8772 return false; 8773} 8774 8775/// parseDirectiveInst 8776/// ::= .inst opcode [, ...] 8777/// ::= .inst.n opcode [, ...] 8778/// ::= .inst.w opcode [, ...] 8779bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) { 8780 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 8781 bool isMachO = MAI->hasSubsectionsViaSymbols(); 8782 if (isMachO) { 8783 Error(Loc, ".inst directive not valid for Mach-O"); 8784 Parser.eatToEndOfStatement(); 8785 return false; 8786 } 8787 8788 int Width; 8789 8790 if (isThumb()) { 8791 switch (Suffix) { 8792 case 'n': 8793 Width = 2; 8794 break; 8795 case 'w': 8796 Width = 4; 8797 break; 8798 default: 8799 Parser.eatToEndOfStatement(); 8800 Error(Loc, "cannot determine Thumb instruction size, " 8801 "use inst.n/inst.w instead"); 8802 return false; 8803 } 8804 } else { 8805 if (Suffix) { 8806 Parser.eatToEndOfStatement(); 8807 Error(Loc, "width suffixes are invalid in ARM mode"); 8808 return false; 8809 } 8810 Width = 4; 8811 } 8812 8813 if (getLexer().is(AsmToken::EndOfStatement)) { 8814 Parser.eatToEndOfStatement(); 8815 Error(Loc, "expected expression following directive"); 8816 return false; 8817 } 8818 8819 for (;;) { 8820 const MCExpr *Expr; 8821 8822 if (getParser().parseExpression(Expr)) { 8823 Error(Loc, "expected expression"); 8824 return false; 8825 } 8826 8827 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr); 8828 if (!Value) { 8829 Error(Loc, "expected constant expression"); 8830 return false; 8831 } 8832 8833 switch (Width) { 8834 case 2: 8835 if (Value->getValue() > 0xffff) { 8836 Error(Loc, "inst.n operand is too big, use inst.w instead"); 8837 return false; 8838 } 8839 break; 8840 case 4: 8841 if (Value->getValue() > 0xffffffff) { 8842 Error(Loc, 8843 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big"); 8844 return false; 8845 } 8846 break; 8847 default: 8848 llvm_unreachable("only supported widths are 2 and 4"); 8849 } 8850 8851 getTargetStreamer().emitInst(Value->getValue(), Suffix); 8852 8853 if (getLexer().is(AsmToken::EndOfStatement)) 8854 break; 8855 8856 if (getLexer().isNot(AsmToken::Comma)) { 8857 Error(Loc, "unexpected token in directive"); 8858 return false; 8859 } 8860 8861 Parser.Lex(); 8862 } 8863 8864 Parser.Lex(); 8865 return false; 8866} 8867 8868/// parseDirectiveLtorg 8869/// ::= .ltorg | .pool 8870bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) { 8871 getTargetStreamer().emitCurrentConstantPool(); 8872 return false; 8873} 8874 8875bool ARMAsmParser::parseDirectiveEven(SMLoc L) { 8876 const MCSection *Section = getStreamer().getCurrentSection().first; 8877 8878 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8879 TokError("unexpected token in directive"); 8880 return false; 8881 } 8882 8883 if (!Section) { 8884 getStreamer().InitSections(); 8885 Section = getStreamer().getCurrentSection().first; 8886 } 8887 8888 assert(Section && "must have section to emit alignment"); 8889 if (Section->UseCodeAlign()) 8890 getStreamer().EmitCodeAlignment(2); 8891 else 8892 getStreamer().EmitValueToAlignment(2); 8893 8894 return false; 8895} 8896 8897/// parseDirectivePersonalityIndex 8898/// ::= .personalityindex index 8899bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) { 8900 bool HasExistingPersonality = UC.hasPersonality(); 8901 8902 UC.recordPersonalityIndex(L); 8903 8904 if (!UC.hasFnStart()) { 8905 Parser.eatToEndOfStatement(); 8906 Error(L, ".fnstart must precede .personalityindex directive"); 8907 return false; 8908 } 8909 if (UC.cantUnwind()) { 8910 Parser.eatToEndOfStatement(); 8911 Error(L, ".personalityindex cannot be used with .cantunwind"); 8912 UC.emitCantUnwindLocNotes(); 8913 return false; 8914 } 8915 if (UC.hasHandlerData()) { 8916 Parser.eatToEndOfStatement(); 8917 Error(L, ".personalityindex must precede .handlerdata directive"); 8918 UC.emitHandlerDataLocNotes(); 8919 return false; 8920 } 8921 if (HasExistingPersonality) { 8922 Parser.eatToEndOfStatement(); 8923 Error(L, "multiple personality directives"); 8924 UC.emitPersonalityLocNotes(); 8925 return false; 8926 } 8927 8928 const MCExpr *IndexExpression; 8929 SMLoc IndexLoc = Parser.getTok().getLoc(); 8930 if (Parser.parseExpression(IndexExpression)) { 8931 Parser.eatToEndOfStatement(); 8932 return false; 8933 } 8934 8935 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression); 8936 if (!CE) { 8937 Parser.eatToEndOfStatement(); 8938 Error(IndexLoc, "index must be a constant number"); 8939 return false; 8940 } 8941 if (CE->getValue() < 0 || 8942 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) { 8943 Parser.eatToEndOfStatement(); 8944 Error(IndexLoc, "personality routine index should be in range [0-3]"); 8945 return false; 8946 } 8947 8948 getTargetStreamer().emitPersonalityIndex(CE->getValue()); 8949 return false; 8950} 8951 8952/// parseDirectiveUnwindRaw 8953/// ::= .unwind_raw offset, opcode [, opcode...] 8954bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) { 8955 if (!UC.hasFnStart()) { 8956 Parser.eatToEndOfStatement(); 8957 Error(L, ".fnstart must precede .unwind_raw directives"); 8958 return false; 8959 } 8960 8961 int64_t StackOffset; 8962 8963 const MCExpr *OffsetExpr; 8964 SMLoc OffsetLoc = getLexer().getLoc(); 8965 if (getLexer().is(AsmToken::EndOfStatement) || 8966 getParser().parseExpression(OffsetExpr)) { 8967 Error(OffsetLoc, "expected expression"); 8968 Parser.eatToEndOfStatement(); 8969 return false; 8970 } 8971 8972 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8973 if (!CE) { 8974 Error(OffsetLoc, "offset must be a constant"); 8975 Parser.eatToEndOfStatement(); 8976 return false; 8977 } 8978 8979 StackOffset = CE->getValue(); 8980 8981 if (getLexer().isNot(AsmToken::Comma)) { 8982 Error(getLexer().getLoc(), "expected comma"); 8983 Parser.eatToEndOfStatement(); 8984 return false; 8985 } 8986 Parser.Lex(); 8987 8988 SmallVector<uint8_t, 16> Opcodes; 8989 for (;;) { 8990 const MCExpr *OE; 8991 8992 SMLoc OpcodeLoc = getLexer().getLoc(); 8993 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) { 8994 Error(OpcodeLoc, "expected opcode expression"); 8995 Parser.eatToEndOfStatement(); 8996 return false; 8997 } 8998 8999 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE); 9000 if (!OC) { 9001 Error(OpcodeLoc, "opcode value must be a constant"); 9002 Parser.eatToEndOfStatement(); 9003 return false; 9004 } 9005 9006 const int64_t Opcode = OC->getValue(); 9007 if (Opcode & ~0xff) { 9008 Error(OpcodeLoc, "invalid opcode"); 9009 Parser.eatToEndOfStatement(); 9010 return false; 9011 } 9012 9013 Opcodes.push_back(uint8_t(Opcode)); 9014 9015 if (getLexer().is(AsmToken::EndOfStatement)) 9016 break; 9017 9018 if (getLexer().isNot(AsmToken::Comma)) { 9019 Error(getLexer().getLoc(), "unexpected token in directive"); 9020 Parser.eatToEndOfStatement(); 9021 return false; 9022 } 9023 9024 Parser.Lex(); 9025 } 9026 9027 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes); 9028 9029 Parser.Lex(); 9030 return false; 9031} 9032 9033/// parseDirectiveTLSDescSeq 9034/// ::= .tlsdescseq tls-variable 9035bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) { 9036 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 9037 bool isMachO = MAI->hasSubsectionsViaSymbols(); 9038 if (isMachO) { 9039 Error(L, ".tlsdescseq directive not valid for Mach-O"); 9040 Parser.eatToEndOfStatement(); 9041 return false; 9042 } 9043 9044 if (getLexer().isNot(AsmToken::Identifier)) { 9045 TokError("expected variable after '.tlsdescseq' directive"); 9046 Parser.eatToEndOfStatement(); 9047 return false; 9048 } 9049 9050 const MCSymbolRefExpr *SRE = 9051 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(), 9052 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext()); 9053 Lex(); 9054 9055 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9056 Error(Parser.getTok().getLoc(), "unexpected token"); 9057 Parser.eatToEndOfStatement(); 9058 return false; 9059 } 9060 9061 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE); 9062 return false; 9063} 9064 9065/// parseDirectiveMovSP 9066/// ::= .movsp reg [, #offset] 9067bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) { 9068 if (!UC.hasFnStart()) { 9069 Parser.eatToEndOfStatement(); 9070 Error(L, ".fnstart must precede .movsp directives"); 9071 return false; 9072 } 9073 if (UC.getFPReg() != ARM::SP) { 9074 Parser.eatToEndOfStatement(); 9075 Error(L, "unexpected .movsp directive"); 9076 return false; 9077 } 9078 9079 SMLoc SPRegLoc = Parser.getTok().getLoc(); 9080 int SPReg = tryParseRegister(); 9081 if (SPReg == -1) { 9082 Parser.eatToEndOfStatement(); 9083 Error(SPRegLoc, "register expected"); 9084 return false; 9085 } 9086 9087 if (SPReg == ARM::SP || SPReg == ARM::PC) { 9088 Parser.eatToEndOfStatement(); 9089 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive"); 9090 return false; 9091 } 9092 9093 int64_t Offset = 0; 9094 if (Parser.getTok().is(AsmToken::Comma)) { 9095 Parser.Lex(); 9096 9097 if (Parser.getTok().isNot(AsmToken::Hash)) { 9098 Error(Parser.getTok().getLoc(), "expected #constant"); 9099 Parser.eatToEndOfStatement(); 9100 return false; 9101 } 9102 Parser.Lex(); 9103 9104 const MCExpr *OffsetExpr; 9105 SMLoc OffsetLoc = Parser.getTok().getLoc(); 9106 if (Parser.parseExpression(OffsetExpr)) { 9107 Parser.eatToEndOfStatement(); 9108 Error(OffsetLoc, "malformed offset expression"); 9109 return false; 9110 } 9111 9112 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9113 if (!CE) { 9114 Parser.eatToEndOfStatement(); 9115 Error(OffsetLoc, "offset must be an immediate constant"); 9116 return false; 9117 } 9118 9119 Offset = CE->getValue(); 9120 } 9121 9122 getTargetStreamer().emitMovSP(SPReg, Offset); 9123 UC.saveFPReg(SPReg); 9124 9125 return false; 9126} 9127 9128/// parseDirectiveObjectArch 9129/// ::= .object_arch name 9130bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) { 9131 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 9132 bool isMachO = MAI->hasSubsectionsViaSymbols(); 9133 if (isMachO) { 9134 Error(L, ".object_arch directive not valid for Mach-O"); 9135 Parser.eatToEndOfStatement(); 9136 return false; 9137 } 9138 9139 if (getLexer().isNot(AsmToken::Identifier)) { 9140 Error(getLexer().getLoc(), "unexpected token"); 9141 Parser.eatToEndOfStatement(); 9142 return false; 9143 } 9144 9145 StringRef Arch = Parser.getTok().getString(); 9146 SMLoc ArchLoc = Parser.getTok().getLoc(); 9147 getLexer().Lex(); 9148 9149 unsigned ID = StringSwitch<unsigned>(Arch) 9150#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \ 9151 .Case(NAME, ARM::ID) 9152#define ARM_ARCH_ALIAS(NAME, ID) \ 9153 .Case(NAME, ARM::ID) 9154#include "MCTargetDesc/ARMArchName.def" 9155#undef ARM_ARCH_NAME 9156#undef ARM_ARCH_ALIAS 9157 .Default(ARM::INVALID_ARCH); 9158 9159 if (ID == ARM::INVALID_ARCH) { 9160 Error(ArchLoc, "unknown architecture '" + Arch + "'"); 9161 Parser.eatToEndOfStatement(); 9162 return false; 9163 } 9164 9165 getTargetStreamer().emitObjectArch(ID); 9166 9167 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9168 Error(getLexer().getLoc(), "unexpected token"); 9169 Parser.eatToEndOfStatement(); 9170 } 9171 9172 return false; 9173} 9174 9175/// parseDirectiveAlign 9176/// ::= .align 9177bool ARMAsmParser::parseDirectiveAlign(SMLoc L) { 9178 // NOTE: if this is not the end of the statement, fall back to the target 9179 // agnostic handling for this directive which will correctly handle this. 9180 if (getLexer().isNot(AsmToken::EndOfStatement)) 9181 return true; 9182 9183 // '.align' is target specifically handled to mean 2**2 byte alignment. 9184 if (getStreamer().getCurrentSection().first->UseCodeAlign()) 9185 getStreamer().EmitCodeAlignment(4, 0); 9186 else 9187 getStreamer().EmitValueToAlignment(4, 0, 1, 0); 9188 9189 return false; 9190} 9191 9192/// parseDirectiveThumbSet 9193/// ::= .thumb_set name, value 9194bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) { 9195 StringRef Name; 9196 if (Parser.parseIdentifier(Name)) { 9197 TokError("expected identifier after '.thumb_set'"); 9198 Parser.eatToEndOfStatement(); 9199 return false; 9200 } 9201 9202 if (getLexer().isNot(AsmToken::Comma)) { 9203 TokError("expected comma after name '" + Name + "'"); 9204 Parser.eatToEndOfStatement(); 9205 return false; 9206 } 9207 Lex(); 9208 9209 const MCExpr *Value; 9210 if (Parser.parseExpression(Value)) { 9211 TokError("missing expression"); 9212 Parser.eatToEndOfStatement(); 9213 return false; 9214 } 9215 9216 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9217 TokError("unexpected token"); 9218 Parser.eatToEndOfStatement(); 9219 return false; 9220 } 9221 Lex(); 9222 9223 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name); 9224 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Value)) { 9225 MCSymbol *Sym = getContext().LookupSymbol(SRE->getSymbol().getName()); 9226 if (!Sym->isDefined()) { 9227 getStreamer().EmitSymbolAttribute(Sym, MCSA_Global); 9228 getStreamer().EmitAssignment(Alias, Value); 9229 return false; 9230 } 9231 9232 const MCObjectFileInfo::Environment Format = 9233 getContext().getObjectFileInfo()->getObjectFileType(); 9234 switch (Format) { 9235 case MCObjectFileInfo::IsCOFF: { 9236 char Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT; 9237 getStreamer().EmitCOFFSymbolType(Type); 9238 // .set values are always local in COFF 9239 getStreamer().EmitSymbolAttribute(Alias, MCSA_Local); 9240 break; 9241 } 9242 case MCObjectFileInfo::IsELF: 9243 getStreamer().EmitSymbolAttribute(Alias, MCSA_ELF_TypeFunction); 9244 break; 9245 case MCObjectFileInfo::IsMachO: 9246 break; 9247 } 9248 } 9249 9250 // FIXME: set the function as being a thumb function via the assembler 9251 getStreamer().EmitThumbFunc(Alias); 9252 getStreamer().EmitAssignment(Alias, Value); 9253 9254 return false; 9255} 9256 9257/// Force static initialization. 9258extern "C" void LLVMInitializeARMAsmParser() { 9259 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget); 9260 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget); 9261 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget); 9262 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget); 9263} 9264 9265#define GET_REGISTER_MATCHER 9266#define GET_SUBTARGET_FEATURE_NAME 9267#define GET_MATCHER_IMPLEMENTATION 9268#include "ARMGenAsmMatcher.inc" 9269 9270static const struct ExtMapEntry { 9271 const char *Extension; 9272 const unsigned ArchCheck; 9273 const uint64_t Features; 9274} Extensions[] = { 9275 { "crc", Feature_HasV8, ARM::FeatureCRC }, 9276 { "crypto", Feature_HasV8, 9277 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 }, 9278 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 }, 9279 { "idiv", Feature_HasV7 | Feature_IsNotMClass, 9280 ARM::FeatureHWDiv | ARM::FeatureHWDivARM }, 9281 // FIXME: iWMMXT not supported 9282 { "iwmmxt", Feature_None, 0 }, 9283 // FIXME: iWMMXT2 not supported 9284 { "iwmmxt2", Feature_None, 0 }, 9285 // FIXME: Maverick not supported 9286 { "maverick", Feature_None, 0 }, 9287 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP }, 9288 // FIXME: ARMv6-m OS Extensions feature not checked 9289 { "os", Feature_None, 0 }, 9290 // FIXME: Also available in ARMv6-K 9291 { "sec", Feature_HasV7, ARM::FeatureTrustZone }, 9292 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 }, 9293 // FIXME: Only available in A-class, isel not predicated 9294 { "virt", Feature_HasV7, ARM::FeatureVirtualization }, 9295 // FIXME: xscale not supported 9296 { "xscale", Feature_None, 0 }, 9297}; 9298 9299/// parseDirectiveArchExtension 9300/// ::= .arch_extension [no]feature 9301bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { 9302 if (getLexer().isNot(AsmToken::Identifier)) { 9303 Error(getLexer().getLoc(), "unexpected token"); 9304 Parser.eatToEndOfStatement(); 9305 return false; 9306 } 9307 9308 StringRef Extension = Parser.getTok().getString(); 9309 SMLoc ExtLoc = Parser.getTok().getLoc(); 9310 getLexer().Lex(); 9311 9312 bool EnableFeature = true; 9313 if (Extension.startswith_lower("no")) { 9314 EnableFeature = false; 9315 Extension = Extension.substr(2); 9316 } 9317 9318 for (unsigned EI = 0, EE = array_lengthof(Extensions); EI != EE; ++EI) { 9319 if (Extensions[EI].Extension != Extension) 9320 continue; 9321 9322 unsigned FB = getAvailableFeatures(); 9323 if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) { 9324 Error(ExtLoc, "architectural extension '" + Extension + "' is not " 9325 "allowed for the current base architecture"); 9326 return false; 9327 } 9328 9329 if (!Extensions[EI].Features) 9330 report_fatal_error("unsupported architectural extension: " + Extension); 9331 9332 if (EnableFeature) 9333 FB |= ComputeAvailableFeatures(Extensions[EI].Features); 9334 else 9335 FB &= ~ComputeAvailableFeatures(Extensions[EI].Features); 9336 9337 setAvailableFeatures(FB); 9338 return false; 9339 } 9340 9341 Error(ExtLoc, "unknown architectural extension: " + Extension); 9342 Parser.eatToEndOfStatement(); 9343 return false; 9344} 9345 9346// Define this matcher function after the auto-generated include so we 9347// have the match class enum definitions. 9348unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp, 9349 unsigned Kind) { 9350 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp); 9351 // If the kind is a token for a literal immediate, check if our asm 9352 // operand matches. This is for InstAliases which have a fixed-value 9353 // immediate in the syntax. 9354 switch (Kind) { 9355 default: break; 9356 case MCK__35_0: 9357 if (Op->isImm()) 9358 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm())) 9359 if (CE->getValue() == 0) 9360 return Match_Success; 9361 break; 9362 case MCK_ARMSOImm: 9363 if (Op->isImm()) { 9364 const MCExpr *SOExpr = Op->getImm(); 9365 int64_t Value; 9366 if (!SOExpr->EvaluateAsAbsolute(Value)) 9367 return Match_Success; 9368 assert((Value >= INT32_MIN && Value <= INT32_MAX) && 9369 "expression value must be representiable in 32 bits"); 9370 } 9371 break; 9372 case MCK_GPRPair: 9373 if (Op->isReg() && 9374 MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg())) 9375 return Match_Success; 9376 break; 9377 } 9378 return Match_InvalidOperand; 9379} 9380