ARMInstPrinter.cpp revision 4ee72398a15cd7b8e217bb3d34a4e9e0e72caca1 
1//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an ARM MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "asm-printer"
15#include "ARMInstPrinter.h"
16#include "MCTargetDesc/ARMAddressingModes.h"
17#include "MCTargetDesc/ARMBaseInfo.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/Support/raw_ostream.h"
24using namespace llvm;
25
26#include "ARMGenAsmWriter.inc"
27
28/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
29///
30/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31static unsigned translateShiftImm(unsigned imm) {
32  // lsr #32 and asr #32 exist, but should be encoded as a 0.
33  assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
34
35  if (imm == 0)
36    return 32;
37  return imm;
38}
39
40/// Prints the shift value with an immediate value.
41static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
42                          unsigned ShImm, bool UseMarkup) {
43  if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
44    return;
45  O << ", ";
46
47  assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
48  O << getShiftOpcStr(ShOpc);
49
50  if (ShOpc != ARM_AM::rrx) {
51    O << " ";
52    if (UseMarkup)
53      O << "<imm:";
54    O << "#" << translateShiftImm(ShImm);
55    if (UseMarkup)
56      O << ">";
57  }
58}
59
60ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
61                               const MCInstrInfo &MII,
62                               const MCRegisterInfo &MRI,
63                               const MCSubtargetInfo &STI) :
64  MCInstPrinter(MAI, MII, MRI) {
65  // Initialize the set of available features.
66  setAvailableFeatures(STI.getFeatureBits());
67}
68
69void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
70  OS << markup("<reg:")
71     << getRegisterName(RegNo)
72     << markup(">");
73}
74
75void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
76                               StringRef Annot) {
77  unsigned Opcode = MI->getOpcode();
78
79  // Check for HINT instructions w/ canonical names.
80  if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
81    switch (MI->getOperand(0).getImm()) {
82    case 0: O << "\tnop"; break;
83    case 1: O << "\tyield"; break;
84    case 2: O << "\twfe"; break;
85    case 3: O << "\twfi"; break;
86    case 4: O << "\tsev"; break;
87    default:
88      // Anything else should just print normally.
89      printInstruction(MI, O);
90      printAnnotation(O, Annot);
91      return;
92    }
93    printPredicateOperand(MI, 1, O);
94    if (Opcode == ARM::t2HINT)
95      O << ".w";
96    printAnnotation(O, Annot);
97    return;
98  }
99
100  // Check for MOVs and print canonical forms, instead.
101  if (Opcode == ARM::MOVsr) {
102    // FIXME: Thumb variants?
103    const MCOperand &Dst = MI->getOperand(0);
104    const MCOperand &MO1 = MI->getOperand(1);
105    const MCOperand &MO2 = MI->getOperand(2);
106    const MCOperand &MO3 = MI->getOperand(3);
107
108    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
109    printSBitModifierOperand(MI, 6, O);
110    printPredicateOperand(MI, 4, O);
111
112    O << '\t';
113    printRegName(O, Dst.getReg());
114    O << ", ";
115    printRegName(O, MO1.getReg());
116
117    O << ", ";
118    printRegName(O, MO2.getReg());
119    assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
120    printAnnotation(O, Annot);
121    return;
122  }
123
124  if (Opcode == ARM::MOVsi) {
125    // FIXME: Thumb variants?
126    const MCOperand &Dst = MI->getOperand(0);
127    const MCOperand &MO1 = MI->getOperand(1);
128    const MCOperand &MO2 = MI->getOperand(2);
129
130    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
131    printSBitModifierOperand(MI, 5, O);
132    printPredicateOperand(MI, 3, O);
133
134    O << '\t';
135    printRegName(O, Dst.getReg());
136    O << ", ";
137    printRegName(O, MO1.getReg());
138
139    if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
140      printAnnotation(O, Annot);
141      return;
142    }
143
144    O << ", "
145      << markup("<imm:")
146      << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
147      << markup(">");
148    printAnnotation(O, Annot);
149    return;
150  }
151
152
153  // A8.6.123 PUSH
154  if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
155      MI->getOperand(0).getReg() == ARM::SP &&
156      MI->getNumOperands() > 5) {
157    // Should only print PUSH if there are at least two registers in the list.
158    O << '\t' << "push";
159    printPredicateOperand(MI, 2, O);
160    if (Opcode == ARM::t2STMDB_UPD)
161      O << ".w";
162    O << '\t';
163    printRegisterList(MI, 4, O);
164    printAnnotation(O, Annot);
165    return;
166  }
167  if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
168      MI->getOperand(3).getImm() == -4) {
169    O << '\t' << "push";
170    printPredicateOperand(MI, 4, O);
171    O << "\t{";
172    printRegName(O, MI->getOperand(1).getReg());
173    O << "}";
174    printAnnotation(O, Annot);
175    return;
176  }
177
178  // A8.6.122 POP
179  if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
180      MI->getOperand(0).getReg() == ARM::SP &&
181      MI->getNumOperands() > 5) {
182    // Should only print POP if there are at least two registers in the list.
183    O << '\t' << "pop";
184    printPredicateOperand(MI, 2, O);
185    if (Opcode == ARM::t2LDMIA_UPD)
186      O << ".w";
187    O << '\t';
188    printRegisterList(MI, 4, O);
189    printAnnotation(O, Annot);
190    return;
191  }
192  if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
193      MI->getOperand(4).getImm() == 4) {
194    O << '\t' << "pop";
195    printPredicateOperand(MI, 5, O);
196    O << "\t{";
197    printRegName(O, MI->getOperand(0).getReg());
198    O << "}";
199    printAnnotation(O, Annot);
200    return;
201  }
202
203
204  // A8.6.355 VPUSH
205  if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
206      MI->getOperand(0).getReg() == ARM::SP) {
207    O << '\t' << "vpush";
208    printPredicateOperand(MI, 2, O);
209    O << '\t';
210    printRegisterList(MI, 4, O);
211    printAnnotation(O, Annot);
212    return;
213  }
214
215  // A8.6.354 VPOP
216  if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
217      MI->getOperand(0).getReg() == ARM::SP) {
218    O << '\t' << "vpop";
219    printPredicateOperand(MI, 2, O);
220    O << '\t';
221    printRegisterList(MI, 4, O);
222    printAnnotation(O, Annot);
223    return;
224  }
225
226  if (Opcode == ARM::tLDMIA) {
227    bool Writeback = true;
228    unsigned BaseReg = MI->getOperand(0).getReg();
229    for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
230      if (MI->getOperand(i).getReg() == BaseReg)
231        Writeback = false;
232    }
233
234    O << "\tldm";
235
236    printPredicateOperand(MI, 1, O);
237    O << '\t';
238    printRegName(O, BaseReg);
239    if (Writeback) O << "!";
240    O << ", ";
241    printRegisterList(MI, 3, O);
242    printAnnotation(O, Annot);
243    return;
244  }
245
246  // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
247  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
248  // a single GPRPair reg operand is used in the .td file to replace the two
249  // GPRs. However, when decoding them, the two GRPs cannot be automatically
250  // expressed as a GPRPair, so we have to manually merge them.
251  // FIXME: We would really like to be able to tablegen'erate this.
252  if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD) {
253    const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
254    bool isStore = Opcode == ARM::STREXD;
255    unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
256    if (MRC.contains(Reg)) {
257      MCInst NewMI;
258      MCOperand NewReg;
259      NewMI.setOpcode(Opcode);
260
261      if (isStore)
262        NewMI.addOperand(MI->getOperand(0));
263      NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
264        &MRI.getRegClass(ARM::GPRPairRegClassID)));
265      NewMI.addOperand(NewReg);
266
267      // Copy the rest operands into NewMI.
268      for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
269        NewMI.addOperand(MI->getOperand(i));
270      printInstruction(&NewMI, O);
271      return;
272    }
273  }
274
275  printInstruction(MI, O);
276  printAnnotation(O, Annot);
277}
278
279void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
280                                  raw_ostream &O) {
281  const MCOperand &Op = MI->getOperand(OpNo);
282  if (Op.isReg()) {
283    unsigned Reg = Op.getReg();
284    printRegName(O, Reg);
285  } else if (Op.isImm()) {
286    O << markup("<imm:")
287      << '#' << formatImm(Op.getImm())
288      << markup(">");
289  } else {
290    assert(Op.isExpr() && "unknown operand kind in printOperand");
291    // If a symbolic branch target was added as a constant expression then print
292    // that address in hex. And only print 32 unsigned bits for the address.
293    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
294    int64_t Address;
295    if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
296      O << "0x";
297      O.write_hex((uint32_t)Address);
298    }
299    else {
300      // Otherwise, just print the expression.
301      O << *Op.getExpr();
302    }
303  }
304}
305
306void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
307                                               raw_ostream &O) {
308  const MCOperand &MO1 = MI->getOperand(OpNum);
309  if (MO1.isExpr()) {
310    O << *MO1.getExpr();
311    return;
312  }
313
314  O << markup("<mem:") << "[pc, ";
315
316  int32_t OffImm = (int32_t)MO1.getImm();
317  bool isSub = OffImm < 0;
318
319  // Special value for #-0. All others are normal.
320  if (OffImm == INT32_MIN)
321    OffImm = 0;
322  if (isSub) {
323    O << markup("<imm:")
324      << "#-" << formatImm(-OffImm)
325      << markup(">");
326  } else {
327    O << markup("<imm:")
328      << "#" << formatImm(OffImm)
329      << markup(">");
330  }
331  O << "]" << markup(">");
332}
333
334// so_reg is a 4-operand unit corresponding to register forms of the A5.1
335// "Addressing Mode 1 - Data-processing operands" forms.  This includes:
336//    REG 0   0           - e.g. R5
337//    REG REG 0,SH_OPC    - e.g. R5, ROR R3
338//    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
339void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
340                                       raw_ostream &O) {
341  const MCOperand &MO1 = MI->getOperand(OpNum);
342  const MCOperand &MO2 = MI->getOperand(OpNum+1);
343  const MCOperand &MO3 = MI->getOperand(OpNum+2);
344
345  printRegName(O, MO1.getReg());
346
347  // Print the shift opc.
348  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
349  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
350  if (ShOpc == ARM_AM::rrx)
351    return;
352
353  O << ' ';
354  printRegName(O, MO2.getReg());
355  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
356}
357
358void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
359                                       raw_ostream &O) {
360  const MCOperand &MO1 = MI->getOperand(OpNum);
361  const MCOperand &MO2 = MI->getOperand(OpNum+1);
362
363  printRegName(O, MO1.getReg());
364
365  // Print the shift opc.
366  printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
367                   ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
368}
369
370
371//===--------------------------------------------------------------------===//
372// Addressing Mode #2
373//===--------------------------------------------------------------------===//
374
375void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
376                                                raw_ostream &O) {
377  const MCOperand &MO1 = MI->getOperand(Op);
378  const MCOperand &MO2 = MI->getOperand(Op+1);
379  const MCOperand &MO3 = MI->getOperand(Op+2);
380
381  O << markup("<mem:") << "[";
382  printRegName(O, MO1.getReg());
383
384  if (!MO2.getReg()) {
385    if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
386      O << ", "
387        << markup("<imm:")
388        << "#"
389        << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
390        << ARM_AM::getAM2Offset(MO3.getImm())
391        << markup(">");
392    }
393    O << "]" << markup(">");
394    return;
395  }
396
397  O << ", ";
398  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
399  printRegName(O, MO2.getReg());
400
401  printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
402                   ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
403  O << "]" << markup(">");
404}
405
406void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
407                                           raw_ostream &O) {
408  const MCOperand &MO1 = MI->getOperand(Op);
409  const MCOperand &MO2 = MI->getOperand(Op+1);
410  O << markup("<mem:") << "[";
411  printRegName(O, MO1.getReg());
412  O << ", ";
413  printRegName(O, MO2.getReg());
414  O << "]" << markup(">");
415}
416
417void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
418                                           raw_ostream &O) {
419  const MCOperand &MO1 = MI->getOperand(Op);
420  const MCOperand &MO2 = MI->getOperand(Op+1);
421  O << markup("<mem:") << "[";
422  printRegName(O, MO1.getReg());
423  O << ", ";
424  printRegName(O, MO2.getReg());
425  O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
426}
427
428void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
429                                           raw_ostream &O) {
430  const MCOperand &MO1 = MI->getOperand(Op);
431
432  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
433    printOperand(MI, Op, O);
434    return;
435  }
436
437#ifndef NDEBUG
438  const MCOperand &MO3 = MI->getOperand(Op+2);
439  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
440  assert(IdxMode != ARMII::IndexModePost &&
441         "Should be pre or offset index op");
442#endif
443
444  printAM2PreOrOffsetIndexOp(MI, Op, O);
445}
446
447void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
448                                                 unsigned OpNum,
449                                                 raw_ostream &O) {
450  const MCOperand &MO1 = MI->getOperand(OpNum);
451  const MCOperand &MO2 = MI->getOperand(OpNum+1);
452
453  if (!MO1.getReg()) {
454    unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
455    O << markup("<imm:")
456      << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
457      << ImmOffs
458      << markup(">");
459    return;
460  }
461
462  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
463  printRegName(O, MO1.getReg());
464
465  printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
466                   ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
467}
468
469//===--------------------------------------------------------------------===//
470// Addressing Mode #3
471//===--------------------------------------------------------------------===//
472
473void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
474                                         raw_ostream &O) {
475  const MCOperand &MO1 = MI->getOperand(Op);
476  const MCOperand &MO2 = MI->getOperand(Op+1);
477  const MCOperand &MO3 = MI->getOperand(Op+2);
478
479  O << markup("<mem:") << "[";
480  printRegName(O, MO1.getReg());
481  O << "], " << markup(">");
482
483  if (MO2.getReg()) {
484    O << (char)ARM_AM::getAM3Op(MO3.getImm());
485    printRegName(O, MO2.getReg());
486    return;
487  }
488
489  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
490  O << markup("<imm:")
491    << '#'
492    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
493    << ImmOffs
494    << markup(">");
495}
496
497void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
498                                                raw_ostream &O,
499                                                bool AlwaysPrintImm0) {
500  const MCOperand &MO1 = MI->getOperand(Op);
501  const MCOperand &MO2 = MI->getOperand(Op+1);
502  const MCOperand &MO3 = MI->getOperand(Op+2);
503
504  O << markup("<mem:") << '[';
505  printRegName(O, MO1.getReg());
506
507  if (MO2.getReg()) {
508    O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
509    printRegName(O, MO2.getReg());
510    O << ']' << markup(">");
511    return;
512  }
513
514  //If the op is sub we have to print the immediate even if it is 0
515  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
516  ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
517
518  if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
519    O << ", "
520      << markup("<imm:")
521      << "#"
522      << ARM_AM::getAddrOpcStr(op)
523      << ImmOffs
524      << markup(">");
525  }
526  O << ']' << markup(">");
527}
528
529template <bool AlwaysPrintImm0>
530void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
531                                           raw_ostream &O) {
532  const MCOperand &MO1 = MI->getOperand(Op);
533  if (!MO1.isReg()) {   //  For label symbolic references.
534    printOperand(MI, Op, O);
535    return;
536  }
537
538  const MCOperand &MO3 = MI->getOperand(Op+2);
539  unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
540
541  if (IdxMode == ARMII::IndexModePost) {
542    printAM3PostIndexOp(MI, Op, O);
543    return;
544  }
545  printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
546}
547
548void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
549                                                 unsigned OpNum,
550                                                 raw_ostream &O) {
551  const MCOperand &MO1 = MI->getOperand(OpNum);
552  const MCOperand &MO2 = MI->getOperand(OpNum+1);
553
554  if (MO1.getReg()) {
555    O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
556    printRegName(O, MO1.getReg());
557    return;
558  }
559
560  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
561  O << markup("<imm:")
562    << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
563    << markup(">");
564}
565
566void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
567                                             unsigned OpNum,
568                                             raw_ostream &O) {
569  const MCOperand &MO = MI->getOperand(OpNum);
570  unsigned Imm = MO.getImm();
571  O << markup("<imm:")
572    << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
573    << markup(">");
574}
575
576void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
577                                            raw_ostream &O) {
578  const MCOperand &MO1 = MI->getOperand(OpNum);
579  const MCOperand &MO2 = MI->getOperand(OpNum+1);
580
581  O << (MO2.getImm() ? "" : "-");
582  printRegName(O, MO1.getReg());
583}
584
585void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
586                                             unsigned OpNum,
587                                             raw_ostream &O) {
588  const MCOperand &MO = MI->getOperand(OpNum);
589  unsigned Imm = MO.getImm();
590  O << markup("<imm:")
591    << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
592    << markup(">");
593}
594
595
596void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
597                                           raw_ostream &O) {
598  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
599                                                 .getImm());
600  O << ARM_AM::getAMSubModeStr(Mode);
601}
602
603template <bool AlwaysPrintImm0>
604void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
605                                           raw_ostream &O) {
606  const MCOperand &MO1 = MI->getOperand(OpNum);
607  const MCOperand &MO2 = MI->getOperand(OpNum+1);
608
609  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
610    printOperand(MI, OpNum, O);
611    return;
612  }
613
614  O << markup("<mem:") << "[";
615  printRegName(O, MO1.getReg());
616
617  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
618  unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
619  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
620    O << ", "
621      << markup("<imm:")
622      << "#"
623      << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
624      << ImmOffs * 4
625      << markup(">");
626  }
627  O << "]" << markup(">");
628}
629
630void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
631                                           raw_ostream &O) {
632  const MCOperand &MO1 = MI->getOperand(OpNum);
633  const MCOperand &MO2 = MI->getOperand(OpNum+1);
634
635  O << markup("<mem:") << "[";
636  printRegName(O, MO1.getReg());
637  if (MO2.getImm()) {
638    O << ":" << (MO2.getImm() << 3);
639  }
640  O << "]" << markup(">");
641}
642
643void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
644                                           raw_ostream &O) {
645  const MCOperand &MO1 = MI->getOperand(OpNum);
646  O << markup("<mem:") << "[";
647  printRegName(O, MO1.getReg());
648  O << "]" << markup(">");
649}
650
651void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
652                                                 unsigned OpNum,
653                                                 raw_ostream &O) {
654  const MCOperand &MO = MI->getOperand(OpNum);
655  if (MO.getReg() == 0)
656    O << "!";
657  else {
658    O << ", ";
659    printRegName(O, MO.getReg());
660  }
661}
662
663void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
664                                                    unsigned OpNum,
665                                                    raw_ostream &O) {
666  const MCOperand &MO = MI->getOperand(OpNum);
667  uint32_t v = ~MO.getImm();
668  int32_t lsb = countTrailingZeros(v);
669  int32_t width = (32 - countLeadingZeros (v)) - lsb;
670  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
671  O << markup("<imm:") << '#' << lsb << markup(">")
672    << ", "
673    << markup("<imm:") << '#' << width << markup(">");
674}
675
676void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
677                                     raw_ostream &O) {
678  unsigned val = MI->getOperand(OpNum).getImm();
679  O << ARM_MB::MemBOptToString(val);
680}
681
682void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
683                                          raw_ostream &O) {
684  unsigned val = MI->getOperand(OpNum).getImm();
685  O << ARM_ISB::InstSyncBOptToString(val);
686}
687
688void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
689                                          raw_ostream &O) {
690  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
691  bool isASR = (ShiftOp & (1 << 5)) != 0;
692  unsigned Amt = ShiftOp & 0x1f;
693  if (isASR) {
694    O << ", asr "
695      << markup("<imm:")
696      << "#" << (Amt == 0 ? 32 : Amt)
697      << markup(">");
698  }
699  else if (Amt) {
700    O << ", lsl "
701      << markup("<imm:")
702      << "#" << Amt
703      << markup(">");
704  }
705}
706
707void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
708                                         raw_ostream &O) {
709  unsigned Imm = MI->getOperand(OpNum).getImm();
710  if (Imm == 0)
711    return;
712  assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
713  O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
714}
715
716void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
717                                         raw_ostream &O) {
718  unsigned Imm = MI->getOperand(OpNum).getImm();
719  // A shift amount of 32 is encoded as 0.
720  if (Imm == 0)
721    Imm = 32;
722  assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
723  O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
724}
725
726void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
727                                       raw_ostream &O) {
728  O << "{";
729  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
730    if (i != OpNum) O << ", ";
731    printRegName(O, MI->getOperand(i).getReg());
732  }
733  O << "}";
734}
735
736void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
737                                         raw_ostream &O) {
738  unsigned Reg = MI->getOperand(OpNum).getReg();
739  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
740  O << ", ";
741  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
742}
743
744
745void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
746                                        raw_ostream &O) {
747  const MCOperand &Op = MI->getOperand(OpNum);
748  if (Op.getImm())
749    O << "be";
750  else
751    O << "le";
752}
753
754void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
755                                  raw_ostream &O) {
756  const MCOperand &Op = MI->getOperand(OpNum);
757  O << ARM_PROC::IModToString(Op.getImm());
758}
759
760void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
761                                   raw_ostream &O) {
762  const MCOperand &Op = MI->getOperand(OpNum);
763  unsigned IFlags = Op.getImm();
764  for (int i=2; i >= 0; --i)
765    if (IFlags & (1 << i))
766      O << ARM_PROC::IFlagsToString(1 << i);
767
768  if (IFlags == 0)
769    O << "none";
770}
771
772void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
773                                         raw_ostream &O) {
774  const MCOperand &Op = MI->getOperand(OpNum);
775  unsigned SpecRegRBit = Op.getImm() >> 4;
776  unsigned Mask = Op.getImm() & 0xf;
777
778  if (getAvailableFeatures() & ARM::FeatureMClass) {
779    unsigned SYSm = Op.getImm();
780    unsigned Opcode = MI->getOpcode();
781    // For reads of the special registers ignore the "mask encoding" bits
782    // which are only for writes.
783    if (Opcode == ARM::t2MRS_M)
784      SYSm &= 0xff;
785    switch (SYSm) {
786    default: llvm_unreachable("Unexpected mask value!");
787    case     0:
788    case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr
789    case 0x400: O << "apsr_g"; return;
790    case 0xc00: O << "apsr_nzcvqg"; return;
791    case     1:
792    case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr
793    case 0x401: O << "iapsr_g"; return;
794    case 0xc01: O << "iapsr_nzcvqg"; return;
795    case     2:
796    case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr
797    case 0x402: O << "eapsr_g"; return;
798    case 0xc02: O << "eapsr_nzcvqg"; return;
799    case     3:
800    case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
801    case 0x403: O << "xpsr_g"; return;
802    case 0xc03: O << "xpsr_nzcvqg"; return;
803    case     5:
804    case 0x805: O << "ipsr"; return;
805    case     6:
806    case 0x806: O << "epsr"; return;
807    case     7:
808    case 0x807: O << "iepsr"; return;
809    case     8:
810    case 0x808: O << "msp"; return;
811    case     9:
812    case 0x809: O << "psp"; return;
813    case  0x10:
814    case 0x810: O << "primask"; return;
815    case  0x11:
816    case 0x811: O << "basepri"; return;
817    case  0x12:
818    case 0x812: O << "basepri_max"; return;
819    case  0x13:
820    case 0x813: O << "faultmask"; return;
821    case  0x14:
822    case 0x814: O << "control"; return;
823    }
824  }
825
826  // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
827  // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
828  if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
829    O << "APSR_";
830    switch (Mask) {
831    default: llvm_unreachable("Unexpected mask value!");
832    case 4:  O << "g"; return;
833    case 8:  O << "nzcvq"; return;
834    case 12: O << "nzcvqg"; return;
835    }
836  }
837
838  if (SpecRegRBit)
839    O << "SPSR";
840  else
841    O << "CPSR";
842
843  if (Mask) {
844    O << '_';
845    if (Mask & 8) O << 'f';
846    if (Mask & 4) O << 's';
847    if (Mask & 2) O << 'x';
848    if (Mask & 1) O << 'c';
849  }
850}
851
852void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
853                                           raw_ostream &O) {
854  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
855  // Handle the undefined 15 CC value here for printing so we don't abort().
856  if ((unsigned)CC == 15)
857    O << "<und>";
858  else if (CC != ARMCC::AL)
859    O << ARMCondCodeToString(CC);
860}
861
862void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
863                                                    unsigned OpNum,
864                                                    raw_ostream &O) {
865  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
866  O << ARMCondCodeToString(CC);
867}
868
869void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
870                                              raw_ostream &O) {
871  if (MI->getOperand(OpNum).getReg()) {
872    assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
873           "Expect ARM CPSR register!");
874    O << 's';
875  }
876}
877
878void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
879                                          raw_ostream &O) {
880  O << MI->getOperand(OpNum).getImm();
881}
882
883void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
884                                     raw_ostream &O) {
885  O << "p" << MI->getOperand(OpNum).getImm();
886}
887
888void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
889                                     raw_ostream &O) {
890  O << "c" << MI->getOperand(OpNum).getImm();
891}
892
893void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
894                                          raw_ostream &O) {
895  O << "{" << MI->getOperand(OpNum).getImm() << "}";
896}
897
898void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
899                                  raw_ostream &O) {
900  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
901}
902
903void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
904                                  raw_ostream &O) {
905  const MCOperand &MO = MI->getOperand(OpNum);
906
907  if (MO.isExpr()) {
908    O << *MO.getExpr();
909    return;
910  }
911
912  int32_t OffImm = (int32_t)MO.getImm();
913
914  O << markup("<imm:");
915  if (OffImm == INT32_MIN)
916    O << "#-0";
917  else if (OffImm < 0)
918    O << "#-" << -OffImm;
919  else
920    O << "#" << OffImm;
921  O << markup(">");
922}
923
924void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
925                                            raw_ostream &O) {
926  O << markup("<imm:")
927    << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
928    << markup(">");
929}
930
931void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
932                                     raw_ostream &O) {
933  unsigned Imm = MI->getOperand(OpNum).getImm();
934  O << markup("<imm:")
935    << "#" << formatImm((Imm == 0 ? 32 : Imm))
936    << markup(">");
937}
938
939void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
940                                      raw_ostream &O) {
941  // (3 - the number of trailing zeros) is the number of then / else.
942  unsigned Mask = MI->getOperand(OpNum).getImm();
943  unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
944  unsigned CondBit0 = Firstcond & 1;
945  unsigned NumTZ = countTrailingZeros(Mask);
946  assert(NumTZ <= 3 && "Invalid IT mask!");
947  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
948    bool T = ((Mask >> Pos) & 1) == CondBit0;
949    if (T)
950      O << 't';
951    else
952      O << 'e';
953  }
954}
955
956void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
957                                                 raw_ostream &O) {
958  const MCOperand &MO1 = MI->getOperand(Op);
959  const MCOperand &MO2 = MI->getOperand(Op + 1);
960
961  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
962    printOperand(MI, Op, O);
963    return;
964  }
965
966  O << markup("<mem:") << "[";
967  printRegName(O, MO1.getReg());
968  if (unsigned RegNum = MO2.getReg()) {
969    O << ", ";
970    printRegName(O, RegNum);
971  }
972  O << "]" << markup(">");
973}
974
975void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
976                                                    unsigned Op,
977                                                    raw_ostream &O,
978                                                    unsigned Scale) {
979  const MCOperand &MO1 = MI->getOperand(Op);
980  const MCOperand &MO2 = MI->getOperand(Op + 1);
981
982  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
983    printOperand(MI, Op, O);
984    return;
985  }
986
987  O << markup("<mem:") << "[";
988  printRegName(O, MO1.getReg());
989  if (unsigned ImmOffs = MO2.getImm()) {
990    O << ", "
991      << markup("<imm:")
992      << "#" << formatImm(ImmOffs * Scale)
993      << markup(">");
994  }
995  O << "]" << markup(">");
996}
997
998void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
999                                                     unsigned Op,
1000                                                     raw_ostream &O) {
1001  printThumbAddrModeImm5SOperand(MI, Op, O, 1);
1002}
1003
1004void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1005                                                     unsigned Op,
1006                                                     raw_ostream &O) {
1007  printThumbAddrModeImm5SOperand(MI, Op, O, 2);
1008}
1009
1010void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1011                                                     unsigned Op,
1012                                                     raw_ostream &O) {
1013  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1014}
1015
1016void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1017                                                 raw_ostream &O) {
1018  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1019}
1020
1021// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1022// register with shift forms.
1023// REG 0   0           - e.g. R5
1024// REG IMM, SH_OPC     - e.g. R5, LSL #3
1025void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1026                                      raw_ostream &O) {
1027  const MCOperand &MO1 = MI->getOperand(OpNum);
1028  const MCOperand &MO2 = MI->getOperand(OpNum+1);
1029
1030  unsigned Reg = MO1.getReg();
1031  printRegName(O, Reg);
1032
1033  // Print the shift opc.
1034  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1035  printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1036                   ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1037}
1038
1039template <bool AlwaysPrintImm0>
1040void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1041                                               raw_ostream &O) {
1042  const MCOperand &MO1 = MI->getOperand(OpNum);
1043  const MCOperand &MO2 = MI->getOperand(OpNum+1);
1044
1045  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
1046    printOperand(MI, OpNum, O);
1047    return;
1048  }
1049
1050  O << markup("<mem:") << "[";
1051  printRegName(O, MO1.getReg());
1052
1053  int32_t OffImm = (int32_t)MO2.getImm();
1054  bool isSub = OffImm < 0;
1055  // Special value for #-0. All others are normal.
1056  if (OffImm == INT32_MIN)
1057    OffImm = 0;
1058  if (isSub) {
1059    O << ", "
1060      << markup("<imm:")
1061      << "#-" << -OffImm
1062      << markup(">");
1063  }
1064  else if (AlwaysPrintImm0 || OffImm > 0) {
1065    O << ", "
1066      << markup("<imm:")
1067      << "#" << OffImm
1068      << markup(">");
1069  }
1070  O << "]" << markup(">");
1071}
1072
1073template<bool AlwaysPrintImm0>
1074void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1075                                                unsigned OpNum,
1076                                                raw_ostream &O) {
1077  const MCOperand &MO1 = MI->getOperand(OpNum);
1078  const MCOperand &MO2 = MI->getOperand(OpNum+1);
1079
1080  O << markup("<mem:") << "[";
1081  printRegName(O, MO1.getReg());
1082
1083  int32_t OffImm = (int32_t)MO2.getImm();
1084  bool isSub = OffImm < 0;
1085  // Don't print +0.
1086  if (OffImm == INT32_MIN)
1087    OffImm = 0;
1088  if (isSub) {
1089    O << ", "
1090      << markup("<imm:")
1091      << "#-" << -OffImm
1092      << markup(">");
1093  } else if (AlwaysPrintImm0 || OffImm > 0) {
1094    O << ", "
1095      << markup("<imm:")
1096      << "#" << OffImm
1097      << markup(">");
1098  }
1099  O << "]" << markup(">");
1100}
1101
1102template<bool AlwaysPrintImm0>
1103void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1104                                                  unsigned OpNum,
1105                                                  raw_ostream &O) {
1106  const MCOperand &MO1 = MI->getOperand(OpNum);
1107  const MCOperand &MO2 = MI->getOperand(OpNum+1);
1108
1109  if (!MO1.isReg()) {   //  For label symbolic references.
1110    printOperand(MI, OpNum, O);
1111    return;
1112  }
1113
1114  O << markup("<mem:") << "[";
1115  printRegName(O, MO1.getReg());
1116
1117  int32_t OffImm = (int32_t)MO2.getImm();
1118  bool isSub = OffImm < 0;
1119
1120  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1121
1122  // Don't print +0.
1123  if (OffImm == INT32_MIN)
1124    OffImm = 0;
1125  if (isSub) {
1126    O << ", "
1127      << markup("<imm:")
1128      << "#-" << -OffImm
1129      << markup(">");
1130  } else if (AlwaysPrintImm0 || OffImm > 0) {
1131    O << ", "
1132      << markup("<imm:")
1133      << "#" << OffImm
1134      << markup(">");
1135  }
1136  O << "]" << markup(">");
1137}
1138
1139void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
1140                                                       unsigned OpNum,
1141                                                       raw_ostream &O) {
1142  const MCOperand &MO1 = MI->getOperand(OpNum);
1143  const MCOperand &MO2 = MI->getOperand(OpNum+1);
1144
1145  O << markup("<mem:") << "[";
1146  printRegName(O, MO1.getReg());
1147  if (MO2.getImm()) {
1148    O << ", "
1149      << markup("<imm:")
1150      << "#" << formatImm(MO2.getImm() * 4)
1151      << markup(">");
1152  }
1153  O << "]" << markup(">");
1154}
1155
1156void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
1157                                                      unsigned OpNum,
1158                                                      raw_ostream &O) {
1159  const MCOperand &MO1 = MI->getOperand(OpNum);
1160  int32_t OffImm = (int32_t)MO1.getImm();
1161  O << ", " << markup("<imm:");
1162  if (OffImm == INT32_MIN)
1163    O << "#-0";
1164  else if (OffImm < 0)
1165    O << "#-" << -OffImm;
1166  else
1167    O << "#" << OffImm;
1168  O << markup(">");
1169}
1170
1171void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
1172                                                        unsigned OpNum,
1173                                                        raw_ostream &O) {
1174  const MCOperand &MO1 = MI->getOperand(OpNum);
1175  int32_t OffImm = (int32_t)MO1.getImm();
1176
1177  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1178
1179  // Don't print +0.
1180  if (OffImm != 0)
1181    O << ", ";
1182  if (OffImm != 0 && UseMarkup)
1183    O << "<imm:";
1184  if (OffImm == INT32_MIN)
1185    O << "#-0";
1186  else if (OffImm < 0)
1187    O << "#-" << -OffImm;
1188  else if (OffImm > 0)
1189    O << "#" << OffImm;
1190  if (OffImm != 0 && UseMarkup)
1191    O << ">";
1192}
1193
1194void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1195                                                 unsigned OpNum,
1196                                                 raw_ostream &O) {
1197  const MCOperand &MO1 = MI->getOperand(OpNum);
1198  const MCOperand &MO2 = MI->getOperand(OpNum+1);
1199  const MCOperand &MO3 = MI->getOperand(OpNum+2);
1200
1201  O << markup("<mem:") << "[";
1202  printRegName(O, MO1.getReg());
1203
1204  assert(MO2.getReg() && "Invalid so_reg load / store address!");
1205  O << ", ";
1206  printRegName(O, MO2.getReg());
1207
1208  unsigned ShAmt = MO3.getImm();
1209  if (ShAmt) {
1210    assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1211    O << ", lsl "
1212      << markup("<imm:")
1213      << "#" << ShAmt
1214      << markup(">");
1215  }
1216  O << "]" << markup(">");
1217}
1218
1219void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1220                                       raw_ostream &O) {
1221  const MCOperand &MO = MI->getOperand(OpNum);
1222  O << markup("<imm:")
1223    << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1224    << markup(">");
1225}
1226
1227void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1228                                            raw_ostream &O) {
1229  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1230  unsigned EltBits;
1231  uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1232  O << markup("<imm:")
1233    << "#0x";
1234  O.write_hex(Val);
1235  O << markup(">");
1236}
1237
1238void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1239                                            raw_ostream &O) {
1240  unsigned Imm = MI->getOperand(OpNum).getImm();
1241  O << markup("<imm:")
1242    << "#" << formatImm(Imm + 1)
1243    << markup(">");
1244}
1245
1246void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1247                                        raw_ostream &O) {
1248  unsigned Imm = MI->getOperand(OpNum).getImm();
1249  if (Imm == 0)
1250    return;
1251  O << ", ror "
1252    << markup("<imm:")
1253    << "#";
1254  switch (Imm) {
1255  default: assert (0 && "illegal ror immediate!");
1256  case 1: O << "8"; break;
1257  case 2: O << "16"; break;
1258  case 3: O << "24"; break;
1259  }
1260  O << markup(">");
1261}
1262
1263void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1264                                  raw_ostream &O) {
1265  O << markup("<imm:")
1266    << "#" << 16 - MI->getOperand(OpNum).getImm()
1267    << markup(">");
1268}
1269
1270void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1271                                  raw_ostream &O) {
1272  O << markup("<imm:")
1273    << "#" << 32 - MI->getOperand(OpNum).getImm()
1274    << markup(">");
1275}
1276
1277void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1278                                      raw_ostream &O) {
1279  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1280}
1281
1282void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1283                                        raw_ostream &O) {
1284  O << "{";
1285  printRegName(O, MI->getOperand(OpNum).getReg());
1286  O << "}";
1287}
1288
1289void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1290                                          raw_ostream &O) {
1291  unsigned Reg = MI->getOperand(OpNum).getReg();
1292  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1293  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1294  O << "{";
1295  printRegName(O, Reg0);
1296  O << ", ";
1297  printRegName(O, Reg1);
1298  O << "}";
1299}
1300
1301void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1302                                              unsigned OpNum,
1303                                              raw_ostream &O) {
1304  unsigned Reg = MI->getOperand(OpNum).getReg();
1305  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1306  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1307  O << "{";
1308  printRegName(O, Reg0);
1309  O << ", ";
1310  printRegName(O, Reg1);
1311  O << "}";
1312}
1313
1314void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1315                                          raw_ostream &O) {
1316  // Normally, it's not safe to use register enum values directly with
1317  // addition to get the next register, but for VFP registers, the
1318  // sort order is guaranteed because they're all of the form D<n>.
1319  O << "{";
1320  printRegName(O, MI->getOperand(OpNum).getReg());
1321  O << ", ";
1322  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1323  O << ", ";
1324  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1325  O << "}";
1326}
1327
1328void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1329                                         raw_ostream &O) {
1330  // Normally, it's not safe to use register enum values directly with
1331  // addition to get the next register, but for VFP registers, the
1332  // sort order is guaranteed because they're all of the form D<n>.
1333  O << "{";
1334  printRegName(O, MI->getOperand(OpNum).getReg());
1335  O << ", ";
1336  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1337  O << ", ";
1338  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1339  O << ", ";
1340  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1341  O << "}";
1342}
1343
1344void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1345                                                unsigned OpNum,
1346                                                raw_ostream &O) {
1347  O << "{";
1348  printRegName(O, MI->getOperand(OpNum).getReg());
1349  O << "[]}";
1350}
1351
1352void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1353                                                unsigned OpNum,
1354                                                raw_ostream &O) {
1355  unsigned Reg = MI->getOperand(OpNum).getReg();
1356  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1357  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1358  O << "{";
1359  printRegName(O, Reg0);
1360  O << "[], ";
1361  printRegName(O, Reg1);
1362  O << "[]}";
1363}
1364
1365void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1366                                                  unsigned OpNum,
1367                                                  raw_ostream &O) {
1368  // Normally, it's not safe to use register enum values directly with
1369  // addition to get the next register, but for VFP registers, the
1370  // sort order is guaranteed because they're all of the form D<n>.
1371  O << "{";
1372  printRegName(O, MI->getOperand(OpNum).getReg());
1373  O << "[], ";
1374  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1375  O << "[], ";
1376  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1377  O << "[]}";
1378}
1379
1380void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1381                                                  unsigned OpNum,
1382                                                  raw_ostream &O) {
1383  // Normally, it's not safe to use register enum values directly with
1384  // addition to get the next register, but for VFP registers, the
1385  // sort order is guaranteed because they're all of the form D<n>.
1386  O << "{";
1387  printRegName(O, MI->getOperand(OpNum).getReg());
1388  O << "[], ";
1389  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1390  O << "[], ";
1391  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1392  O << "[], ";
1393  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1394  O << "[]}";
1395}
1396
1397void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1398                                                      unsigned OpNum,
1399                                                      raw_ostream &O) {
1400  unsigned Reg = MI->getOperand(OpNum).getReg();
1401  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1402  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1403  O << "{";
1404  printRegName(O, Reg0);
1405  O << "[], ";
1406  printRegName(O, Reg1);
1407  O << "[]}";
1408}
1409
1410void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1411                                                        unsigned OpNum,
1412                                                        raw_ostream &O) {
1413  // Normally, it's not safe to use register enum values directly with
1414  // addition to get the next register, but for VFP registers, the
1415  // sort order is guaranteed because they're all of the form D<n>.
1416  O << "{";
1417  printRegName(O, MI->getOperand(OpNum).getReg());
1418  O  << "[], ";
1419  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1420  O << "[], ";
1421  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1422  O << "[]}";
1423}
1424
1425void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1426                                                       unsigned OpNum,
1427                                                       raw_ostream &O) {
1428  // Normally, it's not safe to use register enum values directly with
1429  // addition to get the next register, but for VFP registers, the
1430  // sort order is guaranteed because they're all of the form D<n>.
1431  O << "{";
1432  printRegName(O, MI->getOperand(OpNum).getReg());
1433  O << "[], ";
1434  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1435  O << "[], ";
1436  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1437  O << "[], ";
1438  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1439  O << "[]}";
1440}
1441
1442void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1443                                                unsigned OpNum,
1444                                                raw_ostream &O) {
1445  // Normally, it's not safe to use register enum values directly with
1446  // addition to get the next register, but for VFP registers, the
1447  // sort order is guaranteed because they're all of the form D<n>.
1448  O << "{";
1449  printRegName(O, MI->getOperand(OpNum).getReg());
1450  O << ", ";
1451  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1452  O << ", ";
1453  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1454  O << "}";
1455}
1456
1457void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1458                                                unsigned OpNum,
1459                                                raw_ostream &O) {
1460  // Normally, it's not safe to use register enum values directly with
1461  // addition to get the next register, but for VFP registers, the
1462  // sort order is guaranteed because they're all of the form D<n>.
1463  O << "{";
1464  printRegName(O, MI->getOperand(OpNum).getReg());
1465  O << ", ";
1466  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1467  O << ", ";
1468  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1469  O << ", ";
1470  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1471  O << "}";
1472}
1473