178a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===// 278a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// 378a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// The LLVM Compiler Infrastructure 478a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// 578a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// This file is distributed under the University of Illinois Open Source 678a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// License. See LICENSE.TXT for details. 778a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// 878a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng//===----------------------------------------------------------------------===// 978a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// 1078a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// This file provides ARM specific target descriptions. 1178a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// 1278a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng//===----------------------------------------------------------------------===// 1378a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng 1478a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng#ifndef ARMMCTARGETDESC_H 1578a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng#define ARMMCTARGETDESC_H 1678a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng 17883d99f70ba41d334adc9fef321804a2f88c4468NAKAMURA Takumi#include "llvm/Support/DataTypes.h" 1894ca42ff0407d71bacc41de4032d8dbe6358d33dEvan Cheng#include <string> 1994ca42ff0407d71bacc41de4032d8dbe6358d33dEvan Cheng 2078a9f138ae95458bf6d922f38706eed045691d5aEvan Chengnamespace llvm { 21320296a4cfe414ce59f406b8a5ce15272f563103Rafael Espindolaclass formatted_raw_ostream; 2278c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5cEvan Chengclass MCAsmBackend; 23be74029f44c32efc09274a16cbff588ad10dc5eaEvan Chengclass MCCodeEmitter; 24be74029f44c32efc09274a16cbff588ad10dc5eaEvan Chengclass MCContext; 25be74029f44c32efc09274a16cbff588ad10dc5eaEvan Chengclass MCInstrInfo; 26320296a4cfe414ce59f406b8a5ce15272f563103Rafael Espindolaclass MCInstPrinter; 27be74029f44c32efc09274a16cbff588ad10dc5eaEvan Chengclass MCObjectWriter; 28918f55fe239f00651e396be841f2b3b6e242f98dJim Grosbachclass MCRegisterInfo; 29ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Chengclass MCSubtargetInfo; 30320296a4cfe414ce59f406b8a5ce15272f563103Rafael Espindolaclass MCStreamer; 312c94d0faa0e1c268893d5e04dc77e8a35889db00Ahmed Bougachaclass MCRelocationInfo; 3294ca42ff0407d71bacc41de4032d8dbe6358d33dEvan Chengclass StringRef; 33be74029f44c32efc09274a16cbff588ad10dc5eaEvan Chengclass Target; 34be74029f44c32efc09274a16cbff588ad10dc5eaEvan Chengclass raw_ostream; 3578a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng 3636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesextern Target TheARMLETarget, TheThumbLETarget; 3736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesextern Target TheARMBETarget, TheThumbBETarget; 3894ca42ff0407d71bacc41de4032d8dbe6358d33dEvan Cheng 3994ca42ff0407d71bacc41de4032d8dbe6358d33dEvan Chengnamespace ARM_MC { 40e67a4163f5d2ad8e42a3aa0ccdaa27d85f6d5be4Evan Cheng std::string ParseARMTriple(StringRef TT, StringRef CPU); 41ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng 42ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance. 43ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng /// This is exposed so Asm parser, etc. do not need to go through 44ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng /// TargetRegistry. 45ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, 46ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng StringRef FS); 4794ca42ff0407d71bacc41de4032d8dbe6358d33dEvan Cheng} 4894ca42ff0407d71bacc41de4032d8dbe6358d33dEvan Cheng 49320296a4cfe414ce59f406b8a5ce15272f563103Rafael EspindolaMCStreamer *createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, 50dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool isVerboseAsm, bool useDwarfDirectory, 51320296a4cfe414ce59f406b8a5ce15272f563103Rafael Espindola MCInstPrinter *InstPrint, MCCodeEmitter *CE, 52320296a4cfe414ce59f406b8a5ce15272f563103Rafael Espindola MCAsmBackend *TAB, bool ShowInst); 53320296a4cfe414ce59f406b8a5ce15272f563103Rafael Espindola 54cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen HinesMCStreamer *createARMNullStreamer(MCContext &Ctx); 55cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 5636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen HinesMCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 5736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const MCRegisterInfo &MRI, 5836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const MCSubtargetInfo &STI, 5936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MCContext &Ctx); 6036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 6136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen HinesMCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 6236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const MCRegisterInfo &MRI, 6336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const MCSubtargetInfo &STI, 6436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MCContext &Ctx); 65be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng 66c3cee57f7d20f69a84fd88464ed8cf050e63c7adBill WendlingMCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, 6736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines StringRef TT, StringRef CPU, 6836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool IsLittleEndian); 6936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 7036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen HinesMCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 7136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines StringRef TT, StringRef CPU); 7236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 7336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen HinesMCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 74c3cee57f7d20f69a84fd88464ed8cf050e63c7adBill Wendling StringRef TT, StringRef CPU); 75be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng 7636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen HinesMCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 7736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines StringRef TT, StringRef CPU); 7836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 7936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen HinesMCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 8036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines StringRef TT, StringRef CPU); 8136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 82dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines/// createARMWinCOFFStreamer - Construct a PE/COFF machine code streamer which 83dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines/// will generate a PE/COFF object file. 84dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen HinesMCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB, 85dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MCCodeEmitter &Emitter, raw_ostream &OS); 86dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 8769bbda03918a18bd4477bb254d51346ee3033567Rafael Espindola/// createARMELFObjectWriter - Construct an ELF Mach-O object writer. 8869bbda03918a18bd4477bb254d51346ee3033567Rafael EspindolaMCObjectWriter *createARMELFObjectWriter(raw_ostream &OS, 8936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines uint8_t OSABI, 9036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool IsLittleEndian); 9169bbda03918a18bd4477bb254d51346ee3033567Rafael Espindola 92be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng/// createARMMachObjectWriter - Construct an ARM Mach-O object writer. 93be74029f44c32efc09274a16cbff588ad10dc5eaEvan ChengMCObjectWriter *createARMMachObjectWriter(raw_ostream &OS, 94be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng bool Is64Bit, 95be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng uint32_t CPUType, 96be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng uint32_t CPUSubtype); 97be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng 98dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines/// createARMWinCOFFObjectWriter - Construct an ARM PE/COFF object writer. 99dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen HinesMCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit); 1002c94d0faa0e1c268893d5e04dc77e8a35889db00Ahmed Bougacha 1012c94d0faa0e1c268893d5e04dc77e8a35889db00Ahmed Bougacha/// createARMMachORelocationInfo - Construct ARM Mach-O relocation info. 1022c94d0faa0e1c268893d5e04dc77e8a35889db00Ahmed BougachaMCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx); 10378a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng} // End llvm namespace 10478a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng 10578a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// Defines symbolic names for ARM registers. This defines a mapping from 10678a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// register name to register number. 10778a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// 10878a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng#define GET_REGINFO_ENUM 10978a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng#include "ARMGenRegisterInfo.inc" 11078a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng 11178a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// Defines symbolic names for the ARM instructions. 11278a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng// 11378a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng#define GET_INSTRINFO_ENUM 11478a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng#include "ARMGenInstrInfo.inc" 11578a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng 116c60f9b752381baa6c4b80c0739034660f1748c84Evan Cheng#define GET_SUBTARGETINFO_ENUM 117c60f9b752381baa6c4b80c0739034660f1748c84Evan Cheng#include "ARMGenSubtargetInfo.inc" 118c60f9b752381baa6c4b80c0739034660f1748c84Evan Cheng 11978a9f138ae95458bf6d922f38706eed045691d5aEvan Cheng#endif 120