ARMMCTargetDesc.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides ARM specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMMCTARGETDESC_H
15#define ARMMCTARGETDESC_H
16
17#include "llvm/Support/DataTypes.h"
18#include <string>
19
20namespace llvm {
21class formatted_raw_ostream;
22class MCAsmBackend;
23class MCCodeEmitter;
24class MCContext;
25class MCInstrInfo;
26class MCInstPrinter;
27class MCObjectWriter;
28class MCRegisterInfo;
29class MCSubtargetInfo;
30class MCStreamer;
31class MCRelocationInfo;
32class StringRef;
33class Target;
34class raw_ostream;
35
36extern Target TheARMLETarget, TheThumbLETarget;
37extern Target TheARMBETarget, TheThumbBETarget;
38
39namespace ARM_MC {
40  std::string ParseARMTriple(StringRef TT, StringRef CPU);
41
42  /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
43  /// This is exposed so Asm parser, etc. do not need to go through
44  /// TargetRegistry.
45  MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
46                                            StringRef FS);
47}
48
49MCStreamer *createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
50                                bool isVerboseAsm, bool useCFI,
51                                bool useDwarfDirectory,
52                                MCInstPrinter *InstPrint, MCCodeEmitter *CE,
53                                MCAsmBackend *TAB, bool ShowInst);
54
55MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
56                                        const MCRegisterInfo &MRI,
57                                        const MCSubtargetInfo &STI,
58                                        MCContext &Ctx);
59
60MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
61                                        const MCRegisterInfo &MRI,
62                                        const MCSubtargetInfo &STI,
63                                        MCContext &Ctx);
64
65MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
66                                  StringRef TT, StringRef CPU,
67                                  bool IsLittleEndian);
68
69MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
70                                  StringRef TT, StringRef CPU);
71
72MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
73                                  StringRef TT, StringRef CPU);
74
75MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
76                                      StringRef TT, StringRef CPU);
77
78MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
79                                      StringRef TT, StringRef CPU);
80
81/// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
82MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
83                                         uint8_t OSABI,
84                                         bool IsLittleEndian);
85
86/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
87MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
88                                          bool Is64Bit,
89                                          uint32_t CPUType,
90                                          uint32_t CPUSubtype);
91
92
93/// createARMMachORelocationInfo - Construct ARM Mach-O relocation info.
94MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
95} // End llvm namespace
96
97// Defines symbolic names for ARM registers.  This defines a mapping from
98// register name to register number.
99//
100#define GET_REGINFO_ENUM
101#include "ARMGenRegisterInfo.inc"
102
103// Defines symbolic names for the ARM instructions.
104//
105#define GET_INSTRINFO_ENUM
106#include "ARMGenInstrInfo.inc"
107
108#define GET_SUBTARGETINFO_ENUM
109#include "ARMGenSubtargetInfo.inc"
110
111#endif
112