ARMMCTargetDesc.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides ARM specific target descriptions. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef ARMMCTARGETDESC_H 15#define ARMMCTARGETDESC_H 16 17#include "llvm/Support/DataTypes.h" 18#include <string> 19 20namespace llvm { 21class formatted_raw_ostream; 22class MCAsmBackend; 23class MCCodeEmitter; 24class MCContext; 25class MCInstrInfo; 26class MCInstPrinter; 27class MCObjectWriter; 28class MCRegisterInfo; 29class MCSubtargetInfo; 30class MCStreamer; 31class MCRelocationInfo; 32class StringRef; 33class Target; 34class raw_ostream; 35 36extern Target TheARMLETarget, TheThumbLETarget; 37extern Target TheARMBETarget, TheThumbBETarget; 38 39namespace ARM_MC { 40 std::string ParseARMTriple(StringRef TT, StringRef CPU); 41 42 /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance. 43 /// This is exposed so Asm parser, etc. do not need to go through 44 /// TargetRegistry. 45 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, 46 StringRef FS); 47} 48 49MCStreamer *createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, 50 bool isVerboseAsm, bool useDwarfDirectory, 51 MCInstPrinter *InstPrint, MCCodeEmitter *CE, 52 MCAsmBackend *TAB, bool ShowInst); 53 54MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 55 const MCRegisterInfo &MRI, 56 const MCSubtargetInfo &STI, 57 MCContext &Ctx); 58 59MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 60 const MCRegisterInfo &MRI, 61 const MCSubtargetInfo &STI, 62 MCContext &Ctx); 63 64MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, 65 StringRef TT, StringRef CPU, 66 bool IsLittleEndian); 67 68MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 69 StringRef TT, StringRef CPU); 70 71MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 72 StringRef TT, StringRef CPU); 73 74MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 75 StringRef TT, StringRef CPU); 76 77MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 78 StringRef TT, StringRef CPU); 79 80/// createARMWinCOFFStreamer - Construct a PE/COFF machine code streamer which 81/// will generate a PE/COFF object file. 82MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB, 83 MCCodeEmitter &Emitter, raw_ostream &OS); 84 85/// createARMELFObjectWriter - Construct an ELF Mach-O object writer. 86MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS, 87 uint8_t OSABI, 88 bool IsLittleEndian); 89 90/// createARMMachObjectWriter - Construct an ARM Mach-O object writer. 91MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS, 92 bool Is64Bit, 93 uint32_t CPUType, 94 uint32_t CPUSubtype); 95 96/// createARMWinCOFFObjectWriter - Construct an ARM PE/COFF object writer. 97MCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit); 98 99/// createARMMachORelocationInfo - Construct ARM Mach-O relocation info. 100MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx); 101} // End llvm namespace 102 103// Defines symbolic names for ARM registers. This defines a mapping from 104// register name to register number. 105// 106#define GET_REGINFO_ENUM 107#include "ARMGenRegisterInfo.inc" 108 109// Defines symbolic names for the ARM instructions. 110// 111#define GET_INSTRINFO_ENUM 112#include "ARMGenInstrInfo.inc" 113 114#define GET_SUBTARGETINFO_ENUM 115#include "ARMGenSubtargetInfo.inc" 116 117#endif 118