Thumb1FrameLowering.cpp revision 1b26fdbf1f01e90b803cc035b6b932cd95c76830
1cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)//===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===// 2cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// 3cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// The LLVM Compiler Infrastructure 4cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// 5cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 6cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// License. See LICENSE.TXT for details. 7116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch// 8cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)//===----------------------------------------------------------------------===// 95f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 1046d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles)// This file contains the Thumb1 implementation of TargetFrameLowering class. 11116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch// 12cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)//===----------------------------------------------------------------------===// 13cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 14cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "Thumb1FrameLowering.h" 15116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch#include "ARMMachineFunctionInfo.h" 16116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch#include "llvm/CodeGen/MachineFrameInfo.h" 17116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch#include "llvm/CodeGen/MachineFunction.h" 18116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch#include "llvm/CodeGen/MachineInstrBuilder.h" 191320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci#include "llvm/CodeGen/MachineRegisterInfo.h" 201320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci 21116680a4aac90f2aa7413d9095a592090648e557Ben Murdochusing namespace llvm; 22116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 23116680a4aac90f2aa7413d9095a592090648e557Ben Murdochbool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{ 24116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const MachineFrameInfo *FFI = MF.getFrameInfo(); 25116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch unsigned CFSize = FFI->getMaxCallFrameSize(); 26116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // It's not always a good idea to include the call frame as part of the 27116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // stack frame. ARM (especially Thumb) has small immediate offset to 28116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // address the stack frame. So a large call frame can cause poor codegen 29116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // and may even makes it impossible to scavenge a register. 30116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 31116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch return false; 32116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 33116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch return !MF.getFrameInfo()->hasVarSizedObjects(); 34116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch} 35116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 36116680a4aac90f2aa7413d9095a592090648e557Ben Murdochstatic void 37116680a4aac90f2aa7413d9095a592090648e557Ben MurdochemitSPUpdate(MachineBasicBlock &MBB, 38116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch MachineBasicBlock::iterator &MBBI, 39116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const TargetInstrInfo &TII, DebugLoc dl, 40116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const Thumb1RegisterInfo &MRI, 41116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) { 42116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, 43116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch MRI, MIFlags); 44116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch} 45116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 46116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 47116680a4aac90f2aa7413d9095a592090648e557Ben Murdochvoid Thumb1FrameLowering:: 48116680a4aac90f2aa7413d9095a592090648e557Ben MurdocheliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 49116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch MachineBasicBlock::iterator I) const { 50116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const Thumb1InstrInfo &TII = 51116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo()); 52116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const Thumb1RegisterInfo *RegInfo = 53116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo()); 54116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch if (!hasReservedCallFrame(MF)) { 55116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // If we have alloca, convert as follows: 56116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // ADJCALLSTACKDOWN -> sub, sp, sp, amount 57116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // ADJCALLSTACKUP -> add, sp, sp, amount 58116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch MachineInstr *Old = I; 59116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch DebugLoc dl = Old->getDebugLoc(); 60116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch unsigned Amount = Old->getOperand(0).getImm(); 61116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch if (Amount != 0) { 62116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // We need to keep the stack aligned properly. To do this, we round the 63116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // amount of space needed for the outgoing arguments up to the next 64116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // alignment boundary. 65116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch unsigned Align = getStackAlignment(); 66116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch Amount = (Amount+Align-1)/Align*Align; 67116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 68116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // Replace the pseudo instruction with a new instruction... 69116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch unsigned Opc = Old->getOpcode(); 70116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 71116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); 72116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch } else { 73116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 74116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); 75116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch } 76116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch } 77116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch } 78116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch MBB.erase(I); 79116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch} 80116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 81116680a4aac90f2aa7413d9095a592090648e557Ben Murdochvoid Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const { 8246d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) MachineBasicBlock &MBB = MF.front(); 8346d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) MachineBasicBlock::iterator MBBI = MBB.begin(); 8446d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) MachineFrameInfo *MFI = MF.getFrameInfo(); 85116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 86116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const Thumb1RegisterInfo *RegInfo = 87116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo()); 8846d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) const Thumb1InstrInfo &TII = 8946d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo()); 9046d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) 91116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 92116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align); 93116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch unsigned NumBytes = MFI->getStackSize(); 94116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 95116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 96116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch unsigned FramePtr = RegInfo->getFrameRegister(MF); 9746d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) unsigned BasePtr = RegInfo->getBaseRegister(); 9846d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) 9946d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 10046d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) NumBytes = (NumBytes + 3) & ~3; 10146d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) MFI->setStackSize(NumBytes); 10246d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) 1035f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) // Determine the sizes of each callee-save spill areas and record which frame 1045f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) // belongs to which callee-save spill areas. 1055f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1065f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) int FramePtrSpillFI = 0; 1075f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 108116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch if (ArgRegsSaveSize) 109116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, 1101320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci MachineInstr::FrameSetup); 1111320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci 1121320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (!AFI->hasStackFrame()) { 1131320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (NumBytes != 0) 1141320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 1151320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci MachineInstr::FrameSetup); 1161320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci return; 1171320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci } 118116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 119116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 120116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch unsigned Reg = CSI[i].getReg(); 121116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch int FI = CSI[i].getFrameIdx(); 122116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch switch (Reg) { 123116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch case ARM::R4: 124116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch case ARM::R5: 125116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch case ARM::R6: 126116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch case ARM::R7: 127116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch case ARM::LR: 128116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch if (Reg == FramePtr) 129116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch FramePtrSpillFI = FI; 130116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch GPRCS1Size += 4; 131116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch break; 132116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch case ARM::R8: 133116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch case ARM::R9: 134116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch case ARM::R10: 135116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch case ARM::R11: 136116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch if (Reg == FramePtr) 137cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) FramePtrSpillFI = FI; 138cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (STI.isTargetIOS()) 1395f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) GPRCS2Size += 4; 1401320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci else 1411320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci GPRCS1Size += 4; 1421320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci break; 1435f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) default: 1445f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) DPRCSSize += 8; 145cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 146 } 147 148 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { 149 ++MBBI; 150 if (MBBI != MBB.end()) 151 dl = MBBI->getDebugLoc(); 152 } 153 154 // Determine starting offsets of spill areas. 155 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 156 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 157 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 158 bool HasFP = hasFP(MF); 159 if (HasFP) 160 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 161 NumBytes); 162 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 163 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 164 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 165 NumBytes = DPRCSOffset; 166 167 int FramePtrOffsetInBlock = 0; 168 if (tryFoldSPUpdateIntoPushPop(MF, prior(MBBI), NumBytes)) { 169 FramePtrOffsetInBlock = NumBytes; 170 NumBytes = 0; 171 } 172 173 // Adjust FP so it point to the stack slot that contains the previous FP. 174 if (HasFP) { 175 FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI) + GPRCS1Size; 176 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) 177 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4) 178 .setMIFlags(MachineInstr::FrameSetup)); 179 if (NumBytes > 508) 180 // If offset is > 508 then sp cannot be adjusted in a single instruction, 181 // try restoring from fp instead. 182 AFI->setShouldRestoreSPFromFP(true); 183 } 184 185 if (NumBytes) 186 // Insert it after all the callee-save spills. 187 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 188 MachineInstr::FrameSetup); 189 190 if (STI.isTargetELF() && HasFP) 191 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 192 AFI->getFramePtrSpillOffset()); 193 194 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 195 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 196 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 197 198 // Thumb1 does not currently support dynamic stack realignment. Report a 199 // fatal error rather then silently generate bad code. 200 if (RegInfo->needsStackRealignment(MF)) 201 report_fatal_error("Dynamic stack realignment not supported for thumb1."); 202 203 // If we need a base pointer, set it up here. It's whatever the value 204 // of the stack pointer is at this point. Any variable size objects 205 // will be allocated after this, so we can still use the base pointer 206 // to reference locals. 207 if (RegInfo->hasBasePointer(MF)) 208 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) 209 .addReg(ARM::SP)); 210 211 // If the frame has variable sized objects then the epilogue must restore 212 // the sp from fp. We can assume there's an FP here since hasFP already 213 // checks for hasVarSizedObjects. 214 if (MFI->hasVarSizedObjects()) 215 AFI->setShouldRestoreSPFromFP(true); 216} 217 218static bool isCSRestore(MachineInstr *MI, const uint16_t *CSRegs) { 219 if (MI->getOpcode() == ARM::tLDRspi && 220 MI->getOperand(1).isFI() && 221 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)) 222 return true; 223 else if (MI->getOpcode() == ARM::tPOP) { 224 // The first two operands are predicates. The last two are 225 // imp-def and imp-use of SP. Check everything in between. 226 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i) 227 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) 228 return false; 229 return true; 230 } 231 return false; 232} 233 234void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, 235 MachineBasicBlock &MBB) const { 236 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 237 assert((MBBI->getOpcode() == ARM::tBX_RET || 238 MBBI->getOpcode() == ARM::tPOP_RET) && 239 "Can only insert epilog into returning blocks"); 240 DebugLoc dl = MBBI->getDebugLoc(); 241 MachineFrameInfo *MFI = MF.getFrameInfo(); 242 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 243 const Thumb1RegisterInfo *RegInfo = 244 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo()); 245 const Thumb1InstrInfo &TII = 246 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo()); 247 248 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 249 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align); 250 int NumBytes = (int)MFI->getStackSize(); 251 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(); 252 unsigned FramePtr = RegInfo->getFrameRegister(MF); 253 254 if (!AFI->hasStackFrame()) { 255 if (NumBytes != 0) 256 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes); 257 } else { 258 // Unwind MBBI to point to first LDR / VLDRD. 259 if (MBBI != MBB.begin()) { 260 do 261 --MBBI; 262 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 263 if (!isCSRestore(MBBI, CSRegs)) 264 ++MBBI; 265 } 266 267 // Move SP to start of FP callee save spill area. 268 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 269 AFI->getGPRCalleeSavedArea2Size() + 270 AFI->getDPRCalleeSavedAreaSize()); 271 272 if (AFI->shouldRestoreSPFromFP()) { 273 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 274 // Reset SP based on frame pointer only if the stack frame extends beyond 275 // frame pointer stack slot, the target is ELF and the function has FP, or 276 // the target uses var sized objects. 277 if (NumBytes) { 278 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && 279 "No scratch register to restore SP from FP!"); 280 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 281 TII, *RegInfo); 282 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 283 ARM::SP) 284 .addReg(ARM::R4)); 285 } else 286 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 287 ARM::SP) 288 .addReg(FramePtr)); 289 } else { 290 if (MBBI->getOpcode() == ARM::tBX_RET && 291 &MBB.front() != MBBI && 292 prior(MBBI)->getOpcode() == ARM::tPOP) { 293 MachineBasicBlock::iterator PMBBI = prior(MBBI); 294 if (!tryFoldSPUpdateIntoPushPop(MF, PMBBI, NumBytes)) 295 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes); 296 } else if (!tryFoldSPUpdateIntoPushPop(MF, MBBI, NumBytes)) 297 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes); 298 } 299 } 300 301 if (ArgRegsSaveSize) { 302 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore 303 // to LR, and we can't pop the value directly to the PC since 304 // we need to update the SP after popping the value. Therefore, we 305 // pop the old LR into R3 as a temporary. 306 307 // Move back past the callee-saved register restoration 308 while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs)) 309 ++MBBI; 310 // Epilogue for vararg functions: pop LR to R3 and branch off it. 311 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))) 312 .addReg(ARM::R3, RegState::Define); 313 314 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize); 315 316 MachineInstrBuilder MIB = 317 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)) 318 .addReg(ARM::R3, RegState::Kill); 319 AddDefaultPred(MIB); 320 MIB.copyImplicitOps(&*MBBI); 321 // erase the old tBX_RET instruction 322 MBB.erase(MBBI); 323 } 324} 325 326bool Thumb1FrameLowering:: 327spillCalleeSavedRegisters(MachineBasicBlock &MBB, 328 MachineBasicBlock::iterator MI, 329 const std::vector<CalleeSavedInfo> &CSI, 330 const TargetRegisterInfo *TRI) const { 331 if (CSI.empty()) 332 return false; 333 334 DebugLoc DL; 335 MachineFunction &MF = *MBB.getParent(); 336 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 337 338 if (MI != MBB.end()) DL = MI->getDebugLoc(); 339 340 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); 341 AddDefaultPred(MIB); 342 for (unsigned i = CSI.size(); i != 0; --i) { 343 unsigned Reg = CSI[i-1].getReg(); 344 bool isKill = true; 345 346 // Add the callee-saved register as live-in unless it's LR and 347 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress 348 // then it's already added to the function and entry block live-in sets. 349 if (Reg == ARM::LR) { 350 MachineFunction &MF = *MBB.getParent(); 351 if (MF.getFrameInfo()->isReturnAddressTaken() && 352 MF.getRegInfo().isLiveIn(Reg)) 353 isKill = false; 354 } 355 356 if (isKill) 357 MBB.addLiveIn(Reg); 358 359 MIB.addReg(Reg, getKillRegState(isKill)); 360 } 361 MIB.setMIFlags(MachineInstr::FrameSetup); 362 return true; 363} 364 365bool Thumb1FrameLowering:: 366restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 367 MachineBasicBlock::iterator MI, 368 const std::vector<CalleeSavedInfo> &CSI, 369 const TargetRegisterInfo *TRI) const { 370 if (CSI.empty()) 371 return false; 372 373 MachineFunction &MF = *MBB.getParent(); 374 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 375 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 376 377 bool isVarArg = AFI->getArgRegsSaveSize() > 0; 378 DebugLoc DL = MI->getDebugLoc(); 379 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); 380 AddDefaultPred(MIB); 381 382 bool NumRegs = false; 383 for (unsigned i = CSI.size(); i != 0; --i) { 384 unsigned Reg = CSI[i-1].getReg(); 385 if (Reg == ARM::LR) { 386 // Special epilogue for vararg functions. See emitEpilogue 387 if (isVarArg) 388 continue; 389 Reg = ARM::PC; 390 (*MIB).setDesc(TII.get(ARM::tPOP_RET)); 391 MIB.copyImplicitOps(&*MI); 392 MI = MBB.erase(MI); 393 } 394 MIB.addReg(Reg, getDefRegState(true)); 395 NumRegs = true; 396 } 397 398 // It's illegal to emit pop instruction without operands. 399 if (NumRegs) 400 MBB.insert(MI, &*MIB); 401 else 402 MF.DeleteMachineInstr(MIB); 403 404 return true; 405} 406