Thumb1RegisterInfo.cpp revision 452d952c5ca697114235f88dd4ea9f0e83354ac8 
1//===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMSubtarget.h"
20#include "Thumb1InstrInfo.h"
21#include "Thumb1RegisterInfo.h"
22#include "llvm/Constants.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
25#include "llvm/LLVMContext.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/Target/TargetFrameInfo.h"
33#include "llvm/Target/TargetMachine.h"
34#include "llvm/ADT/BitVector.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39
40namespace llvm {
41extern cl::opt<bool> ReuseFrameIndexVals;
42}
43
44using namespace llvm;
45
46Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
47                                       const ARMSubtarget &sti)
48  : ARMBaseRegisterInfo(tii, sti) {
49}
50
51/// emitLoadConstPool - Emits a load from constpool to materialize the
52/// specified immediate.
53void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
54                                           MachineBasicBlock::iterator &MBBI,
55                                           DebugLoc dl,
56                                           unsigned DestReg, unsigned SubIdx,
57                                           int Val,
58                                           ARMCC::CondCodes Pred,
59                                           unsigned PredReg) const {
60  MachineFunction &MF = *MBB.getParent();
61  MachineConstantPool *ConstantPool = MF.getConstantPool();
62  const Constant *C = ConstantInt::get(
63          Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
64  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
65
66  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
67          .addReg(DestReg, getDefRegState(true), SubIdx)
68          .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
69}
70
71const TargetRegisterClass*
72Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
73  if (isARMLowRegister(Reg))
74    return ARM::tGPRRegisterClass;
75  switch (Reg) {
76   default:
77    break;
78   case ARM::R8:  case ARM::R9:  case ARM::R10:  case ARM::R11:
79   case ARM::R12: case ARM::SP:  case ARM::LR:   case ARM::PC:
80    return ARM::GPRRegisterClass;
81  }
82
83  return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
84}
85
86bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
87  const MachineFrameInfo *FFI = MF.getFrameInfo();
88  unsigned CFSize = FFI->getMaxCallFrameSize();
89  // It's not always a good idea to include the call frame as part of the
90  // stack frame. ARM (especially Thumb) has small immediate offset to
91  // address the stack frame. So a large call frame can cause poor codegen
92  // and may even makes it impossible to scavenge a register.
93  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
94    return false;
95
96  return !MF.getFrameInfo()->hasVarSizedObjects();
97}
98
99
100/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
101/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
102/// in a register using mov / mvn sequences or load the immediate from a
103/// constpool entry.
104static
105void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
106                              MachineBasicBlock::iterator &MBBI,
107                              unsigned DestReg, unsigned BaseReg,
108                              int NumBytes, bool CanChangeCC,
109                              const TargetInstrInfo &TII,
110                              const Thumb1RegisterInfo& MRI,
111                              DebugLoc dl) {
112    MachineFunction &MF = *MBB.getParent();
113    bool isHigh = !isARMLowRegister(DestReg) ||
114                  (BaseReg != 0 && !isARMLowRegister(BaseReg));
115    bool isSub = false;
116    // Subtract doesn't have high register version. Load the negative value
117    // if either base or dest register is a high register. Also, if do not
118    // issue sub as part of the sequence if condition register is to be
119    // preserved.
120    if (NumBytes < 0 && !isHigh && CanChangeCC) {
121      isSub = true;
122      NumBytes = -NumBytes;
123    }
124    unsigned LdReg = DestReg;
125    if (DestReg == ARM::SP) {
126      assert(BaseReg == ARM::SP && "Unexpected!");
127      LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
128    }
129
130    if (NumBytes <= 255 && NumBytes >= 0)
131      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
132        .addImm(NumBytes);
133    else if (NumBytes < 0 && NumBytes >= -255) {
134      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
135        .addImm(NumBytes);
136      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
137        .addReg(LdReg, RegState::Kill);
138    } else
139      MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
140
141    // Emit add / sub.
142    int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
143    MachineInstrBuilder MIB =
144      BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
145    if (Opc != ARM::tADDhirr)
146      MIB = AddDefaultT1CC(MIB);
147    if (DestReg == ARM::SP || isSub)
148      MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
149    else
150      MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
151    AddDefaultPred(MIB);
152}
153
154/// calcNumMI - Returns the number of instructions required to materialize
155/// the specific add / sub r, c instruction.
156static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
157                          unsigned NumBits, unsigned Scale) {
158  unsigned NumMIs = 0;
159  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
160
161  if (Opc == ARM::tADDrSPi) {
162    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
163    Bytes -= ThisVal;
164    NumMIs++;
165    NumBits = 8;
166    Scale = 1;  // Followed by a number of tADDi8.
167    Chunk = ((1 << NumBits) - 1) * Scale;
168  }
169
170  NumMIs += Bytes / Chunk;
171  if ((Bytes % Chunk) != 0)
172    NumMIs++;
173  if (ExtraOpc)
174    NumMIs++;
175  return NumMIs;
176}
177
178/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
179/// a destreg = basereg + immediate in Thumb code.
180static
181void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
182                               MachineBasicBlock::iterator &MBBI,
183                               unsigned DestReg, unsigned BaseReg,
184                               int NumBytes, const TargetInstrInfo &TII,
185                               const Thumb1RegisterInfo& MRI,
186                               DebugLoc dl) {
187  bool isSub = NumBytes < 0;
188  unsigned Bytes = (unsigned)NumBytes;
189  if (isSub) Bytes = -NumBytes;
190  bool isMul4 = (Bytes & 3) == 0;
191  bool isTwoAddr = false;
192  bool DstNotEqBase = false;
193  unsigned NumBits = 1;
194  unsigned Scale = 1;
195  int Opc = 0;
196  int ExtraOpc = 0;
197  bool NeedCC = false;
198  bool NeedPred = false;
199
200  if (DestReg == BaseReg && BaseReg == ARM::SP) {
201    assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
202    NumBits = 7;
203    Scale = 4;
204    Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
205    isTwoAddr = true;
206  } else if (!isSub && BaseReg == ARM::SP) {
207    // r1 = add sp, 403
208    // =>
209    // r1 = add sp, 100 * 4
210    // r1 = add r1, 3
211    if (!isMul4) {
212      Bytes &= ~3;
213      ExtraOpc = ARM::tADDi3;
214    }
215    NumBits = 8;
216    Scale = 4;
217    Opc = ARM::tADDrSPi;
218  } else {
219    // sp = sub sp, c
220    // r1 = sub sp, c
221    // r8 = sub sp, c
222    if (DestReg != BaseReg)
223      DstNotEqBase = true;
224    NumBits = 8;
225    if (DestReg == ARM::SP) {
226      Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
227      assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
228      NumBits = 7;
229      Scale = 4;
230    } else {
231      Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
232      NumBits = 8;
233      NeedPred = NeedCC = true;
234    }
235    isTwoAddr = true;
236  }
237
238  unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
239  unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
240  if (NumMIs > Threshold) {
241    // This will expand into too many instructions. Load the immediate from a
242    // constpool entry.
243    emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
244                             MRI, dl);
245    return;
246  }
247
248  if (DstNotEqBase) {
249    if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
250      // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
251      unsigned Chunk = (1 << 3) - 1;
252      unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
253      Bytes -= ThisVal;
254      const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
255      const MachineInstrBuilder MIB =
256        AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
257      AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
258    } else {
259      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
260        .addReg(BaseReg, RegState::Kill);
261    }
262    BaseReg = DestReg;
263  }
264
265  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
266  while (Bytes) {
267    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
268    Bytes -= ThisVal;
269    ThisVal /= Scale;
270    // Build the new tADD / tSUB.
271    if (isTwoAddr) {
272      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
273      if (NeedCC)
274        MIB = AddDefaultT1CC(MIB);
275      MIB .addReg(DestReg).addImm(ThisVal);
276      if (NeedPred)
277        MIB = AddDefaultPred(MIB);
278    }
279    else {
280      bool isKill = BaseReg != ARM::SP;
281      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
282      if (NeedCC)
283        MIB = AddDefaultT1CC(MIB);
284      MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
285      if (NeedPred)
286        MIB = AddDefaultPred(MIB);
287      BaseReg = DestReg;
288
289      if (Opc == ARM::tADDrSPi) {
290        // r4 = add sp, imm
291        // r4 = add r4, imm
292        // ...
293        NumBits = 8;
294        Scale = 1;
295        Chunk = ((1 << NumBits) - 1) * Scale;
296        Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
297        NeedPred = NeedCC = isTwoAddr = true;
298      }
299    }
300  }
301
302  if (ExtraOpc) {
303    const TargetInstrDesc &TID = TII.get(ExtraOpc);
304    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
305                   .addReg(DestReg, RegState::Kill)
306                   .addImm(((unsigned)NumBytes) & 3));
307  }
308}
309
310static void emitSPUpdate(MachineBasicBlock &MBB,
311                         MachineBasicBlock::iterator &MBBI,
312                         const TargetInstrInfo &TII, DebugLoc dl,
313                         const Thumb1RegisterInfo &MRI,
314                         int NumBytes) {
315  emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
316                            MRI, dl);
317}
318
319void Thumb1RegisterInfo::
320eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
321                              MachineBasicBlock::iterator I) const {
322  if (!hasReservedCallFrame(MF)) {
323    // If we have alloca, convert as follows:
324    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
325    // ADJCALLSTACKUP   -> add, sp, sp, amount
326    MachineInstr *Old = I;
327    DebugLoc dl = Old->getDebugLoc();
328    unsigned Amount = Old->getOperand(0).getImm();
329    if (Amount != 0) {
330      // We need to keep the stack aligned properly.  To do this, we round the
331      // amount of space needed for the outgoing arguments up to the next
332      // alignment boundary.
333      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
334      Amount = (Amount+Align-1)/Align*Align;
335
336      // Replace the pseudo instruction with a new instruction...
337      unsigned Opc = Old->getOpcode();
338      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
339        emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
340      } else {
341        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
342        emitSPUpdate(MBB, I, TII, dl, *this, Amount);
343      }
344    }
345  }
346  MBB.erase(I);
347}
348
349/// emitThumbConstant - Emit a series of instructions to materialize a
350/// constant.
351static void emitThumbConstant(MachineBasicBlock &MBB,
352                              MachineBasicBlock::iterator &MBBI,
353                              unsigned DestReg, int Imm,
354                              const TargetInstrInfo &TII,
355                              const Thumb1RegisterInfo& MRI,
356                              DebugLoc dl) {
357  bool isSub = Imm < 0;
358  if (isSub) Imm = -Imm;
359
360  int Chunk = (1 << 8) - 1;
361  int ThisVal = (Imm > Chunk) ? Chunk : Imm;
362  Imm -= ThisVal;
363  AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
364                                        DestReg))
365                 .addImm(ThisVal));
366  if (Imm > 0)
367    emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
368  if (isSub) {
369    const TargetInstrDesc &TID = TII.get(ARM::tRSB);
370    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
371                   .addReg(DestReg, RegState::Kill));
372  }
373}
374
375static void removeOperands(MachineInstr &MI, unsigned i) {
376  unsigned Op = i;
377  for (unsigned e = MI.getNumOperands(); i != e; ++i)
378    MI.RemoveOperand(Op);
379}
380
381int Thumb1RegisterInfo::
382rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
383                  unsigned FrameReg, int Offset,
384                  unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const
385{
386  // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
387  // version then can pull out Thumb1 specific parts here
388  return 0;
389}
390
391/// saveScavengerRegister - Spill the register so it can be used by the
392/// register scavenger. Return true.
393bool
394Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
395                                          MachineBasicBlock::iterator I,
396                                          MachineBasicBlock::iterator &UseMI,
397                                          const TargetRegisterClass *RC,
398                                          unsigned Reg) const {
399  // Thumb1 can't use the emergency spill slot on the stack because
400  // ldr/str immediate offsets must be positive, and if we're referencing
401  // off the frame pointer (if, for example, there are alloca() calls in
402  // the function, the offset will be negative. Use R12 instead since that's
403  // a call clobbered register that we know won't be used in Thumb1 mode.
404  DebugLoc DL;
405  BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
406    addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
407
408  // The UseMI is where we would like to restore the register. If there's
409  // interference with R12 before then, however, we'll need to restore it
410  // before that instead and adjust the UseMI.
411  bool done = false;
412  for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
413    // If this instruction affects R12, adjust our restore point.
414    for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
415      const MachineOperand &MO = II->getOperand(i);
416      if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
417          TargetRegisterInfo::isVirtualRegister(MO.getReg()))
418        continue;
419      if (MO.getReg() == ARM::R12) {
420        UseMI = II;
421        done = true;
422        break;
423      }
424    }
425  }
426  // Restore the register from R12
427  BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
428    addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill);
429
430  return true;
431}
432
433unsigned
434Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
435                                        int SPAdj, FrameIndexValue *Value,
436                                        RegScavenger *RS) const{
437  unsigned VReg = 0;
438  unsigned i = 0;
439  MachineInstr &MI = *II;
440  MachineBasicBlock &MBB = *MI.getParent();
441  MachineFunction &MF = *MBB.getParent();
442  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
443  DebugLoc dl = MI.getDebugLoc();
444
445  while (!MI.getOperand(i).isFI()) {
446    ++i;
447    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
448  }
449
450  unsigned FrameReg = ARM::SP;
451  int FrameIndex = MI.getOperand(i).getIndex();
452  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
453               MF.getFrameInfo()->getStackSize() + SPAdj;
454
455  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
456    Offset -= AFI->getGPRCalleeSavedArea1Offset();
457  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
458    Offset -= AFI->getGPRCalleeSavedArea2Offset();
459  else if (MF.getFrameInfo()->hasVarSizedObjects()) {
460    assert(SPAdj == 0 && hasFP(MF) && "Unexpected");
461    // There are alloca()'s in this function, must reference off the frame
462    // pointer instead.
463    FrameReg = getFrameRegister(MF);
464    Offset -= AFI->getFramePtrSpillOffset();
465  }
466
467  // Special handling of dbg_value instructions.
468  if (MI.isDebugValue()) {
469    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
470    MI.getOperand(i+1).ChangeToImmediate(Offset);
471    return 0;
472  }
473
474  unsigned Opcode = MI.getOpcode();
475  const TargetInstrDesc &Desc = MI.getDesc();
476  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
477
478  if (Opcode == ARM::tADDrSPi) {
479    Offset += MI.getOperand(i+1).getImm();
480
481    // Can't use tADDrSPi if it's based off the frame pointer.
482    unsigned NumBits = 0;
483    unsigned Scale = 1;
484    if (FrameReg != ARM::SP) {
485      Opcode = ARM::tADDi3;
486      MI.setDesc(TII.get(Opcode));
487      NumBits = 3;
488    } else {
489      NumBits = 8;
490      Scale = 4;
491      assert((Offset & 3) == 0 &&
492             "Thumb add/sub sp, #imm immediate must be multiple of 4!");
493    }
494
495    unsigned PredReg;
496    if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
497      // Turn it into a move.
498      MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
499      MI.getOperand(i).ChangeToRegister(FrameReg, false);
500      // Remove offset and remaining explicit predicate operands.
501      do MI.RemoveOperand(i+1);
502      while (MI.getNumOperands() > i+1 &&
503             (!MI.getOperand(i+1).isReg() || !MI.getOperand(i+1).isImm()));
504      return 0;
505    }
506
507    // Common case: small offset, fits into instruction.
508    unsigned Mask = (1 << NumBits) - 1;
509    if (((Offset / Scale) & ~Mask) == 0) {
510      // Replace the FrameIndex with sp / fp
511      if (Opcode == ARM::tADDi3) {
512        removeOperands(MI, i);
513        MachineInstrBuilder MIB(&MI);
514        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
515                       .addImm(Offset / Scale));
516      } else {
517        MI.getOperand(i).ChangeToRegister(FrameReg, false);
518        MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
519      }
520      return 0;
521    }
522
523    unsigned DestReg = MI.getOperand(0).getReg();
524    unsigned Bytes = (Offset > 0) ? Offset : -Offset;
525    unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
526    // MI would expand into a large number of instructions. Don't try to
527    // simplify the immediate.
528    if (NumMIs > 2) {
529      emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
530                                *this, dl);
531      MBB.erase(II);
532      return 0;
533    }
534
535    if (Offset > 0) {
536      // Translate r0 = add sp, imm to
537      // r0 = add sp, 255*4
538      // r0 = add r0, (imm - 255*4)
539      if (Opcode == ARM::tADDi3) {
540        removeOperands(MI, i);
541        MachineInstrBuilder MIB(&MI);
542        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
543      } else {
544        MI.getOperand(i).ChangeToRegister(FrameReg, false);
545        MI.getOperand(i+1).ChangeToImmediate(Mask);
546      }
547      Offset = (Offset - Mask * Scale);
548      MachineBasicBlock::iterator NII = llvm::next(II);
549      emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
550                                *this, dl);
551    } else {
552      // Translate r0 = add sp, -imm to
553      // r0 = -imm (this is then translated into a series of instructons)
554      // r0 = add r0, sp
555      emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
556
557      MI.setDesc(TII.get(ARM::tADDhirr));
558      MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
559      MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
560      if (Opcode == ARM::tADDi3) {
561        MachineInstrBuilder MIB(&MI);
562        AddDefaultPred(MIB);
563      }
564    }
565    return 0;
566  } else {
567    unsigned ImmIdx = 0;
568    int InstrOffs = 0;
569    unsigned NumBits = 0;
570    unsigned Scale = 1;
571    switch (AddrMode) {
572    case ARMII::AddrModeT1_s: {
573      ImmIdx = i+1;
574      InstrOffs = MI.getOperand(ImmIdx).getImm();
575      NumBits = (FrameReg == ARM::SP) ? 8 : 5;
576      Scale = 4;
577      break;
578    }
579    default:
580      llvm_unreachable("Unsupported addressing mode!");
581      break;
582    }
583
584    Offset += InstrOffs * Scale;
585    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
586
587    // Common case: small offset, fits into instruction.
588    MachineOperand &ImmOp = MI.getOperand(ImmIdx);
589    int ImmedOffset = Offset / Scale;
590    unsigned Mask = (1 << NumBits) - 1;
591    if ((unsigned)Offset <= Mask * Scale) {
592      // Replace the FrameIndex with sp
593      MI.getOperand(i).ChangeToRegister(FrameReg, false);
594      ImmOp.ChangeToImmediate(ImmedOffset);
595      return 0;
596    }
597
598    bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
599    if (AddrMode == ARMII::AddrModeT1_s) {
600      // Thumb tLDRspi, tSTRspi. These will change to instructions that use
601      // a different base register.
602      NumBits = 5;
603      Mask = (1 << NumBits) - 1;
604    }
605    // If this is a thumb spill / restore, we will be using a constpool load to
606    // materialize the offset.
607    if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
608      ImmOp.ChangeToImmediate(0);
609    else {
610      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
611      ImmedOffset = ImmedOffset & Mask;
612      ImmOp.ChangeToImmediate(ImmedOffset);
613      Offset &= ~(Mask*Scale);
614    }
615  }
616
617  // If we get here, the immediate doesn't fit into the instruction.  We folded
618  // as much as possible above, handle the rest, providing a register that is
619  // SP+LargeImm.
620  assert(Offset && "This code isn't needed if offset already handled!");
621
622  // Remove predicate first.
623  int PIdx = MI.findFirstPredOperandIdx();
624  if (PIdx != -1)
625    removeOperands(MI, PIdx);
626
627  if (Desc.mayLoad()) {
628    // Use the destination register to materialize sp + offset.
629    unsigned TmpReg = MI.getOperand(0).getReg();
630    bool UseRR = false;
631    if (Opcode == ARM::tRestore) {
632      if (FrameReg == ARM::SP)
633        emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
634                                 Offset, false, TII, *this, dl);
635      else {
636        emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
637        UseRR = true;
638      }
639    } else {
640      emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
641                                *this, dl);
642    }
643
644    MI.setDesc(TII.get(ARM::tLDR));
645    MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
646    if (UseRR)
647      // Use [reg, reg] addrmode.
648      MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
649    else  // tLDR has an extra register operand.
650      MI.addOperand(MachineOperand::CreateReg(0, false));
651  } else if (Desc.mayStore()) {
652      VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
653      assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
654      bool UseRR = false;
655      bool TrackVReg = true;
656      Value->first = FrameReg; // use the frame register as a kind indicator
657      Value->second = Offset;
658
659      if (Opcode == ARM::tSpill) {
660        if (FrameReg == ARM::SP)
661          emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
662                                   Offset, false, TII, *this, dl);
663        else {
664          emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
665          UseRR = true;
666          TrackVReg = false;
667        }
668      } else
669        emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
670                                  *this, dl);
671      MI.setDesc(TII.get(ARM::tSTR));
672      MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
673      if (UseRR)  // Use [reg, reg] addrmode.
674        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
675      else // tSTR has an extra register operand.
676        MI.addOperand(MachineOperand::CreateReg(0, false));
677      if (!ReuseFrameIndexVals || !TrackVReg)
678        VReg = 0;
679  } else
680    assert(false && "Unexpected opcode!");
681
682  // Add predicate back if it's needed.
683  if (MI.getDesc().isPredicable()) {
684    MachineInstrBuilder MIB(&MI);
685    AddDefaultPred(MIB);
686  }
687  return VReg;
688}
689
690void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
691  MachineBasicBlock &MBB = MF.front();
692  MachineBasicBlock::iterator MBBI = MBB.begin();
693  MachineFrameInfo  *MFI = MF.getFrameInfo();
694  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
695  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
696  unsigned NumBytes = MFI->getStackSize();
697  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
698  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
699
700  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
701  NumBytes = (NumBytes + 3) & ~3;
702  MFI->setStackSize(NumBytes);
703
704  // Determine the sizes of each callee-save spill areas and record which frame
705  // belongs to which callee-save spill areas.
706  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
707  int FramePtrSpillFI = 0;
708
709  if (VARegSaveSize)
710    emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
711
712  if (!AFI->hasStackFrame()) {
713    if (NumBytes != 0)
714      emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
715    return;
716  }
717
718  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
719    unsigned Reg = CSI[i].getReg();
720    int FI = CSI[i].getFrameIdx();
721    switch (Reg) {
722    case ARM::R4:
723    case ARM::R5:
724    case ARM::R6:
725    case ARM::R7:
726    case ARM::LR:
727      if (Reg == FramePtr)
728        FramePtrSpillFI = FI;
729      AFI->addGPRCalleeSavedArea1Frame(FI);
730      GPRCS1Size += 4;
731      break;
732    case ARM::R8:
733    case ARM::R9:
734    case ARM::R10:
735    case ARM::R11:
736      if (Reg == FramePtr)
737        FramePtrSpillFI = FI;
738      if (STI.isTargetDarwin()) {
739        AFI->addGPRCalleeSavedArea2Frame(FI);
740        GPRCS2Size += 4;
741      } else {
742        AFI->addGPRCalleeSavedArea1Frame(FI);
743        GPRCS1Size += 4;
744      }
745      break;
746    default:
747      AFI->addDPRCalleeSavedAreaFrame(FI);
748      DPRCSSize += 8;
749    }
750  }
751
752  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
753    ++MBBI;
754    if (MBBI != MBB.end())
755      dl = MBBI->getDebugLoc();
756  }
757
758  // Darwin ABI requires FP to point to the stack slot that contains the
759  // previous FP.
760  if (STI.isTargetDarwin() || hasFP(MF)) {
761    BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
762      .addFrameIndex(FramePtrSpillFI).addImm(0);
763  }
764
765  // Determine starting offsets of spill areas.
766  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
767  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
768  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
769  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
770  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
771  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
772  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
773
774  NumBytes = DPRCSOffset;
775  if (NumBytes) {
776    // Insert it after all the callee-save spills.
777    emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
778  }
779
780  if (STI.isTargetELF() && hasFP(MF)) {
781    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
782                             AFI->getFramePtrSpillOffset());
783  }
784
785  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
786  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
787  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
788}
789
790static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
791  for (unsigned i = 0; CSRegs[i]; ++i)
792    if (Reg == CSRegs[i])
793      return true;
794  return false;
795}
796
797static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
798  if (MI->getOpcode() == ARM::tRestore &&
799      MI->getOperand(1).isFI() &&
800      isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
801    return true;
802  else if (MI->getOpcode() == ARM::tPOP) {
803    // The first two operands are predicates. The last two are
804    // imp-def and imp-use of SP. Check everything in between.
805    for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
806      if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
807        return false;
808    return true;
809  }
810  return false;
811}
812
813void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
814                                      MachineBasicBlock &MBB) const {
815  MachineBasicBlock::iterator MBBI = prior(MBB.end());
816  assert((MBBI->getOpcode() == ARM::tBX_RET ||
817          MBBI->getOpcode() == ARM::tPOP_RET) &&
818         "Can only insert epilog into returning blocks");
819  DebugLoc dl = MBBI->getDebugLoc();
820  MachineFrameInfo *MFI = MF.getFrameInfo();
821  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
822  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
823  int NumBytes = (int)MFI->getStackSize();
824  const unsigned *CSRegs = getCalleeSavedRegs();
825
826  if (!AFI->hasStackFrame()) {
827    if (NumBytes != 0)
828      emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
829  } else {
830    // Unwind MBBI to point to first LDR / VLDRD.
831    if (MBBI != MBB.begin()) {
832      do
833        --MBBI;
834      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
835      if (!isCSRestore(MBBI, CSRegs))
836        ++MBBI;
837    }
838
839    // Move SP to start of FP callee save spill area.
840    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
841                 AFI->getGPRCalleeSavedArea2Size() +
842                 AFI->getDPRCalleeSavedAreaSize());
843
844    if (hasFP(MF)) {
845      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
846      // Reset SP based on frame pointer only if the stack frame extends beyond
847      // frame pointer stack slot or target is ELF and the function has FP.
848      if (NumBytes)
849        emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
850                                  TII, *this, dl);
851      else
852        BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
853          .addReg(FramePtr);
854    } else {
855      if (MBBI->getOpcode() == ARM::tBX_RET &&
856          &MBB.front() != MBBI &&
857          prior(MBBI)->getOpcode() == ARM::tPOP) {
858        MachineBasicBlock::iterator PMBBI = prior(MBBI);
859        emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
860      } else
861        emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
862    }
863  }
864
865  if (VARegSaveSize) {
866    // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
867    // to LR, and we can't pop the value directly to the PC since
868    // we need to update the SP after popping the value. Therefore, we
869    // pop the old LR into R3 as a temporary.
870
871    // Move back past the callee-saved register restoration
872    while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
873      ++MBBI;
874    // Epilogue for vararg functions: pop LR to R3 and branch off it.
875    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
876      .addReg(ARM::R3, RegState::Define);
877
878    emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
879
880    BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
881      .addReg(ARM::R3, RegState::Kill);
882    // erase the old tBX_RET instruction
883    MBB.erase(MBBI);
884  }
885}
886