Thumb1RegisterInfo.cpp revision 6a8700301ca6f8f2f5f787c8d1f5206a7dfceed6 
1//===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMSubtarget.h"
20#include "Thumb1InstrInfo.h"
21#include "Thumb1RegisterInfo.h"
22#include "llvm/Constants.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
25#include "llvm/LLVMContext.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/Target/TargetFrameInfo.h"
33#include "llvm/Target/TargetMachine.h"
34#include "llvm/ADT/BitVector.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39
40namespace llvm {
41extern cl::opt<bool> ReuseFrameIndexVals;
42}
43
44using namespace llvm;
45
46Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
47                                       const ARMSubtarget &sti)
48  : ARMBaseRegisterInfo(tii, sti) {
49}
50
51/// emitLoadConstPool - Emits a load from constpool to materialize the
52/// specified immediate.
53void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
54                                           MachineBasicBlock::iterator &MBBI,
55                                           DebugLoc dl,
56                                           unsigned DestReg, unsigned SubIdx,
57                                           int Val,
58                                           ARMCC::CondCodes Pred,
59                                           unsigned PredReg) const {
60  MachineFunction &MF = *MBB.getParent();
61  MachineConstantPool *ConstantPool = MF.getConstantPool();
62  const Constant *C = ConstantInt::get(
63          Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
64  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
65
66  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
67          .addReg(DestReg, getDefRegState(true), SubIdx)
68          .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
69}
70
71bool Thumb1RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
72  const MachineFrameInfo *FFI = MF.getFrameInfo();
73  unsigned CFSize = FFI->getMaxCallFrameSize();
74  // It's not always a good idea to include the call frame as part of the
75  // stack frame. ARM (especially Thumb) has small immediate offset to
76  // address the stack frame. So a large call frame can cause poor codegen
77  // and may even makes it impossible to scavenge a register.
78  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
79    return false;
80
81  return !MF.getFrameInfo()->hasVarSizedObjects();
82}
83
84
85/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
86/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
87/// in a register using mov / mvn sequences or load the immediate from a
88/// constpool entry.
89static
90void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
91                              MachineBasicBlock::iterator &MBBI,
92                              unsigned DestReg, unsigned BaseReg,
93                              int NumBytes, bool CanChangeCC,
94                              const TargetInstrInfo &TII,
95                              const Thumb1RegisterInfo& MRI,
96                              DebugLoc dl) {
97    MachineFunction &MF = *MBB.getParent();
98    bool isHigh = !isARMLowRegister(DestReg) ||
99                  (BaseReg != 0 && !isARMLowRegister(BaseReg));
100    bool isSub = false;
101    // Subtract doesn't have high register version. Load the negative value
102    // if either base or dest register is a high register. Also, if do not
103    // issue sub as part of the sequence if condition register is to be
104    // preserved.
105    if (NumBytes < 0 && !isHigh && CanChangeCC) {
106      isSub = true;
107      NumBytes = -NumBytes;
108    }
109    unsigned LdReg = DestReg;
110    if (DestReg == ARM::SP) {
111      assert(BaseReg == ARM::SP && "Unexpected!");
112      LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
113    }
114
115    if (NumBytes <= 255 && NumBytes >= 0)
116      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
117        .addImm(NumBytes);
118    else if (NumBytes < 0 && NumBytes >= -255) {
119      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
120        .addImm(NumBytes);
121      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
122        .addReg(LdReg, RegState::Kill);
123    } else
124      MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
125
126    // Emit add / sub.
127    int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
128    MachineInstrBuilder MIB =
129      BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
130    if (Opc != ARM::tADDhirr)
131      MIB = AddDefaultT1CC(MIB);
132    if (DestReg == ARM::SP || isSub)
133      MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
134    else
135      MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
136    AddDefaultPred(MIB);
137}
138
139/// calcNumMI - Returns the number of instructions required to materialize
140/// the specific add / sub r, c instruction.
141static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
142                          unsigned NumBits, unsigned Scale) {
143  unsigned NumMIs = 0;
144  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
145
146  if (Opc == ARM::tADDrSPi) {
147    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
148    Bytes -= ThisVal;
149    NumMIs++;
150    NumBits = 8;
151    Scale = 1;  // Followed by a number of tADDi8.
152    Chunk = ((1 << NumBits) - 1) * Scale;
153  }
154
155  NumMIs += Bytes / Chunk;
156  if ((Bytes % Chunk) != 0)
157    NumMIs++;
158  if (ExtraOpc)
159    NumMIs++;
160  return NumMIs;
161}
162
163/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
164/// a destreg = basereg + immediate in Thumb code.
165static
166void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
167                               MachineBasicBlock::iterator &MBBI,
168                               unsigned DestReg, unsigned BaseReg,
169                               int NumBytes, const TargetInstrInfo &TII,
170                               const Thumb1RegisterInfo& MRI,
171                               DebugLoc dl) {
172  bool isSub = NumBytes < 0;
173  unsigned Bytes = (unsigned)NumBytes;
174  if (isSub) Bytes = -NumBytes;
175  bool isMul4 = (Bytes & 3) == 0;
176  bool isTwoAddr = false;
177  bool DstNotEqBase = false;
178  unsigned NumBits = 1;
179  unsigned Scale = 1;
180  int Opc = 0;
181  int ExtraOpc = 0;
182  bool NeedCC = false;
183  bool NeedPred = false;
184
185  if (DestReg == BaseReg && BaseReg == ARM::SP) {
186    assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
187    NumBits = 7;
188    Scale = 4;
189    Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
190    isTwoAddr = true;
191  } else if (!isSub && BaseReg == ARM::SP) {
192    // r1 = add sp, 403
193    // =>
194    // r1 = add sp, 100 * 4
195    // r1 = add r1, 3
196    if (!isMul4) {
197      Bytes &= ~3;
198      ExtraOpc = ARM::tADDi3;
199    }
200    NumBits = 8;
201    Scale = 4;
202    Opc = ARM::tADDrSPi;
203  } else {
204    // sp = sub sp, c
205    // r1 = sub sp, c
206    // r8 = sub sp, c
207    if (DestReg != BaseReg)
208      DstNotEqBase = true;
209    NumBits = 8;
210    if (DestReg == ARM::SP) {
211      Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
212      assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
213      NumBits = 7;
214      Scale = 4;
215    } else {
216      Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
217      NumBits = 8;
218      NeedPred = NeedCC = true;
219    }
220    isTwoAddr = true;
221  }
222
223  unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
224  unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
225  if (NumMIs > Threshold) {
226    // This will expand into too many instructions. Load the immediate from a
227    // constpool entry.
228    emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
229                             MRI, dl);
230    return;
231  }
232
233  if (DstNotEqBase) {
234    if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
235      // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
236      unsigned Chunk = (1 << 3) - 1;
237      unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
238      Bytes -= ThisVal;
239      const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
240      const MachineInstrBuilder MIB =
241        AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
242      AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
243    } else {
244      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
245        .addReg(BaseReg, RegState::Kill);
246    }
247    BaseReg = DestReg;
248  }
249
250  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
251  while (Bytes) {
252    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
253    Bytes -= ThisVal;
254    ThisVal /= Scale;
255    // Build the new tADD / tSUB.
256    if (isTwoAddr) {
257      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
258      if (NeedCC)
259        MIB = AddDefaultT1CC(MIB);
260      MIB .addReg(DestReg).addImm(ThisVal);
261      if (NeedPred)
262        MIB = AddDefaultPred(MIB);
263    }
264    else {
265      bool isKill = BaseReg != ARM::SP;
266      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
267      if (NeedCC)
268        MIB = AddDefaultT1CC(MIB);
269      MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
270      if (NeedPred)
271        MIB = AddDefaultPred(MIB);
272      BaseReg = DestReg;
273
274      if (Opc == ARM::tADDrSPi) {
275        // r4 = add sp, imm
276        // r4 = add r4, imm
277        // ...
278        NumBits = 8;
279        Scale = 1;
280        Chunk = ((1 << NumBits) - 1) * Scale;
281        Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
282        NeedPred = NeedCC = isTwoAddr = true;
283      }
284    }
285  }
286
287  if (ExtraOpc) {
288    const TargetInstrDesc &TID = TII.get(ExtraOpc);
289    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
290                   .addReg(DestReg, RegState::Kill)
291                   .addImm(((unsigned)NumBytes) & 3));
292  }
293}
294
295static void emitSPUpdate(MachineBasicBlock &MBB,
296                         MachineBasicBlock::iterator &MBBI,
297                         const TargetInstrInfo &TII, DebugLoc dl,
298                         const Thumb1RegisterInfo &MRI,
299                         int NumBytes) {
300  emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
301                            MRI, dl);
302}
303
304void Thumb1RegisterInfo::
305eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
306                              MachineBasicBlock::iterator I) const {
307  if (!hasReservedCallFrame(MF)) {
308    // If we have alloca, convert as follows:
309    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
310    // ADJCALLSTACKUP   -> add, sp, sp, amount
311    MachineInstr *Old = I;
312    DebugLoc dl = Old->getDebugLoc();
313    unsigned Amount = Old->getOperand(0).getImm();
314    if (Amount != 0) {
315      // We need to keep the stack aligned properly.  To do this, we round the
316      // amount of space needed for the outgoing arguments up to the next
317      // alignment boundary.
318      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
319      Amount = (Amount+Align-1)/Align*Align;
320
321      // Replace the pseudo instruction with a new instruction...
322      unsigned Opc = Old->getOpcode();
323      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
324        emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
325      } else {
326        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
327        emitSPUpdate(MBB, I, TII, dl, *this, Amount);
328      }
329    }
330  }
331  MBB.erase(I);
332}
333
334/// emitThumbConstant - Emit a series of instructions to materialize a
335/// constant.
336static void emitThumbConstant(MachineBasicBlock &MBB,
337                              MachineBasicBlock::iterator &MBBI,
338                              unsigned DestReg, int Imm,
339                              const TargetInstrInfo &TII,
340                              const Thumb1RegisterInfo& MRI,
341                              DebugLoc dl) {
342  bool isSub = Imm < 0;
343  if (isSub) Imm = -Imm;
344
345  int Chunk = (1 << 8) - 1;
346  int ThisVal = (Imm > Chunk) ? Chunk : Imm;
347  Imm -= ThisVal;
348  AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
349                                        DestReg))
350                 .addImm(ThisVal));
351  if (Imm > 0)
352    emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
353  if (isSub) {
354    const TargetInstrDesc &TID = TII.get(ARM::tRSB);
355    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
356                   .addReg(DestReg, RegState::Kill));
357  }
358}
359
360static void removeOperands(MachineInstr &MI, unsigned i) {
361  unsigned Op = i;
362  for (unsigned e = MI.getNumOperands(); i != e; ++i)
363    MI.RemoveOperand(Op);
364}
365
366bool Thumb1RegisterInfo::
367rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
368                  unsigned FrameReg, int &Offset,
369                  const ARMBaseInstrInfo &TII) const {
370  MachineInstr &MI = *II;
371  MachineBasicBlock &MBB = *MI.getParent();
372  DebugLoc dl = MI.getDebugLoc();
373  unsigned Opcode = MI.getOpcode();
374  const TargetInstrDesc &Desc = MI.getDesc();
375  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
376
377  if (Opcode == ARM::tADDrSPi) {
378    Offset += MI.getOperand(FrameRegIdx+1).getImm();
379
380    // Can't use tADDrSPi if it's based off the frame pointer.
381    unsigned NumBits = 0;
382    unsigned Scale = 1;
383    if (FrameReg != ARM::SP) {
384      Opcode = ARM::tADDi3;
385      MI.setDesc(TII.get(Opcode));
386      NumBits = 3;
387    } else {
388      NumBits = 8;
389      Scale = 4;
390      assert((Offset & 3) == 0 &&
391             "Thumb add/sub sp, #imm immediate must be multiple of 4!");
392    }
393
394    unsigned PredReg;
395    if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
396      // Turn it into a move.
397      MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
398      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
399      // Remove offset and remaining explicit predicate operands.
400      do MI.RemoveOperand(FrameRegIdx+1);
401      while (MI.getNumOperands() > FrameRegIdx+1 &&
402             (!MI.getOperand(FrameRegIdx+1).isReg() ||
403              !MI.getOperand(FrameRegIdx+1).isImm()));
404      return true;
405    }
406
407    // Common case: small offset, fits into instruction.
408    unsigned Mask = (1 << NumBits) - 1;
409    if (((Offset / Scale) & ~Mask) == 0) {
410      // Replace the FrameIndex with sp / fp
411      if (Opcode == ARM::tADDi3) {
412        removeOperands(MI, FrameRegIdx);
413        MachineInstrBuilder MIB(&MI);
414        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
415                       .addImm(Offset / Scale));
416      } else {
417        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
418        MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset / Scale);
419      }
420      return true;
421    }
422
423    unsigned DestReg = MI.getOperand(0).getReg();
424    unsigned Bytes = (Offset > 0) ? Offset : -Offset;
425    unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
426    // MI would expand into a large number of instructions. Don't try to
427    // simplify the immediate.
428    if (NumMIs > 2) {
429      emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
430                                *this, dl);
431      MBB.erase(II);
432      return true;
433    }
434
435    if (Offset > 0) {
436      // Translate r0 = add sp, imm to
437      // r0 = add sp, 255*4
438      // r0 = add r0, (imm - 255*4)
439      if (Opcode == ARM::tADDi3) {
440        removeOperands(MI, FrameRegIdx);
441        MachineInstrBuilder MIB(&MI);
442        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
443      } else {
444        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
445        MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
446      }
447      Offset = (Offset - Mask * Scale);
448      MachineBasicBlock::iterator NII = llvm::next(II);
449      emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
450                                *this, dl);
451    } else {
452      // Translate r0 = add sp, -imm to
453      // r0 = -imm (this is then translated into a series of instructons)
454      // r0 = add r0, sp
455      emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
456
457      MI.setDesc(TII.get(ARM::tADDhirr));
458      MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true);
459      MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false);
460      if (Opcode == ARM::tADDi3) {
461        MachineInstrBuilder MIB(&MI);
462        AddDefaultPred(MIB);
463      }
464    }
465    return true;
466  } else {
467    unsigned ImmIdx = 0;
468    int InstrOffs = 0;
469    unsigned NumBits = 0;
470    unsigned Scale = 1;
471    switch (AddrMode) {
472    case ARMII::AddrModeT1_s: {
473      ImmIdx = FrameRegIdx+1;
474      InstrOffs = MI.getOperand(ImmIdx).getImm();
475      NumBits = (FrameReg == ARM::SP) ? 8 : 5;
476      Scale = 4;
477      break;
478    }
479    default:
480      llvm_unreachable("Unsupported addressing mode!");
481      break;
482    }
483
484    Offset += InstrOffs * Scale;
485    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
486
487    // Common case: small offset, fits into instruction.
488    MachineOperand &ImmOp = MI.getOperand(ImmIdx);
489    int ImmedOffset = Offset / Scale;
490    unsigned Mask = (1 << NumBits) - 1;
491    if ((unsigned)Offset <= Mask * Scale) {
492      // Replace the FrameIndex with sp
493      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
494      ImmOp.ChangeToImmediate(ImmedOffset);
495      return true;
496    }
497
498    bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
499    if (AddrMode == ARMII::AddrModeT1_s) {
500      // Thumb tLDRspi, tSTRspi. These will change to instructions that use
501      // a different base register.
502      NumBits = 5;
503      Mask = (1 << NumBits) - 1;
504    }
505    // If this is a thumb spill / restore, we will be using a constpool load to
506    // materialize the offset.
507    if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
508      ImmOp.ChangeToImmediate(0);
509    else {
510      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
511      ImmedOffset = ImmedOffset & Mask;
512      ImmOp.ChangeToImmediate(ImmedOffset);
513      Offset &= ~(Mask*Scale);
514    }
515  }
516  return Offset == 0;
517}
518
519void
520Thumb1RegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
521                                      unsigned BaseReg, int64_t Offset) const {
522  MachineInstr &MI = *I;
523  int Off = Offset; // ARM doesn't need the general 64-bit offsets
524  unsigned i = 0;
525
526  while (!MI.getOperand(i).isFI()) {
527    ++i;
528    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
529  }
530  bool Done = false;
531  Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
532  assert (Done && "Unable to resolve frame index!");
533}
534
535/// saveScavengerRegister - Spill the register so it can be used by the
536/// register scavenger. Return true.
537bool
538Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
539                                          MachineBasicBlock::iterator I,
540                                          MachineBasicBlock::iterator &UseMI,
541                                          const TargetRegisterClass *RC,
542                                          unsigned Reg) const {
543  // Thumb1 can't use the emergency spill slot on the stack because
544  // ldr/str immediate offsets must be positive, and if we're referencing
545  // off the frame pointer (if, for example, there are alloca() calls in
546  // the function, the offset will be negative. Use R12 instead since that's
547  // a call clobbered register that we know won't be used in Thumb1 mode.
548  DebugLoc DL;
549  BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
550    addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
551
552  // The UseMI is where we would like to restore the register. If there's
553  // interference with R12 before then, however, we'll need to restore it
554  // before that instead and adjust the UseMI.
555  bool done = false;
556  for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
557    if (II->isDebugValue())
558      continue;
559    // If this instruction affects R12, adjust our restore point.
560    for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
561      const MachineOperand &MO = II->getOperand(i);
562      if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
563          TargetRegisterInfo::isVirtualRegister(MO.getReg()))
564        continue;
565      if (MO.getReg() == ARM::R12) {
566        UseMI = II;
567        done = true;
568        break;
569      }
570    }
571  }
572  // Restore the register from R12
573  BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
574    addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill);
575
576  return true;
577}
578
579void
580Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
581                                        int SPAdj, RegScavenger *RS) const {
582  unsigned VReg = 0;
583  unsigned i = 0;
584  MachineInstr &MI = *II;
585  MachineBasicBlock &MBB = *MI.getParent();
586  MachineFunction &MF = *MBB.getParent();
587  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
588  DebugLoc dl = MI.getDebugLoc();
589
590  while (!MI.getOperand(i).isFI()) {
591    ++i;
592    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
593  }
594
595  unsigned FrameReg = ARM::SP;
596  int FrameIndex = MI.getOperand(i).getIndex();
597  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
598               MF.getFrameInfo()->getStackSize() + SPAdj;
599
600  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
601    Offset -= AFI->getGPRCalleeSavedArea1Offset();
602  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
603    Offset -= AFI->getGPRCalleeSavedArea2Offset();
604  else if (MF.getFrameInfo()->hasVarSizedObjects()) {
605    assert(SPAdj == 0 && hasFP(MF) && "Unexpected");
606    // There are alloca()'s in this function, must reference off the frame
607    // pointer instead.
608    FrameReg = getFrameRegister(MF);
609    Offset -= AFI->getFramePtrSpillOffset();
610  }
611
612  // Special handling of dbg_value instructions.
613  if (MI.isDebugValue()) {
614    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
615    MI.getOperand(i+1).ChangeToImmediate(Offset);
616    return;
617  }
618
619  // Modify MI as necessary to handle as much of 'Offset' as possible
620  assert(AFI->isThumbFunction() &&
621         "This eliminateFrameIndex only supports Thumb1!");
622  if (rewriteFrameIndex(MI, i, FrameReg, Offset, TII))
623    return;
624
625  // If we get here, the immediate doesn't fit into the instruction.  We folded
626  // as much as possible above, handle the rest, providing a register that is
627  // SP+LargeImm.
628  assert(Offset && "This code isn't needed if offset already handled!");
629
630  unsigned Opcode = MI.getOpcode();
631  const TargetInstrDesc &Desc = MI.getDesc();
632
633  // Remove predicate first.
634  int PIdx = MI.findFirstPredOperandIdx();
635  if (PIdx != -1)
636    removeOperands(MI, PIdx);
637
638  if (Desc.mayLoad()) {
639    // Use the destination register to materialize sp + offset.
640    unsigned TmpReg = MI.getOperand(0).getReg();
641    bool UseRR = false;
642    if (Opcode == ARM::tRestore) {
643      if (FrameReg == ARM::SP)
644        emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
645                                 Offset, false, TII, *this, dl);
646      else {
647        emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
648        UseRR = true;
649      }
650    } else {
651      emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
652                                *this, dl);
653    }
654
655    MI.setDesc(TII.get(ARM::tLDR));
656    MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
657    if (UseRR)
658      // Use [reg, reg] addrmode.
659      MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
660    else  // tLDR has an extra register operand.
661      MI.addOperand(MachineOperand::CreateReg(0, false));
662  } else if (Desc.mayStore()) {
663      VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
664      bool UseRR = false;
665
666      if (Opcode == ARM::tSpill) {
667        if (FrameReg == ARM::SP)
668          emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
669                                   Offset, false, TII, *this, dl);
670        else {
671          emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
672          UseRR = true;
673        }
674      } else
675        emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
676                                  *this, dl);
677      MI.setDesc(TII.get(ARM::tSTR));
678      MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
679      if (UseRR)  // Use [reg, reg] addrmode.
680        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
681      else // tSTR has an extra register operand.
682        MI.addOperand(MachineOperand::CreateReg(0, false));
683  } else
684    assert(false && "Unexpected opcode!");
685
686  // Add predicate back if it's needed.
687  if (MI.getDesc().isPredicable()) {
688    MachineInstrBuilder MIB(&MI);
689    AddDefaultPred(MIB);
690  }
691}
692
693void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
694  MachineBasicBlock &MBB = MF.front();
695  MachineBasicBlock::iterator MBBI = MBB.begin();
696  MachineFrameInfo  *MFI = MF.getFrameInfo();
697  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
698  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
699  unsigned NumBytes = MFI->getStackSize();
700  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
701  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
702
703  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
704  NumBytes = (NumBytes + 3) & ~3;
705  MFI->setStackSize(NumBytes);
706
707  // Determine the sizes of each callee-save spill areas and record which frame
708  // belongs to which callee-save spill areas.
709  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
710  int FramePtrSpillFI = 0;
711
712  if (VARegSaveSize)
713    emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
714
715  if (!AFI->hasStackFrame()) {
716    if (NumBytes != 0)
717      emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
718    return;
719  }
720
721  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
722    unsigned Reg = CSI[i].getReg();
723    int FI = CSI[i].getFrameIdx();
724    switch (Reg) {
725    case ARM::R4:
726    case ARM::R5:
727    case ARM::R6:
728    case ARM::R7:
729    case ARM::LR:
730      if (Reg == FramePtr)
731        FramePtrSpillFI = FI;
732      AFI->addGPRCalleeSavedArea1Frame(FI);
733      GPRCS1Size += 4;
734      break;
735    case ARM::R8:
736    case ARM::R9:
737    case ARM::R10:
738    case ARM::R11:
739      if (Reg == FramePtr)
740        FramePtrSpillFI = FI;
741      if (STI.isTargetDarwin()) {
742        AFI->addGPRCalleeSavedArea2Frame(FI);
743        GPRCS2Size += 4;
744      } else {
745        AFI->addGPRCalleeSavedArea1Frame(FI);
746        GPRCS1Size += 4;
747      }
748      break;
749    default:
750      AFI->addDPRCalleeSavedAreaFrame(FI);
751      DPRCSSize += 8;
752    }
753  }
754
755  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
756    ++MBBI;
757    if (MBBI != MBB.end())
758      dl = MBBI->getDebugLoc();
759  }
760
761  // Adjust FP so it point to the stack slot that contains the previous FP.
762  if (hasFP(MF)) {
763    BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
764      .addFrameIndex(FramePtrSpillFI).addImm(0);
765    AFI->setShouldRestoreSPFromFP(true);
766  }
767
768  // Determine starting offsets of spill areas.
769  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
770  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
771  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
772  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
773  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
774  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
775  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
776
777  NumBytes = DPRCSOffset;
778  if (NumBytes) {
779    // Insert it after all the callee-save spills.
780    emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
781  }
782
783  if (STI.isTargetELF() && hasFP(MF))
784    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
785                             AFI->getFramePtrSpillOffset());
786
787  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
788  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
789  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
790}
791
792static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
793  for (unsigned i = 0; CSRegs[i]; ++i)
794    if (Reg == CSRegs[i])
795      return true;
796  return false;
797}
798
799static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
800  if (MI->getOpcode() == ARM::tRestore &&
801      MI->getOperand(1).isFI() &&
802      isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
803    return true;
804  else if (MI->getOpcode() == ARM::tPOP) {
805    // The first two operands are predicates. The last two are
806    // imp-def and imp-use of SP. Check everything in between.
807    for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
808      if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
809        return false;
810    return true;
811  }
812  return false;
813}
814
815void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
816                                      MachineBasicBlock &MBB) const {
817  MachineBasicBlock::iterator MBBI = prior(MBB.end());
818  assert((MBBI->getOpcode() == ARM::tBX_RET ||
819          MBBI->getOpcode() == ARM::tPOP_RET) &&
820         "Can only insert epilog into returning blocks");
821  DebugLoc dl = MBBI->getDebugLoc();
822  MachineFrameInfo *MFI = MF.getFrameInfo();
823  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
824  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
825  int NumBytes = (int)MFI->getStackSize();
826  const unsigned *CSRegs = getCalleeSavedRegs();
827
828  if (!AFI->hasStackFrame()) {
829    if (NumBytes != 0)
830      emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
831  } else {
832    // Unwind MBBI to point to first LDR / VLDRD.
833    if (MBBI != MBB.begin()) {
834      do
835        --MBBI;
836      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
837      if (!isCSRestore(MBBI, CSRegs))
838        ++MBBI;
839    }
840
841    // Move SP to start of FP callee save spill area.
842    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
843                 AFI->getGPRCalleeSavedArea2Size() +
844                 AFI->getDPRCalleeSavedAreaSize());
845
846    if (AFI->shouldRestoreSPFromFP()) {
847      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
848      // Reset SP based on frame pointer only if the stack frame extends beyond
849      // frame pointer stack slot or target is ELF and the function has FP.
850      if (NumBytes)
851        emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
852                                  TII, *this, dl);
853      else
854        BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
855          .addReg(FramePtr);
856    } else {
857      if (MBBI->getOpcode() == ARM::tBX_RET &&
858          &MBB.front() != MBBI &&
859          prior(MBBI)->getOpcode() == ARM::tPOP) {
860        MachineBasicBlock::iterator PMBBI = prior(MBBI);
861        emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
862      } else
863        emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
864    }
865  }
866
867  if (VARegSaveSize) {
868    // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
869    // to LR, and we can't pop the value directly to the PC since
870    // we need to update the SP after popping the value. Therefore, we
871    // pop the old LR into R3 as a temporary.
872
873    // Move back past the callee-saved register restoration
874    while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
875      ++MBBI;
876    // Epilogue for vararg functions: pop LR to R3 and branch off it.
877    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
878      .addReg(ARM::R3, RegState::Define);
879
880    emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
881
882    BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
883      .addReg(ARM::R3, RegState::Kill);
884    // erase the old tBX_RET instruction
885    MBB.erase(MBBI);
886  }
887}
888