Thumb1RegisterInfo.cpp revision ab3d00e5350fd4c097e2a5b077da7584692029a7 
1//===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMSubtarget.h"
20#include "Thumb1InstrInfo.h"
21#include "Thumb1RegisterInfo.h"
22#include "llvm/Constants.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
25#include "llvm/LLVMContext.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/Target/TargetFrameInfo.h"
33#include "llvm/Target/TargetMachine.h"
34#include "llvm/ADT/BitVector.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39
40namespace llvm {
41extern cl::opt<bool> ReuseFrameIndexVals;
42}
43
44using namespace llvm;
45
46Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
47                                       const ARMSubtarget &sti)
48  : ARMBaseRegisterInfo(tii, sti) {
49}
50
51/// emitLoadConstPool - Emits a load from constpool to materialize the
52/// specified immediate.
53void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
54                                           MachineBasicBlock::iterator &MBBI,
55                                           DebugLoc dl,
56                                           unsigned DestReg, unsigned SubIdx,
57                                           int Val,
58                                           ARMCC::CondCodes Pred,
59                                           unsigned PredReg) const {
60  MachineFunction &MF = *MBB.getParent();
61  MachineConstantPool *ConstantPool = MF.getConstantPool();
62  const Constant *C = ConstantInt::get(
63          Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
64  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
65
66  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
67          .addReg(DestReg, getDefRegState(true), SubIdx)
68          .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
69}
70
71bool Thumb1RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
72  const MachineFrameInfo *FFI = MF.getFrameInfo();
73  unsigned CFSize = FFI->getMaxCallFrameSize();
74  // It's not always a good idea to include the call frame as part of the
75  // stack frame. ARM (especially Thumb) has small immediate offset to
76  // address the stack frame. So a large call frame can cause poor codegen
77  // and may even makes it impossible to scavenge a register.
78  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
79    return false;
80
81  return !MF.getFrameInfo()->hasVarSizedObjects();
82}
83
84
85/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
86/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
87/// in a register using mov / mvn sequences or load the immediate from a
88/// constpool entry.
89static
90void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
91                              MachineBasicBlock::iterator &MBBI,
92                              unsigned DestReg, unsigned BaseReg,
93                              int NumBytes, bool CanChangeCC,
94                              const TargetInstrInfo &TII,
95                              const ARMBaseRegisterInfo& MRI,
96                              DebugLoc dl) {
97    MachineFunction &MF = *MBB.getParent();
98    bool isHigh = !isARMLowRegister(DestReg) ||
99                  (BaseReg != 0 && !isARMLowRegister(BaseReg));
100    bool isSub = false;
101    // Subtract doesn't have high register version. Load the negative value
102    // if either base or dest register is a high register. Also, if do not
103    // issue sub as part of the sequence if condition register is to be
104    // preserved.
105    if (NumBytes < 0 && !isHigh && CanChangeCC) {
106      isSub = true;
107      NumBytes = -NumBytes;
108    }
109    unsigned LdReg = DestReg;
110    if (DestReg == ARM::SP) {
111      assert(BaseReg == ARM::SP && "Unexpected!");
112      LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
113    }
114
115    if (NumBytes <= 255 && NumBytes >= 0)
116      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
117        .addImm(NumBytes);
118    else if (NumBytes < 0 && NumBytes >= -255) {
119      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
120        .addImm(NumBytes);
121      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
122        .addReg(LdReg, RegState::Kill);
123    } else
124      MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
125
126    // Emit add / sub.
127    int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
128    MachineInstrBuilder MIB =
129      BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
130    if (Opc != ARM::tADDhirr)
131      MIB = AddDefaultT1CC(MIB);
132    if (DestReg == ARM::SP || isSub)
133      MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
134    else
135      MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
136    AddDefaultPred(MIB);
137}
138
139/// calcNumMI - Returns the number of instructions required to materialize
140/// the specific add / sub r, c instruction.
141static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
142                          unsigned NumBits, unsigned Scale) {
143  unsigned NumMIs = 0;
144  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
145
146  if (Opc == ARM::tADDrSPi) {
147    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
148    Bytes -= ThisVal;
149    NumMIs++;
150    NumBits = 8;
151    Scale = 1;  // Followed by a number of tADDi8.
152    Chunk = ((1 << NumBits) - 1) * Scale;
153  }
154
155  NumMIs += Bytes / Chunk;
156  if ((Bytes % Chunk) != 0)
157    NumMIs++;
158  if (ExtraOpc)
159    NumMIs++;
160  return NumMIs;
161}
162
163/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
164/// a destreg = basereg + immediate in Thumb code.
165void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
166                                     MachineBasicBlock::iterator &MBBI,
167                                     unsigned DestReg, unsigned BaseReg,
168                                     int NumBytes, const TargetInstrInfo &TII,
169                                     const ARMBaseRegisterInfo& MRI,
170                                     DebugLoc dl) {
171  bool isSub = NumBytes < 0;
172  unsigned Bytes = (unsigned)NumBytes;
173  if (isSub) Bytes = -NumBytes;
174  bool isMul4 = (Bytes & 3) == 0;
175  bool isTwoAddr = false;
176  bool DstNotEqBase = false;
177  unsigned NumBits = 1;
178  unsigned Scale = 1;
179  int Opc = 0;
180  int ExtraOpc = 0;
181  bool NeedCC = false;
182  bool NeedPred = false;
183
184  if (DestReg == BaseReg && BaseReg == ARM::SP) {
185    assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
186    NumBits = 7;
187    Scale = 4;
188    Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
189    isTwoAddr = true;
190  } else if (!isSub && BaseReg == ARM::SP) {
191    // r1 = add sp, 403
192    // =>
193    // r1 = add sp, 100 * 4
194    // r1 = add r1, 3
195    if (!isMul4) {
196      Bytes &= ~3;
197      ExtraOpc = ARM::tADDi3;
198    }
199    NumBits = 8;
200    Scale = 4;
201    Opc = ARM::tADDrSPi;
202  } else {
203    // sp = sub sp, c
204    // r1 = sub sp, c
205    // r8 = sub sp, c
206    if (DestReg != BaseReg)
207      DstNotEqBase = true;
208    NumBits = 8;
209    if (DestReg == ARM::SP) {
210      Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
211      assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
212      NumBits = 7;
213      Scale = 4;
214    } else {
215      Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
216      NumBits = 8;
217      NeedPred = NeedCC = true;
218    }
219    isTwoAddr = true;
220  }
221
222  unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
223  unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
224  if (NumMIs > Threshold) {
225    // This will expand into too many instructions. Load the immediate from a
226    // constpool entry.
227    emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
228                             MRI, dl);
229    return;
230  }
231
232  if (DstNotEqBase) {
233    if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
234      // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
235      unsigned Chunk = (1 << 3) - 1;
236      unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
237      Bytes -= ThisVal;
238      const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
239      const MachineInstrBuilder MIB =
240        AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
241      AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
242    } else {
243      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
244        .addReg(BaseReg, RegState::Kill);
245    }
246    BaseReg = DestReg;
247  }
248
249  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
250  while (Bytes) {
251    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
252    Bytes -= ThisVal;
253    ThisVal /= Scale;
254    // Build the new tADD / tSUB.
255    if (isTwoAddr) {
256      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
257      if (NeedCC)
258        MIB = AddDefaultT1CC(MIB);
259      MIB .addReg(DestReg).addImm(ThisVal);
260      if (NeedPred)
261        MIB = AddDefaultPred(MIB);
262    }
263    else {
264      bool isKill = BaseReg != ARM::SP;
265      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
266      if (NeedCC)
267        MIB = AddDefaultT1CC(MIB);
268      MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
269      if (NeedPred)
270        MIB = AddDefaultPred(MIB);
271      BaseReg = DestReg;
272
273      if (Opc == ARM::tADDrSPi) {
274        // r4 = add sp, imm
275        // r4 = add r4, imm
276        // ...
277        NumBits = 8;
278        Scale = 1;
279        Chunk = ((1 << NumBits) - 1) * Scale;
280        Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
281        NeedPred = NeedCC = isTwoAddr = true;
282      }
283    }
284  }
285
286  if (ExtraOpc) {
287    const TargetInstrDesc &TID = TII.get(ExtraOpc);
288    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
289                   .addReg(DestReg, RegState::Kill)
290                   .addImm(((unsigned)NumBytes) & 3));
291  }
292}
293
294static void emitSPUpdate(MachineBasicBlock &MBB,
295                         MachineBasicBlock::iterator &MBBI,
296                         const TargetInstrInfo &TII, DebugLoc dl,
297                         const Thumb1RegisterInfo &MRI,
298                         int NumBytes) {
299  emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
300                            MRI, dl);
301}
302
303void Thumb1RegisterInfo::
304eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
305                              MachineBasicBlock::iterator I) const {
306  if (!hasReservedCallFrame(MF)) {
307    // If we have alloca, convert as follows:
308    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
309    // ADJCALLSTACKUP   -> add, sp, sp, amount
310    MachineInstr *Old = I;
311    DebugLoc dl = Old->getDebugLoc();
312    unsigned Amount = Old->getOperand(0).getImm();
313    if (Amount != 0) {
314      // We need to keep the stack aligned properly.  To do this, we round the
315      // amount of space needed for the outgoing arguments up to the next
316      // alignment boundary.
317      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
318      Amount = (Amount+Align-1)/Align*Align;
319
320      // Replace the pseudo instruction with a new instruction...
321      unsigned Opc = Old->getOpcode();
322      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
323        emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
324      } else {
325        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
326        emitSPUpdate(MBB, I, TII, dl, *this, Amount);
327      }
328    }
329  }
330  MBB.erase(I);
331}
332
333/// emitThumbConstant - Emit a series of instructions to materialize a
334/// constant.
335static void emitThumbConstant(MachineBasicBlock &MBB,
336                              MachineBasicBlock::iterator &MBBI,
337                              unsigned DestReg, int Imm,
338                              const TargetInstrInfo &TII,
339                              const Thumb1RegisterInfo& MRI,
340                              DebugLoc dl) {
341  bool isSub = Imm < 0;
342  if (isSub) Imm = -Imm;
343
344  int Chunk = (1 << 8) - 1;
345  int ThisVal = (Imm > Chunk) ? Chunk : Imm;
346  Imm -= ThisVal;
347  AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
348                                        DestReg))
349                 .addImm(ThisVal));
350  if (Imm > 0)
351    emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
352  if (isSub) {
353    const TargetInstrDesc &TID = TII.get(ARM::tRSB);
354    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
355                   .addReg(DestReg, RegState::Kill));
356  }
357}
358
359static void removeOperands(MachineInstr &MI, unsigned i) {
360  unsigned Op = i;
361  for (unsigned e = MI.getNumOperands(); i != e; ++i)
362    MI.RemoveOperand(Op);
363}
364
365bool Thumb1RegisterInfo::
366rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
367                  unsigned FrameReg, int &Offset,
368                  const ARMBaseInstrInfo &TII) const {
369  MachineInstr &MI = *II;
370  MachineBasicBlock &MBB = *MI.getParent();
371  DebugLoc dl = MI.getDebugLoc();
372  unsigned Opcode = MI.getOpcode();
373  const TargetInstrDesc &Desc = MI.getDesc();
374  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
375
376  if (Opcode == ARM::tADDrSPi) {
377    Offset += MI.getOperand(FrameRegIdx+1).getImm();
378
379    // Can't use tADDrSPi if it's based off the frame pointer.
380    unsigned NumBits = 0;
381    unsigned Scale = 1;
382    if (FrameReg != ARM::SP) {
383      Opcode = ARM::tADDi3;
384      MI.setDesc(TII.get(Opcode));
385      NumBits = 3;
386    } else {
387      NumBits = 8;
388      Scale = 4;
389      assert((Offset & 3) == 0 &&
390             "Thumb add/sub sp, #imm immediate must be multiple of 4!");
391    }
392
393    unsigned PredReg;
394    if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
395      // Turn it into a move.
396      MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
397      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
398      // Remove offset and remaining explicit predicate operands.
399      do MI.RemoveOperand(FrameRegIdx+1);
400      while (MI.getNumOperands() > FrameRegIdx+1 &&
401             (!MI.getOperand(FrameRegIdx+1).isReg() ||
402              !MI.getOperand(FrameRegIdx+1).isImm()));
403      return true;
404    }
405
406    // Common case: small offset, fits into instruction.
407    unsigned Mask = (1 << NumBits) - 1;
408    if (((Offset / Scale) & ~Mask) == 0) {
409      // Replace the FrameIndex with sp / fp
410      if (Opcode == ARM::tADDi3) {
411        removeOperands(MI, FrameRegIdx);
412        MachineInstrBuilder MIB(&MI);
413        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
414                       .addImm(Offset / Scale));
415      } else {
416        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
417        MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset / Scale);
418      }
419      return true;
420    }
421
422    unsigned DestReg = MI.getOperand(0).getReg();
423    unsigned Bytes = (Offset > 0) ? Offset : -Offset;
424    unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
425    // MI would expand into a large number of instructions. Don't try to
426    // simplify the immediate.
427    if (NumMIs > 2) {
428      emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
429                                *this, dl);
430      MBB.erase(II);
431      return true;
432    }
433
434    if (Offset > 0) {
435      // Translate r0 = add sp, imm to
436      // r0 = add sp, 255*4
437      // r0 = add r0, (imm - 255*4)
438      if (Opcode == ARM::tADDi3) {
439        removeOperands(MI, FrameRegIdx);
440        MachineInstrBuilder MIB(&MI);
441        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
442      } else {
443        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
444        MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
445      }
446      Offset = (Offset - Mask * Scale);
447      MachineBasicBlock::iterator NII = llvm::next(II);
448      emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
449                                *this, dl);
450    } else {
451      // Translate r0 = add sp, -imm to
452      // r0 = -imm (this is then translated into a series of instructons)
453      // r0 = add r0, sp
454      emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
455
456      MI.setDesc(TII.get(ARM::tADDhirr));
457      MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true);
458      MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false);
459      if (Opcode == ARM::tADDi3) {
460        MachineInstrBuilder MIB(&MI);
461        AddDefaultPred(MIB);
462      }
463    }
464    return true;
465  } else {
466    unsigned ImmIdx = 0;
467    int InstrOffs = 0;
468    unsigned NumBits = 0;
469    unsigned Scale = 1;
470    switch (AddrMode) {
471    case ARMII::AddrModeT1_s: {
472      ImmIdx = FrameRegIdx+1;
473      InstrOffs = MI.getOperand(ImmIdx).getImm();
474      NumBits = (FrameReg == ARM::SP) ? 8 : 5;
475      Scale = 4;
476      break;
477    }
478    default:
479      llvm_unreachable("Unsupported addressing mode!");
480      break;
481    }
482
483    Offset += InstrOffs * Scale;
484    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
485
486    // Common case: small offset, fits into instruction.
487    MachineOperand &ImmOp = MI.getOperand(ImmIdx);
488    int ImmedOffset = Offset / Scale;
489    unsigned Mask = (1 << NumBits) - 1;
490    if ((unsigned)Offset <= Mask * Scale) {
491      // Replace the FrameIndex with sp
492      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
493      ImmOp.ChangeToImmediate(ImmedOffset);
494      return true;
495    }
496
497    bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
498    if (AddrMode == ARMII::AddrModeT1_s) {
499      // Thumb tLDRspi, tSTRspi. These will change to instructions that use
500      // a different base register.
501      NumBits = 5;
502      Mask = (1 << NumBits) - 1;
503    }
504    // If this is a thumb spill / restore, we will be using a constpool load to
505    // materialize the offset.
506    if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
507      ImmOp.ChangeToImmediate(0);
508    else {
509      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
510      ImmedOffset = ImmedOffset & Mask;
511      ImmOp.ChangeToImmediate(ImmedOffset);
512      Offset &= ~(Mask*Scale);
513    }
514  }
515  return Offset == 0;
516}
517
518void
519Thumb1RegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
520                                      unsigned BaseReg, int64_t Offset) const {
521  MachineInstr &MI = *I;
522  int Off = Offset; // ARM doesn't need the general 64-bit offsets
523  unsigned i = 0;
524
525  while (!MI.getOperand(i).isFI()) {
526    ++i;
527    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
528  }
529  bool Done = false;
530  Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
531  assert (Done && "Unable to resolve frame index!");
532}
533
534/// saveScavengerRegister - Spill the register so it can be used by the
535/// register scavenger. Return true.
536bool
537Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
538                                          MachineBasicBlock::iterator I,
539                                          MachineBasicBlock::iterator &UseMI,
540                                          const TargetRegisterClass *RC,
541                                          unsigned Reg) const {
542  // Thumb1 can't use the emergency spill slot on the stack because
543  // ldr/str immediate offsets must be positive, and if we're referencing
544  // off the frame pointer (if, for example, there are alloca() calls in
545  // the function, the offset will be negative. Use R12 instead since that's
546  // a call clobbered register that we know won't be used in Thumb1 mode.
547  DebugLoc DL;
548  BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
549    addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
550
551  // The UseMI is where we would like to restore the register. If there's
552  // interference with R12 before then, however, we'll need to restore it
553  // before that instead and adjust the UseMI.
554  bool done = false;
555  for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
556    if (II->isDebugValue())
557      continue;
558    // If this instruction affects R12, adjust our restore point.
559    for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
560      const MachineOperand &MO = II->getOperand(i);
561      if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
562          TargetRegisterInfo::isVirtualRegister(MO.getReg()))
563        continue;
564      if (MO.getReg() == ARM::R12) {
565        UseMI = II;
566        done = true;
567        break;
568      }
569    }
570  }
571  // Restore the register from R12
572  BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
573    addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill);
574
575  return true;
576}
577
578void
579Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
580                                        int SPAdj, RegScavenger *RS) const {
581  unsigned VReg = 0;
582  unsigned i = 0;
583  MachineInstr &MI = *II;
584  MachineBasicBlock &MBB = *MI.getParent();
585  MachineFunction &MF = *MBB.getParent();
586  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
587  DebugLoc dl = MI.getDebugLoc();
588
589  while (!MI.getOperand(i).isFI()) {
590    ++i;
591    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
592  }
593
594  unsigned FrameReg = ARM::SP;
595  int FrameIndex = MI.getOperand(i).getIndex();
596  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
597               MF.getFrameInfo()->getStackSize() + SPAdj;
598
599  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
600    Offset -= AFI->getGPRCalleeSavedArea1Offset();
601  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
602    Offset -= AFI->getGPRCalleeSavedArea2Offset();
603  else if (MF.getFrameInfo()->hasVarSizedObjects()) {
604    assert(SPAdj == 0 && hasFP(MF) && "Unexpected");
605    // There are alloca()'s in this function, must reference off the frame
606    // pointer or base pointer instead.
607    if (!hasBasePointer(MF)) {
608      FrameReg = getFrameRegister(MF);
609      Offset -= AFI->getFramePtrSpillOffset();
610    } else
611      FrameReg = BasePtr;
612  }
613
614  // Special handling of dbg_value instructions.
615  if (MI.isDebugValue()) {
616    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
617    MI.getOperand(i+1).ChangeToImmediate(Offset);
618    return;
619  }
620
621  // Modify MI as necessary to handle as much of 'Offset' as possible
622  assert(AFI->isThumbFunction() &&
623         "This eliminateFrameIndex only supports Thumb1!");
624  if (rewriteFrameIndex(MI, i, FrameReg, Offset, TII))
625    return;
626
627  // If we get here, the immediate doesn't fit into the instruction.  We folded
628  // as much as possible above, handle the rest, providing a register that is
629  // SP+LargeImm.
630  assert(Offset && "This code isn't needed if offset already handled!");
631
632  unsigned Opcode = MI.getOpcode();
633  const TargetInstrDesc &Desc = MI.getDesc();
634
635  // Remove predicate first.
636  int PIdx = MI.findFirstPredOperandIdx();
637  if (PIdx != -1)
638    removeOperands(MI, PIdx);
639
640  if (Desc.mayLoad()) {
641    // Use the destination register to materialize sp + offset.
642    unsigned TmpReg = MI.getOperand(0).getReg();
643    bool UseRR = false;
644    if (Opcode == ARM::tRestore) {
645      if (FrameReg == ARM::SP)
646        emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
647                                 Offset, false, TII, *this, dl);
648      else {
649        emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
650        UseRR = true;
651      }
652    } else {
653      emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
654                                *this, dl);
655    }
656
657    MI.setDesc(TII.get(ARM::tLDR));
658    MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
659    if (UseRR)
660      // Use [reg, reg] addrmode.
661      MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
662    else  // tLDR has an extra register operand.
663      MI.addOperand(MachineOperand::CreateReg(0, false));
664  } else if (Desc.mayStore()) {
665      VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
666      bool UseRR = false;
667
668      if (Opcode == ARM::tSpill) {
669        if (FrameReg == ARM::SP)
670          emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
671                                   Offset, false, TII, *this, dl);
672        else {
673          emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
674          UseRR = true;
675        }
676      } else
677        emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
678                                  *this, dl);
679      MI.setDesc(TII.get(ARM::tSTR));
680      MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
681      if (UseRR)  // Use [reg, reg] addrmode.
682        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
683      else // tSTR has an extra register operand.
684        MI.addOperand(MachineOperand::CreateReg(0, false));
685  } else
686    assert(false && "Unexpected opcode!");
687
688  // Add predicate back if it's needed.
689  if (MI.getDesc().isPredicable()) {
690    MachineInstrBuilder MIB(&MI);
691    AddDefaultPred(MIB);
692  }
693}
694
695void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
696  MachineBasicBlock &MBB = MF.front();
697  MachineBasicBlock::iterator MBBI = MBB.begin();
698  MachineFrameInfo  *MFI = MF.getFrameInfo();
699  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
700  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
701  unsigned NumBytes = MFI->getStackSize();
702  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
703  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
704
705  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
706  NumBytes = (NumBytes + 3) & ~3;
707  MFI->setStackSize(NumBytes);
708
709  // Determine the sizes of each callee-save spill areas and record which frame
710  // belongs to which callee-save spill areas.
711  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
712  int FramePtrSpillFI = 0;
713
714  if (VARegSaveSize)
715    emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
716
717  if (!AFI->hasStackFrame()) {
718    if (NumBytes != 0)
719      emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
720    return;
721  }
722
723  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
724    unsigned Reg = CSI[i].getReg();
725    int FI = CSI[i].getFrameIdx();
726    switch (Reg) {
727    case ARM::R4:
728    case ARM::R5:
729    case ARM::R6:
730    case ARM::R7:
731    case ARM::LR:
732      if (Reg == FramePtr)
733        FramePtrSpillFI = FI;
734      AFI->addGPRCalleeSavedArea1Frame(FI);
735      GPRCS1Size += 4;
736      break;
737    case ARM::R8:
738    case ARM::R9:
739    case ARM::R10:
740    case ARM::R11:
741      if (Reg == FramePtr)
742        FramePtrSpillFI = FI;
743      if (STI.isTargetDarwin()) {
744        AFI->addGPRCalleeSavedArea2Frame(FI);
745        GPRCS2Size += 4;
746      } else {
747        AFI->addGPRCalleeSavedArea1Frame(FI);
748        GPRCS1Size += 4;
749      }
750      break;
751    default:
752      AFI->addDPRCalleeSavedAreaFrame(FI);
753      DPRCSSize += 8;
754    }
755  }
756
757  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
758    ++MBBI;
759    if (MBBI != MBB.end())
760      dl = MBBI->getDebugLoc();
761  }
762
763  // Adjust FP so it point to the stack slot that contains the previous FP.
764  if (hasFP(MF)) {
765    BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
766      .addFrameIndex(FramePtrSpillFI).addImm(0);
767    AFI->setShouldRestoreSPFromFP(true);
768  }
769
770  // Determine starting offsets of spill areas.
771  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
772  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
773  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
774  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
775  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
776  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
777  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
778
779  NumBytes = DPRCSOffset;
780  if (NumBytes) {
781    // Insert it after all the callee-save spills.
782    emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
783  }
784
785  if (STI.isTargetELF() && hasFP(MF))
786    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
787                             AFI->getFramePtrSpillOffset());
788
789  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
790  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
791  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
792
793  // If we need a base pointer, set it up here. It's whatever the value
794  // of the stack pointer is at this point. Any variable size objects
795  // will be allocated after this, so we can still use the base pointer
796  // to reference locals.
797  if (hasBasePointer(MF))
798    BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr).addReg(ARM::SP);
799}
800
801static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
802  for (unsigned i = 0; CSRegs[i]; ++i)
803    if (Reg == CSRegs[i])
804      return true;
805  return false;
806}
807
808static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
809  if (MI->getOpcode() == ARM::tRestore &&
810      MI->getOperand(1).isFI() &&
811      isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
812    return true;
813  else if (MI->getOpcode() == ARM::tPOP) {
814    // The first two operands are predicates. The last two are
815    // imp-def and imp-use of SP. Check everything in between.
816    for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
817      if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
818        return false;
819    return true;
820  }
821  return false;
822}
823
824void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
825                                      MachineBasicBlock &MBB) const {
826  MachineBasicBlock::iterator MBBI = prior(MBB.end());
827  assert((MBBI->getOpcode() == ARM::tBX_RET ||
828          MBBI->getOpcode() == ARM::tPOP_RET) &&
829         "Can only insert epilog into returning blocks");
830  DebugLoc dl = MBBI->getDebugLoc();
831  MachineFrameInfo *MFI = MF.getFrameInfo();
832  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
833  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
834  int NumBytes = (int)MFI->getStackSize();
835  const unsigned *CSRegs = getCalleeSavedRegs();
836
837  if (!AFI->hasStackFrame()) {
838    if (NumBytes != 0)
839      emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
840  } else {
841    // Unwind MBBI to point to first LDR / VLDRD.
842    if (MBBI != MBB.begin()) {
843      do
844        --MBBI;
845      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
846      if (!isCSRestore(MBBI, CSRegs))
847        ++MBBI;
848    }
849
850    // Move SP to start of FP callee save spill area.
851    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
852                 AFI->getGPRCalleeSavedArea2Size() +
853                 AFI->getDPRCalleeSavedAreaSize());
854
855    if (AFI->shouldRestoreSPFromFP()) {
856      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
857      // Reset SP based on frame pointer only if the stack frame extends beyond
858      // frame pointer stack slot or target is ELF and the function has FP.
859      if (NumBytes)
860        emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
861                                  TII, *this, dl);
862      else
863        BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
864          .addReg(FramePtr);
865    } else {
866      if (MBBI->getOpcode() == ARM::tBX_RET &&
867          &MBB.front() != MBBI &&
868          prior(MBBI)->getOpcode() == ARM::tPOP) {
869        MachineBasicBlock::iterator PMBBI = prior(MBBI);
870        emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
871      } else
872        emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
873    }
874  }
875
876  if (VARegSaveSize) {
877    // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
878    // to LR, and we can't pop the value directly to the PC since
879    // we need to update the SP after popping the value. Therefore, we
880    // pop the old LR into R3 as a temporary.
881
882    // Move back past the callee-saved register restoration
883    while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
884      ++MBBI;
885    // Epilogue for vararg functions: pop LR to R3 and branch off it.
886    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
887      .addReg(ARM::R3, RegState::Define);
888
889    emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
890
891    BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
892      .addReg(ARM::R3, RegState::Kill);
893    // erase the old tBX_RET instruction
894    MBB.erase(MBBI);
895  }
896}
897