1//===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Thumb2InstrInfo.h"
15#include "ARMConstantPoolValue.h"
16#include "ARMMachineFunctionInfo.h"
17#include "MCTargetDesc/ARMAddressingModes.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineMemOperand.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/Support/CommandLine.h"
24
25using namespace llvm;
26
27static cl::opt<bool>
28OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
29           cl::desc("Use old-style Thumb2 if-conversion heuristics"),
30           cl::init(false));
31
32Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
33  : ARMBaseInstrInfo(STI), RI(STI) {
34}
35
36/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
37void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
38  NopInst.setOpcode(ARM::tHINT);
39  NopInst.addOperand(MCOperand::CreateImm(0));
40  NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
41  NopInst.addOperand(MCOperand::CreateReg(0));
42}
43
44unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
45  // FIXME
46  return 0;
47}
48
49void
50Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
51                                         MachineBasicBlock *NewDest) const {
52  MachineBasicBlock *MBB = Tail->getParent();
53  ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
54  if (!AFI->hasITBlocks()) {
55    TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
56    return;
57  }
58
59  // If the first instruction of Tail is predicated, we may have to update
60  // the IT instruction.
61  unsigned PredReg = 0;
62  ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
63  MachineBasicBlock::iterator MBBI = Tail;
64  if (CC != ARMCC::AL)
65    // Expecting at least the t2IT instruction before it.
66    --MBBI;
67
68  // Actually replace the tail.
69  TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
70
71  // Fix up IT.
72  if (CC != ARMCC::AL) {
73    MachineBasicBlock::iterator E = MBB->begin();
74    unsigned Count = 4; // At most 4 instructions in an IT block.
75    while (Count && MBBI != E) {
76      if (MBBI->isDebugValue()) {
77        --MBBI;
78        continue;
79      }
80      if (MBBI->getOpcode() == ARM::t2IT) {
81        unsigned Mask = MBBI->getOperand(1).getImm();
82        if (Count == 4)
83          MBBI->eraseFromParent();
84        else {
85          unsigned MaskOn = 1 << Count;
86          unsigned MaskOff = ~(MaskOn - 1);
87          MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
88        }
89        return;
90      }
91      --MBBI;
92      --Count;
93    }
94
95    // Ctrl flow can reach here if branch folding is run before IT block
96    // formation pass.
97  }
98}
99
100bool
101Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
102                                     MachineBasicBlock::iterator MBBI) const {
103  while (MBBI->isDebugValue()) {
104    ++MBBI;
105    if (MBBI == MBB.end())
106      return false;
107  }
108
109  unsigned PredReg = 0;
110  return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
111}
112
113void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
114                                  MachineBasicBlock::iterator I, DebugLoc DL,
115                                  unsigned DestReg, unsigned SrcReg,
116                                  bool KillSrc) const {
117  // Handle SPR, DPR, and QPR copies.
118  if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
119    return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
120
121  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
122    .addReg(SrcReg, getKillRegState(KillSrc)));
123}
124
125void Thumb2InstrInfo::
126storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
127                    unsigned SrcReg, bool isKill, int FI,
128                    const TargetRegisterClass *RC,
129                    const TargetRegisterInfo *TRI) const {
130  DebugLoc DL;
131  if (I != MBB.end()) DL = I->getDebugLoc();
132
133  MachineFunction &MF = *MBB.getParent();
134  MachineFrameInfo &MFI = *MF.getFrameInfo();
135  MachineMemOperand *MMO =
136    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
137                            MachineMemOperand::MOStore,
138                            MFI.getObjectSize(FI),
139                            MFI.getObjectAlignment(FI));
140
141  if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
142      RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
143      RC == &ARM::GPRnopcRegClass) {
144    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
145                   .addReg(SrcReg, getKillRegState(isKill))
146                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
147    return;
148  }
149
150  if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
151    // Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
152    // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
153    // otherwise).
154    MachineRegisterInfo *MRI = &MF.getRegInfo();
155    MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
156
157    MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
158    AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
159    AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
160    MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
161    AddDefaultPred(MIB);
162    return;
163  }
164
165  ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
166}
167
168void Thumb2InstrInfo::
169loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
170                     unsigned DestReg, int FI,
171                     const TargetRegisterClass *RC,
172                     const TargetRegisterInfo *TRI) const {
173  MachineFunction &MF = *MBB.getParent();
174  MachineFrameInfo &MFI = *MF.getFrameInfo();
175  MachineMemOperand *MMO =
176    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
177                            MachineMemOperand::MOLoad,
178                            MFI.getObjectSize(FI),
179                            MFI.getObjectAlignment(FI));
180  DebugLoc DL;
181  if (I != MBB.end()) DL = I->getDebugLoc();
182
183  if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
184      RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
185      RC == &ARM::GPRnopcRegClass) {
186    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
187                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
188    return;
189  }
190
191  if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
192    // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
193    // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
194    // otherwise).
195    MachineRegisterInfo *MRI = &MF.getRegInfo();
196    MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
197
198    MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
199    AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200    AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
201    MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
202    AddDefaultPred(MIB);
203
204    if (TargetRegisterInfo::isPhysicalRegister(DestReg))
205      MIB.addReg(DestReg, RegState::ImplicitDefine);
206    return;
207  }
208
209  ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
210}
211
212void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
213                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
214                               unsigned DestReg, unsigned BaseReg, int NumBytes,
215                               ARMCC::CondCodes Pred, unsigned PredReg,
216                               const ARMBaseInstrInfo &TII, unsigned MIFlags) {
217  if (NumBytes == 0 && DestReg != BaseReg) {
218    BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
219      .addReg(BaseReg, RegState::Kill)
220      .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
221    return;
222  }
223
224  bool isSub = NumBytes < 0;
225  if (isSub) NumBytes = -NumBytes;
226
227  // If profitable, use a movw or movt to materialize the offset.
228  // FIXME: Use the scavenger to grab a scratch register.
229  if (DestReg != ARM::SP && DestReg != BaseReg &&
230      NumBytes >= 4096 &&
231      ARM_AM::getT2SOImmVal(NumBytes) == -1) {
232    bool Fits = false;
233    if (NumBytes < 65536) {
234      // Use a movw to materialize the 16-bit constant.
235      BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
236        .addImm(NumBytes)
237        .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
238      Fits = true;
239    } else if ((NumBytes & 0xffff) == 0) {
240      // Use a movt to materialize the 32-bit constant.
241      BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
242        .addReg(DestReg)
243        .addImm(NumBytes >> 16)
244        .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
245      Fits = true;
246    }
247
248    if (Fits) {
249      if (isSub) {
250        BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
251          .addReg(BaseReg, RegState::Kill)
252          .addReg(DestReg, RegState::Kill)
253          .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
254          .setMIFlags(MIFlags);
255      } else {
256        BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
257          .addReg(DestReg, RegState::Kill)
258          .addReg(BaseReg, RegState::Kill)
259          .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
260          .setMIFlags(MIFlags);
261      }
262      return;
263    }
264  }
265
266  while (NumBytes) {
267    unsigned ThisVal = NumBytes;
268    unsigned Opc = 0;
269    if (DestReg == ARM::SP && BaseReg != ARM::SP) {
270      // mov sp, rn. Note t2MOVr cannot be used.
271      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
272        .addReg(BaseReg).setMIFlags(MIFlags));
273      BaseReg = ARM::SP;
274      continue;
275    }
276
277    bool HasCCOut = true;
278    if (BaseReg == ARM::SP) {
279      // sub sp, sp, #imm7
280      if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
281        assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
282        Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
283        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
284          .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
285        NumBytes = 0;
286        continue;
287      }
288
289      // sub rd, sp, so_imm
290      Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
291      if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
292        NumBytes = 0;
293      } else {
294        // FIXME: Move this to ARMAddressingModes.h?
295        unsigned RotAmt = countLeadingZeros(ThisVal);
296        ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
297        NumBytes &= ~ThisVal;
298        assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
299               "Bit extraction didn't work?");
300      }
301    } else {
302      assert(DestReg != ARM::SP && BaseReg != ARM::SP);
303      Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
304      if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
305        NumBytes = 0;
306      } else if (ThisVal < 4096) {
307        Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
308        HasCCOut = false;
309        NumBytes = 0;
310      } else {
311        // FIXME: Move this to ARMAddressingModes.h?
312        unsigned RotAmt = countLeadingZeros(ThisVal);
313        ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
314        NumBytes &= ~ThisVal;
315        assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
316               "Bit extraction didn't work?");
317      }
318    }
319
320    // Build the new ADD / SUB.
321    MachineInstrBuilder MIB =
322      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
323                     .addReg(BaseReg, RegState::Kill)
324                     .addImm(ThisVal)).setMIFlags(MIFlags);
325    if (HasCCOut)
326      AddDefaultCC(MIB);
327
328    BaseReg = DestReg;
329  }
330}
331
332static unsigned
333negativeOffsetOpcode(unsigned opcode)
334{
335  switch (opcode) {
336  case ARM::t2LDRi12:   return ARM::t2LDRi8;
337  case ARM::t2LDRHi12:  return ARM::t2LDRHi8;
338  case ARM::t2LDRBi12:  return ARM::t2LDRBi8;
339  case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
340  case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
341  case ARM::t2STRi12:   return ARM::t2STRi8;
342  case ARM::t2STRBi12:  return ARM::t2STRBi8;
343  case ARM::t2STRHi12:  return ARM::t2STRHi8;
344  case ARM::t2PLDi12:   return ARM::t2PLDi8;
345
346  case ARM::t2LDRi8:
347  case ARM::t2LDRHi8:
348  case ARM::t2LDRBi8:
349  case ARM::t2LDRSHi8:
350  case ARM::t2LDRSBi8:
351  case ARM::t2STRi8:
352  case ARM::t2STRBi8:
353  case ARM::t2STRHi8:
354  case ARM::t2PLDi8:
355    return opcode;
356
357  default:
358    break;
359  }
360
361  return 0;
362}
363
364static unsigned
365positiveOffsetOpcode(unsigned opcode)
366{
367  switch (opcode) {
368  case ARM::t2LDRi8:   return ARM::t2LDRi12;
369  case ARM::t2LDRHi8:  return ARM::t2LDRHi12;
370  case ARM::t2LDRBi8:  return ARM::t2LDRBi12;
371  case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
372  case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
373  case ARM::t2STRi8:   return ARM::t2STRi12;
374  case ARM::t2STRBi8:  return ARM::t2STRBi12;
375  case ARM::t2STRHi8:  return ARM::t2STRHi12;
376  case ARM::t2PLDi8:   return ARM::t2PLDi12;
377
378  case ARM::t2LDRi12:
379  case ARM::t2LDRHi12:
380  case ARM::t2LDRBi12:
381  case ARM::t2LDRSHi12:
382  case ARM::t2LDRSBi12:
383  case ARM::t2STRi12:
384  case ARM::t2STRBi12:
385  case ARM::t2STRHi12:
386  case ARM::t2PLDi12:
387    return opcode;
388
389  default:
390    break;
391  }
392
393  return 0;
394}
395
396static unsigned
397immediateOffsetOpcode(unsigned opcode)
398{
399  switch (opcode) {
400  case ARM::t2LDRs:   return ARM::t2LDRi12;
401  case ARM::t2LDRHs:  return ARM::t2LDRHi12;
402  case ARM::t2LDRBs:  return ARM::t2LDRBi12;
403  case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
404  case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
405  case ARM::t2STRs:   return ARM::t2STRi12;
406  case ARM::t2STRBs:  return ARM::t2STRBi12;
407  case ARM::t2STRHs:  return ARM::t2STRHi12;
408  case ARM::t2PLDs:   return ARM::t2PLDi12;
409
410  case ARM::t2LDRi12:
411  case ARM::t2LDRHi12:
412  case ARM::t2LDRBi12:
413  case ARM::t2LDRSHi12:
414  case ARM::t2LDRSBi12:
415  case ARM::t2STRi12:
416  case ARM::t2STRBi12:
417  case ARM::t2STRHi12:
418  case ARM::t2PLDi12:
419  case ARM::t2LDRi8:
420  case ARM::t2LDRHi8:
421  case ARM::t2LDRBi8:
422  case ARM::t2LDRSHi8:
423  case ARM::t2LDRSBi8:
424  case ARM::t2STRi8:
425  case ARM::t2STRBi8:
426  case ARM::t2STRHi8:
427  case ARM::t2PLDi8:
428    return opcode;
429
430  default:
431    break;
432  }
433
434  return 0;
435}
436
437bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
438                               unsigned FrameReg, int &Offset,
439                               const ARMBaseInstrInfo &TII) {
440  unsigned Opcode = MI.getOpcode();
441  const MCInstrDesc &Desc = MI.getDesc();
442  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
443  bool isSub = false;
444
445  // Memory operands in inline assembly always use AddrModeT2_i12.
446  if (Opcode == ARM::INLINEASM)
447    AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
448
449  if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
450    Offset += MI.getOperand(FrameRegIdx+1).getImm();
451
452    unsigned PredReg;
453    if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
454      // Turn it into a move.
455      MI.setDesc(TII.get(ARM::tMOVr));
456      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
457      // Remove offset and remaining explicit predicate operands.
458      do MI.RemoveOperand(FrameRegIdx+1);
459      while (MI.getNumOperands() > FrameRegIdx+1);
460      MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
461      AddDefaultPred(MIB);
462      return true;
463    }
464
465    bool HasCCOut = Opcode != ARM::t2ADDri12;
466
467    if (Offset < 0) {
468      Offset = -Offset;
469      isSub = true;
470      MI.setDesc(TII.get(ARM::t2SUBri));
471    } else {
472      MI.setDesc(TII.get(ARM::t2ADDri));
473    }
474
475    // Common case: small offset, fits into instruction.
476    if (ARM_AM::getT2SOImmVal(Offset) != -1) {
477      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
478      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
479      // Add cc_out operand if the original instruction did not have one.
480      if (!HasCCOut)
481        MI.addOperand(MachineOperand::CreateReg(0, false));
482      Offset = 0;
483      return true;
484    }
485    // Another common case: imm12.
486    if (Offset < 4096 &&
487        (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
488      unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
489      MI.setDesc(TII.get(NewOpc));
490      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
491      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
492      // Remove the cc_out operand.
493      if (HasCCOut)
494        MI.RemoveOperand(MI.getNumOperands()-1);
495      Offset = 0;
496      return true;
497    }
498
499    // Otherwise, extract 8 adjacent bits from the immediate into this
500    // t2ADDri/t2SUBri.
501    unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
502    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
503
504    // We will handle these bits from offset, clear them.
505    Offset &= ~ThisImmVal;
506
507    assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
508           "Bit extraction didn't work?");
509    MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
510    // Add cc_out operand if the original instruction did not have one.
511    if (!HasCCOut)
512      MI.addOperand(MachineOperand::CreateReg(0, false));
513
514  } else {
515
516    // AddrMode4 and AddrMode6 cannot handle any offset.
517    if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
518      return false;
519
520    // AddrModeT2_so cannot handle any offset. If there is no offset
521    // register then we change to an immediate version.
522    unsigned NewOpc = Opcode;
523    if (AddrMode == ARMII::AddrModeT2_so) {
524      unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
525      if (OffsetReg != 0) {
526        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
527        return Offset == 0;
528      }
529
530      MI.RemoveOperand(FrameRegIdx+1);
531      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
532      NewOpc = immediateOffsetOpcode(Opcode);
533      AddrMode = ARMII::AddrModeT2_i12;
534    }
535
536    unsigned NumBits = 0;
537    unsigned Scale = 1;
538    if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
539      // i8 supports only negative, and i12 supports only positive, so
540      // based on Offset sign convert Opcode to the appropriate
541      // instruction
542      Offset += MI.getOperand(FrameRegIdx+1).getImm();
543      if (Offset < 0) {
544        NewOpc = negativeOffsetOpcode(Opcode);
545        NumBits = 8;
546        isSub = true;
547        Offset = -Offset;
548      } else {
549        NewOpc = positiveOffsetOpcode(Opcode);
550        NumBits = 12;
551      }
552    } else if (AddrMode == ARMII::AddrMode5) {
553      // VFP address mode.
554      const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
555      int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
556      if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
557        InstrOffs *= -1;
558      NumBits = 8;
559      Scale = 4;
560      Offset += InstrOffs * 4;
561      assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
562      if (Offset < 0) {
563        Offset = -Offset;
564        isSub = true;
565      }
566    } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
567      Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
568      NumBits = 8;
569      // MCInst operand has already scaled value.
570      Scale = 1;
571      if (Offset < 0) {
572        isSub = true;
573        Offset = -Offset;
574      }
575    } else {
576      llvm_unreachable("Unsupported addressing mode!");
577    }
578
579    if (NewOpc != Opcode)
580      MI.setDesc(TII.get(NewOpc));
581
582    MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
583
584    // Attempt to fold address computation
585    // Common case: small offset, fits into instruction.
586    int ImmedOffset = Offset / Scale;
587    unsigned Mask = (1 << NumBits) - 1;
588    if ((unsigned)Offset <= Mask * Scale) {
589      // Replace the FrameIndex with fp/sp
590      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
591      if (isSub) {
592        if (AddrMode == ARMII::AddrMode5)
593          // FIXME: Not consistent.
594          ImmedOffset |= 1 << NumBits;
595        else
596          ImmedOffset = -ImmedOffset;
597      }
598      ImmOp.ChangeToImmediate(ImmedOffset);
599      Offset = 0;
600      return true;
601    }
602
603    // Otherwise, offset doesn't fit. Pull in what we can to simplify
604    ImmedOffset = ImmedOffset & Mask;
605    if (isSub) {
606      if (AddrMode == ARMII::AddrMode5)
607        // FIXME: Not consistent.
608        ImmedOffset |= 1 << NumBits;
609      else {
610        ImmedOffset = -ImmedOffset;
611        if (ImmedOffset == 0)
612          // Change the opcode back if the encoded offset is zero.
613          MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
614      }
615    }
616    ImmOp.ChangeToImmediate(ImmedOffset);
617    Offset &= ~(Mask*Scale);
618  }
619
620  Offset = (isSub) ? -Offset : Offset;
621  return Offset == 0;
622}
623
624ARMCC::CondCodes
625llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
626  unsigned Opc = MI->getOpcode();
627  if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
628    return ARMCC::AL;
629  return getInstrPredicate(MI, PredReg);
630}
631