Thumb2InstrInfo.h revision 4d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855 
1//===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef THUMB2INSTRUCTIONINFO_H
15#define THUMB2INSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "ARM.h"
19#include "ARMInstrInfo.h"
20#include "Thumb2RegisterInfo.h"
21
22namespace llvm {
23class ARMSubtarget;
24class ScheduleHazardRecognizer;
25
26class Thumb2InstrInfo : public ARMBaseInstrInfo {
27  Thumb2RegisterInfo RI;
28public:
29  explicit Thumb2InstrInfo(const ARMSubtarget &STI);
30
31  // Return the non-pre/post incrementing version of 'Opc'. Return 0
32  // if there is not such an opcode.
33  unsigned getUnindexedOpcode(unsigned Opc) const;
34
35  void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
36                               MachineBasicBlock *NewDest) const;
37
38  bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
39                           MachineBasicBlock::iterator MBBI) const;
40
41  bool copyRegToReg(MachineBasicBlock &MBB,
42                    MachineBasicBlock::iterator I,
43                    unsigned DestReg, unsigned SrcReg,
44                    const TargetRegisterClass *DestRC,
45                    const TargetRegisterClass *SrcRC,
46                    DebugLoc DL) const;
47
48  void storeRegToStackSlot(MachineBasicBlock &MBB,
49                           MachineBasicBlock::iterator MBBI,
50                           unsigned SrcReg, bool isKill, int FrameIndex,
51                           const TargetRegisterClass *RC,
52                           const TargetRegisterInfo *TRI) const;
53
54  void loadRegFromStackSlot(MachineBasicBlock &MBB,
55                            MachineBasicBlock::iterator MBBI,
56                            unsigned DestReg, int FrameIndex,
57                            const TargetRegisterClass *RC,
58                            const TargetRegisterInfo *TRI) const;
59
60  /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
61  /// two-addrss instruction inserted by two-address pass.
62  void scheduleTwoAddrSource(MachineInstr *SrcMI, MachineInstr *UseMI,
63                             const TargetRegisterInfo &TRI) const;
64
65  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
66  /// such, whenever a client has an instance of instruction info, it should
67  /// always be able to get register info as well (through this method).
68  ///
69  const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
70
71  ScheduleHazardRecognizer *
72  CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const;
73};
74
75/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
76/// to llvm::getInstrPredicate except it returns AL for conditional branch
77/// instructions which are "predicated", but are not in IT blocks.
78ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
79
80
81}
82
83#endif // THUMB2INSTRUCTIONINFO_H
84