HexagonISelLowering.h revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 
1//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Hexagon uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef Hexagon_ISELLOWERING_H
16#define Hexagon_ISELLOWERING_H
17
18#include "Hexagon.h"
19#include "llvm/CodeGen/CallingConvLower.h"
20#include "llvm/IR/CallingConv.h"
21#include "llvm/Target/TargetLowering.h"
22
23namespace llvm {
24  namespace HexagonISD {
25    enum {
26      FIRST_NUMBER = ISD::BUILTIN_OP_END,
27
28      CONST32,
29      CONST32_GP,  // For marking data present in GP.
30      CONST32_Int_Real,
31      FCONST32,
32      SETCC,
33      ADJDYNALLOC,
34      ARGEXTEND,
35
36      CMPICC,      // Compare two GPR operands, set icc.
37      CMPFCC,      // Compare two FP operands, set fcc.
38      BRICC,       // Branch to dest on icc condition
39      BRFCC,       // Branch to dest on fcc condition
40      SELECT_ICC,  // Select between two values using the current ICC flags.
41      SELECT_FCC,  // Select between two values using the current FCC flags.
42
43      Hi, Lo,      // Hi/Lo operations, typically on a global address.
44
45      FTOI,        // FP to Int within a FP register.
46      ITOF,        // Int to FP within a FP register.
47
48      CALL,        // A call instruction.
49      RET_FLAG,    // Return with a flag operand.
50      BR_JT,       // Jump table.
51      BARRIER,     // Memory barrier.
52      WrapperJT,
53      WrapperCP,
54      WrapperCombineII,
55      WrapperCombineRR,
56      WrapperCombineRI_V4,
57      WrapperCombineIR_V4,
58      WrapperPackhl,
59      WrapperSplatB,
60      WrapperSplatH,
61      WrapperShuffEB,
62      WrapperShuffEH,
63      WrapperShuffOB,
64      WrapperShuffOH,
65      TC_RETURN,
66      EH_RETURN
67    };
68  }
69
70  class HexagonTargetLowering : public TargetLowering {
71    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
72
73    bool CanReturnSmallStruct(const Function* CalleeFn,
74                              unsigned& RetSize) const;
75
76  public:
77    const TargetMachine &TM;
78    explicit HexagonTargetLowering(const TargetMachine &targetmachine);
79
80    /// IsEligibleForTailCallOptimization - Check whether the call is eligible
81    /// for tail call optimization. Targets which want to do tail call
82    /// optimization should implement this function.
83    bool
84    IsEligibleForTailCallOptimization(SDValue Callee,
85                                      CallingConv::ID CalleeCC,
86                                      bool isVarArg,
87                                      bool isCalleeStructRet,
88                                      bool isCallerStructRet,
89                                      const
90                                      SmallVectorImpl<ISD::OutputArg> &Outs,
91                                      const SmallVectorImpl<SDValue> &OutVals,
92                                      const SmallVectorImpl<ISD::InputArg> &Ins,
93                                      SelectionDAG& DAG) const;
94
95    bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
96    bool isTruncateFree(EVT VT1, EVT VT2) const override;
97
98    bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
99
100    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
101
102    const char *getTargetNodeName(unsigned Opcode) const override;
103    SDValue  LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
104    SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
105    SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
106    SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
107    SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
108    SDValue LowerFormalArguments(SDValue Chain,
109                                 CallingConv::ID CallConv, bool isVarArg,
110                                 const SmallVectorImpl<ISD::InputArg> &Ins,
111                                 SDLoc dl, SelectionDAG &DAG,
112                                 SmallVectorImpl<SDValue> &InVals) const override;
113    SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
114    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
115
116    SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
117                      SmallVectorImpl<SDValue> &InVals) const override;
118
119    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
120                            CallingConv::ID CallConv, bool isVarArg,
121                            const SmallVectorImpl<ISD::InputArg> &Ins,
122                            SDLoc dl, SelectionDAG &DAG,
123                            SmallVectorImpl<SDValue> &InVals,
124                            const SmallVectorImpl<SDValue> &OutVals,
125                            SDValue Callee) const;
126
127    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
128    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
129    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
130
131    SDValue LowerReturn(SDValue Chain,
132                        CallingConv::ID CallConv, bool isVarArg,
133                        const SmallVectorImpl<ISD::OutputArg> &Outs,
134                        const SmallVectorImpl<SDValue> &OutVals,
135                        SDLoc dl, SelectionDAG &DAG) const override;
136
137    MachineBasicBlock *
138    EmitInstrWithCustomInserter(MachineInstr *MI,
139                                MachineBasicBlock *BB) const override;
140
141    SDValue  LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
142    SDValue  LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
143    EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
144      if (!VT.isVector())
145        return MVT::i1;
146      else
147        return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
148    }
149
150    bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
151                                    SDValue &Base, SDValue &Offset,
152                                    ISD::MemIndexedMode &AM,
153                                    SelectionDAG &DAG) const override;
154
155    std::pair<unsigned, const TargetRegisterClass*>
156    getRegForInlineAsmConstraint(const std::string &Constraint,
157                                 MVT VT) const override;
158
159    // Intrinsics
160    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
161    /// isLegalAddressingMode - Return true if the addressing mode represented
162    /// by AM is legal for this target, for a load/store of the specified type.
163    /// The type may be VoidTy, in which case only return true if the addressing
164    /// mode is legal for a load/store of any legal type.
165    /// TODO: Handle pre/postinc as well.
166    bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
167    bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
168
169    /// isLegalICmpImmediate - Return true if the specified immediate is legal
170    /// icmp immediate, that is the target has icmp instructions which can
171    /// compare a register against the immediate without having to materialize
172    /// the immediate into a register.
173    bool isLegalICmpImmediate(int64_t Imm) const override;
174  };
175} // end namespace llvm
176
177#endif    // Hexagon_ISELLOWERING_H
178